coreboot-gerrit May 2020

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Change in coreboot[master]: soc/intel/skl: always enable SataPwrOptEnable
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40877 ) Change subject: soc/intel/skl: always enable SataPwrOptEnable ...................................................................... Uploaded patch set 3. -- To view, visit https://review.coreboot.org/c/coreboot/+/40877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Gerrit-Change-Number: 40877 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pena Galvão <mragalvao(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 May 2020 15:07:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: always enable SataPwrOptEnable
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Hello build bot (Jenkins), Patrick Georgi, Angel Pena Galvão, Matt DeVillier, Jeremy Soller, Paul Menzel, Subrata Banik, Youness Alaoui, Aamir Bohra, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Swift Geek (Sebastian Grzywna), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40877 to look at the new patch set (#3). Change subject: soc/intel/skl: always enable SataPwrOptEnable ...................................................................... soc/intel/skl: always enable SataPwrOptEnable For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default. This leads to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "Unaligned Write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable staticly. There is no valid reason to provide an option for breaking coreboot, anyway. Surprisingly cml and cnl are not affected, even though they share mostly the same reference code in this regard. Thus, only skl gets changed. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 5 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/40877/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/40877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Gerrit-Change-Number: 40877 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pena Galvão <mragalvao(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: payloads/ipxe: Enable HTTPS support
by Felix Singer (Code Review) 01 May '20

01 May '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31086 Change subject: payloads/ipxe: Enable HTTPS support ...................................................................... payloads/ipxe: Enable HTTPS support HTTPS needs a newer iPXE version than 2017.3, because it doesn't work with this release. Tested under master branch. Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31086/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..05b6f4dd 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Gerrit-Change-Number: 31086 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: update USB2 strength
by 9elements QA (Code Review) 01 May '20

01 May '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40482 ) Change subject: mb/google/puff: update USB2 strength ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2920 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2919 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2918 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2917 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/40482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4 Gerrit-Change-Number: 40482 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 14:30:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/sonorapass: Add Sonora Pass
by Maxim Polyakov (Code Review) 01 May '20

01 May '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40469 ) Change subject: mb/ocp/sonorapass: Add Sonora Pass ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Gerrit-Change-Number: 40469 Gerrit-PatchSet: 6 Gerrit-Owner: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 14:13:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Increase SPI flash frequency to 37.5MHz
by Julius Werner (Code Review) 01 May '20

01 May '20

Hello Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40874 to review the following change. Change subject: sc7180: Increase SPI flash frequency to 37.5MHz ...................................................................... sc7180: Increase SPI flash frequency to 37.5MHz It seems that all SC7180 boards we have can well handle 37.5MHz of SPI flash speed, so bump that up from the current 25MHz so that we don't leave boot speed on the table. (The next step would be 50MHz which currently doesn't work on all boards so we're not going there yet.) BUG=b:117440651 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea --- M src/soc/qualcomm/sc7180/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/40874/1 diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 9cecb4f..d860c4a 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -22,6 +22,6 @@ { sc7180_mmu_init(); clock_init(); - quadspi_init(25 * MHz); + quadspi_init(37500 * KHz); qupv3_fw_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea Gerrit-Change-Number: 40874 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Check SPD is not NULL before print
by EricR Lai (Code Review) 01 May '20

01 May '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40560 ) Change subject: soc/intel/tigerlake: Check SPD is not NULL before print ...................................................................... soc/intel/tigerlake: Check SPD is not NULL before print Check SPD is not NULL before print. Thsi can avoid system hang up. BUG=b:154445630 TEST=Check NULL SPD is not print. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40560/1 diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 8664547..1210bcd 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -308,7 +308,7 @@ get_spd_smbus(blk); for (i = 0; i < ARRAY_SIZE(blk->addr_map); i++) { - if (blk->addr_map[i]) + if (blk->addr_map[i] && blk->spd_array[i] != NULL) print_spd_info((unsigned char *)blk->spd_array[i]); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04 Gerrit-Change-Number: 40560 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/pei_data.h: Add ULT system type
by Angel Pons (Code Review) 01 May '20

01 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40692 ) Change subject: nb/intel/haswell/pei_data.h: Add ULT system type ...................................................................... nb/intel/haswell/pei_data.h: Add ULT system type Looks like 5 is a valid system type, as Google Beltino and Slippy are using it. According to comments on these mainboards' code, this value corresponds to ULT systems. So, add it to the comment on the pei_data struct, which was likely copied from Sandy Bridge and was not updated. Change-Id: I3654bb6022839dba3e1499cf43e8beaa97d1def1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/pei_data.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/40692/1 diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 17b7c18..455b043 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -81,7 +81,8 @@ uint32_t pmbase; uint32_t gpiobase; uint32_t temp_mmio_base; - uint32_t system_type; // 0 Mobile, 1 Desktop/Server + /* Board type: 0 => Mobile, 1 => Desktop/Server, 5 => ULT, Others => Reserved */ + uint32_t system_type; uint32_t tseg_size; uint8_t spd_addresses[4]; int boot_mode; -- To view, visit https://review.coreboot.org/c/coreboot/+/40692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3654bb6022839dba3e1499cf43e8beaa97d1def1 Gerrit-Change-Number: 40692 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Disable secure debug unlock
by Furquan Shaikh (Code Review) 01 May '20

01 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40683 ) Change subject: soc/amd/picasso: Disable secure debug unlock ...................................................................... soc/amd/picasso: Disable secure debug unlock This change updates PSP_SOFTFUSE to disable secure debug unlock by default and also removes the addition of debug key and debug file to PSP directory. This is not something that we would want to be enabled on shipping devices. If debug capability is required, there should be a separate Kconfig to enable it. BUG=b:154880818 TEST=Verified that trembyle boots to OS. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5 --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 2 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/40683/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e686ab8..577db50 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -106,11 +106,8 @@ PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin -# type = 0x9 -PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin - # type = 0xb - See #55758 (NDA) for bit definitions. -PSP_SOFTFUSE="0x0000000010000001" +PSP_SOFTFUSE="0x0000000010000000" ifeq ($(CONFIG_USE_PSPSCUREOS),y) # types = 0x2, 0xc @@ -118,9 +115,6 @@ PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_ftpm_prod_RV.csbin endif -# type = 0x13 -PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin - # type = 0x21 PSP_IKEK_FILE=$(top)/$(FIRMWARE_LOCATE)/PspIkekRV.bin @@ -135,7 +129,7 @@ # BIOS type = 0x6a PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin else -PSP_SOFTFUSE="0x0000000030000001" +PSP_SOFTFUSE="0x0000000030000000" endif # type = 0x28 @@ -214,11 +208,9 @@ OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) -OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) OPT_SECG2_FILE=$(call add_opt_prefix, $(PSP_SECG2_FILE), --subprog 2 --sec-gasket) @@ -263,7 +255,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ - $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ $(call strip_quotes, $(PSP_APCB0_FILE)) \ $(call strip_quotes, $(PSP_APCB1_FILE)) \ @@ -301,7 +292,6 @@ $(call_strip_quotes, $(PSP_DRIVERS_FILE)) \ $(call_strip_quotes, $(PSP_S0I3_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ - $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -309,7 +299,6 @@ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ $(OPT_SMUFW1_SUB2_FILE) \ $(OPT_SMUFW2_SUB2_FILE) \ @@ -355,9 +344,7 @@ $(OPT_DRIVERS_FILE) \ $(OPT_PSP_S0I3_FILE) \ $(OPT_IKEK_FILE) \ - $(OPT_SEC_DEBUG_FILE) \ --combo-capable \ - --token-unlock \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/40683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5 Gerrit-Change-Number: 40683 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci_id: Add Tiger Lake TCSS device ID
by John Zhao (Code Review) 01 May '20

01 May '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40693 ) Change subject: device/pci_id: Add Tiger Lake TCSS device ID ...................................................................... device/pci_id: Add Tiger Lake TCSS device ID Add Tiger Lake TCSS USB xHCI, xDCI and Thunderbolt DMA device ID. BUG=None TEST=Built and booted image sucessfully. Change-Id: Idef3850666c9f393181e0a13974b9ad79ba258ad Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/40693/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3de67ca..a42d61f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3537,6 +3537,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI 0x9a13 +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI 0x9a15 #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded @@ -3647,6 +3649,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 -- To view, visit https://review.coreboot.org/c/coreboot/+/40693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef3850666c9f393181e0a13974b9ad79ba258ad Gerrit-Change-Number: 40693 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2020