Change in coreboot[master]: sc7180: Increase SPI flash frequency to 37.5MHz

[Julius Werner (Code Review)]

Hello Philip Chen, mturney mturney,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/40874

to review the following change.

Change subject: sc7180: Increase SPI flash frequency to 37.5MHz
......................................................................

sc7180: Increase SPI flash frequency to 37.5MHz

It seems that all SC7180 boards we have can well handle 37.5MHz of SPI
flash speed, so bump that up from the current 25MHz so that we don't
leave boot speed on the table. (The next step would be 50MHz which
currently doesn't work on all boards so we're not going there yet.)

BUG=b:117440651

Signed-off-by: Julius Werner 
Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea
---
M src/soc/qualcomm/sc7180/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/40874/1

diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c
index 9cecb4f..d860c4a 100644
--- a/src/soc/qualcomm/sc7180/bootblock.c
+++ b/src/soc/qualcomm/sc7180/bootblock.c
@@ -22,6 +22,6 @@
 {
    sc7180_mmu_init();
    clock_init();
-	quadspi_init(25 * MHz);
+	quadspi_init(37500 * KHz);
    qupv3_fw_init();
 }

[Philip Chen (Code Review)]

Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40874 )

Change subject: sc7180: Increase SPI flash frequency to 37.5MHz
......................................................................

Patch Set 1: Code-Review+2

So it maps to qspi_core_cfg[2] now?
From the bug link, this seems to have been tested and boot fine.
So LGTM.

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40874 )

Change subject: sc7180: Increase SPI flash frequency to 37.5MHz
......................................................................

Patch Set 1:
> So it maps to qspi_core_cfg[2] now?

Yes, but the clock code is able to figure that out internally.

We want to cut a clean release tomorrow so let's push this a bit prematurely to make sure it is in...

[Julius Werner (Code Review)]

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40874 )

Change subject: sc7180: Increase SPI flash frequency to 37.5MHz
......................................................................

sc7180: Increase SPI flash frequency to 37.5MHz

It seems that all SC7180 boards we have can well handle 37.5MHz of SPI
flash speed, so bump that up from the current 25MHz so that we don't
leave boot speed on the table. (The next step would be 50MHz which
currently doesn't work on all boards so we're not going there yet.)

BUG=b:117440651

Signed-off-by: Julius Werner 
Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40874
Tested-by: build bot (Jenkins) 
Reviewed-by: Philip Chen 
---
M src/soc/qualcomm/sc7180/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Philip Chen: Looks good to me, approved

diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c
index 9cecb4f..d860c4a 100644
--- a/src/soc/qualcomm/sc7180/bootblock.c
+++ b/src/soc/qualcomm/sc7180/bootblock.c
@@ -22,6 +22,6 @@
 {
    sc7180_mmu_init();
    clock_init();
-	quadspi_init(25 * MHz);
+	quadspi_init(37500 * KHz);
    qupv3_fw_init();
 }

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40874 )

Change subject: sc7180: Increase SPI flash frequency to 37.5MHz
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2908
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2907
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2906
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2905

Please note: This test is under development and might not be accurate at all!