Julius Werner would like Philip Chen and mturney mturney to review this change.
sc7180: Increase SPI flash frequency to 37.5MHz
It seems that all SC7180 boards we have can well handle 37.5MHz of SPI
flash speed, so bump that up from the current 25MHz so that we don't
leave boot speed on the table. (The next step would be 50MHz which
currently doesn't work on all boards so we're not going there yet.)
BUG=b:117440651
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea
---
M src/soc/qualcomm/sc7180/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/40874/1
diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c
index 9cecb4f..d860c4a 100644
--- a/src/soc/qualcomm/sc7180/bootblock.c
+++ b/src/soc/qualcomm/sc7180/bootblock.c
@@ -22,6 +22,6 @@
{
sc7180_mmu_init();
clock_init();
- quadspi_init(25 * MHz);
+ quadspi_init(37500 * KHz);
qupv3_fw_init();
}
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