coreboot-gerrit May 2020

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Change in coreboot[master]: soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40844 ) Change subject: soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/graphics.c 2 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/40844/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index d67edea..516359d 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -61,22 +61,21 @@ static void soc_config_pwrmbase(void) { uint32_t reg32; + uint16_t reg16; /* * Assign Resources to PWRMBASE * Clear BIT 1-2 Command Register */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MEMORY); - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Enable PWRM in PMC */ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index c2f9957..834c7f8 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -48,9 +48,9 @@ } /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + uint16_t reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); /* * GFX PEIM module inside FSP binary is taking care of graphics -- To view, visit https://review.coreboot.org/c/coreboot/+/40844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33 Gerrit-Change-Number: 40844 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40843 ) Change subject: soc/intel/common: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/intel/common: Fix 16-bit read/write PCI_COMMAND register Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/uart/uart.c 8 files changed, 21 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40843/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 8daf6d2..2ae70bf 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -75,7 +75,7 @@ #else struct device *dev = PCH_DEV_CSE; #endif - u8 pcireg; + u16 pcireg; /* Assume it is already initialized, nothing else to do */ if (cse.sec_bar) @@ -87,18 +87,18 @@ /* Assign Resources to HECI1 */ /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg = pci_read_config16(dev, PCI_COMMAND); pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_write_config16(dev, PCI_COMMAND, pcireg); /* Program Temporary BAR for HECI1 */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg = pci_read_config16(dev, PCI_COMMAND); pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_write_config16(dev, PCI_COMMAND, pcireg); cse.sec_bar = tempbar; } diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index b420308..d0c8b9b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -260,22 +260,22 @@ #else struct device *dev = PCH_DEV_SPI; #endif - uint8_t pcireg; + uint16_t pcireg; /* Assign Resources to SPI Controller */ /* Clear BIT 1-2 SPI Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg = pci_read_config16(dev, PCI_COMMAND); pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_write_config16(dev, PCI_COMMAND, pcireg); /* Program Temporary BAR for SPI */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY); /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg = pci_read_config16(dev, PCI_COMMAND); pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); + pci_write_config16(dev, PCI_COMMAND, pcireg); /* Initialize SPI to allow BIOS to write/erase on flash. */ fast_spi_init(); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index b9638fe..38e96ee 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -69,7 +69,7 @@ /* Prepare early base address for access before memory */ base = dw_i2c_get_soc_early_base(bus); pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Take device out of reset */ diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 731ce50..ff6c9dc 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -23,7 +23,7 @@ pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, + pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 40b9ac6..93ba867 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -34,8 +34,7 @@ u8 port_impl, temp; /* Set Bus Master */ - temp = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Read Ports Implemented (GHC_PI) */ port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 5980b6b..00946b3 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -32,14 +32,14 @@ { pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, PRERAM_MMC_BASE_ADDRESS); - pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } static void disable_mmc_controller_bar(void) { pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, 0); - pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 44fe59d..d8127a8 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -139,7 +139,7 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); @@ -152,9 +152,9 @@ continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If it's not a bridge, move on. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7d75bdd..9498060 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -68,7 +68,7 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); /* Enable memory access and bus master */ - pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); + pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); uart_lpss_init(device, baseaddr); } @@ -109,7 +109,7 @@ if (!base) return false; - if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE) + if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) != UART_PCI_ENABLE) return false; -- To view, visit https://review.coreboot.org/c/coreboot/+/40843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Gerrit-Change-Number: 40843 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40850 ) Change subject: soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smihandler.c 8 files changed, 34 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/40850/1 diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 82904de..cde7496 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -22,11 +22,12 @@ config_t *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32; + uint16_t reg16; /* Ensure memory and bus master are enabled */ - tmp32 = pci_read_config32(dev, PCI_COMMAND); - tmp32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, tmp32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 476d092..c5ce2e4 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -84,7 +84,6 @@ u8 *base; struct resource *res; u32 codec_mask; - u32 reg32; /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -95,8 +94,7 @@ printk(BIOS_DEBUG, "HDA: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); hda_pch_init(dev, base); @@ -110,7 +108,7 @@ static void hda_enable(struct device *dev) { - u32 reg32; + u16 reg16; u8 reg8; reg8 = pci_read_config8(dev, 0x43); @@ -126,10 +124,10 @@ printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n"); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device */ pch_disable_devfn(dev); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 730d77e..0edc1d3 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -600,17 +600,17 @@ static void intel_me_finalize(struct device *dev) { - u32 reg32; + u16 reg16; /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0) return; /* Make sure IO is disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -712,7 +712,7 @@ { struct resource *res; struct mei_csr host; - u32 reg32; + u16 reg16; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -723,9 +723,9 @@ mei_base_address = res2mmio(res, 0, 0); /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 2dcab97..da0b42a 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -62,8 +62,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index f6f3746..ac6ac2a 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -171,7 +171,7 @@ void broadwell_pch_enable_dev(struct device *dev) { - u32 reg32; + u16 reg16; /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { @@ -185,18 +185,16 @@ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f81f042..d506057 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -574,19 +574,14 @@ static void pch_pcie_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); @@ -597,6 +592,7 @@ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG + u32 reg32; reg32 = pci_read_config32(dev, 0x20); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index a4922f7..8ad9b54 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -160,14 +160,14 @@ config_t *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; - u32 reg32; + u16 reg16; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index bce157d..1d92c12 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -69,7 +69,7 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -79,9 +79,9 @@ continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); -- To view, visit https://review.coreboot.org/c/coreboot/+/40850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Gerrit-Change-Number: 40850 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/tianocore: Fix check for custom bootsplash
by Matt DeVillier (Code Review) 01 May '20

01 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40860 ) Change subject: payloads/tianocore: Fix check for custom bootsplash ...................................................................... payloads/tianocore: Fix check for custom bootsplash -n needs to check against a string, but if CONFIG_TIANOCORE_BOOTSPLASH_FILE is unset, then $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) evaluates to nothing and the check fails, leading the Makefile to try and copy a non- existant file/path. Change-Id: Iff717dd48748cff16f485bafaa91c7a225fb5bdb Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40860/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 1dc368d..21bae75 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -94,7 +94,7 @@ build: update checktools unset CC; $(MAKE) -C $(project_dir)/BaseTools echo " build $(project_name) $(TAG)" - if [ -n $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) ]; then \ + if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \ echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ /*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/40860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff717dd48748cff16f485bafaa91c7a225fb5bdb Gerrit-Change-Number: 40860 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "soc/mediatek/mt8183: Force retraining memory if requested"
by Julius Werner (Code Review) 01 May '20

01 May '20

Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Paul Menzel, Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40623 to review the following change. Change subject: Revert "soc/mediatek/mt8183: Force retraining memory if requested" ...................................................................... Revert "soc/mediatek/mt8183: Force retraining memory if requested" This reverts commit 285975dbba8c7f3bbb9f9950e79a30bb983d5123. Reason for revert: VB2_RECOVERY_TRAIN_AND_REBOOT was never meant to have any special effect on memory training behavior. It was just supposed to be a "reboot automatically after reaching kernel verification" recovery reason. On x86 devices this was used to prime the separate recovery MRC cache in the factory (make sure it is initialized before shipping). This isn't used on Kukui anyway, but in order to make sure nobody copies this code and keep the behavior consistent between platforms, let's remove it. Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40623/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index b9ed619..2a4ebbd 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -169,8 +169,7 @@ /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); - if (vboot_recovery_mode_memory_retrain() || - vboot_check_recovery_request() == VB2_RECOVERY_TRAIN_AND_REBOOT) { + if (vboot_recovery_mode_memory_retrain()) { printk(BIOS_WARNING, "Retrain memory in next boot\n"); /* Use 0xFF as erased flash data. */ memset(dparam, 0xff, sizeof(*dparam)); -- To view, visit https://review.coreboot.org/c/coreboot/+/40623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f Gerrit-Change-Number: 40623 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl: always enable SataPwrOptEnable
by Angel Pons (Code Review) 01 May '20

01 May '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40877 ) Change subject: soc/intel/skl: always enable SataPwrOptEnable ...................................................................... Patch Set 3: (9 comments) https://review.coreboot.org/c/coreboot/+/40877/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40877/3//COMMIT_MSG@11 PS3, Line 11: This leads to all sorts of problems and errors, for example: : - links get lost : - only 1.5 or 3 Gbps instead of 6 Gbps : - "Unaligned Write" errors in Linux : - ... You told me this only happens when you enable power management in SATA (e.g. SALP), so why don't you mention it anywhere? https://review.coreboot.org/c/coreboot/+/40877/3//COMMIT_MSG@22 PS3, Line 22: provide an option : for breaking coreboot That is not its intended purpose, yet your wording makes it sound as it were. I would suggest a less charged wording: There is no reason to have debugging switches as devicetree options, anyway. Its actual purpose would be to disable power management stuff for debugging purposes. Power management mechanisms in the hardware are increasingly complex, so there's lots of things that could go wrong. Unfortunately, there are undocumented interdependencies between FSP UPDs. In this case, looks like enabling SATA power management but disabling power management programming steps is an invalid configuration, but nothing says a word about that. Moreover, the FSP integration in coreboot results in default values of zero for the devicetree fields that are not explicitly assigned on each mainboard. So, even if FSP had the correct default value in the UPDs, it would get overwritten by coreboot. https://review.coreboot.org/c/coreboot/+/40877/3//COMMIT_MSG@24 PS3, Line 24: : Surprisingly cml and cnl are not affected, even though they share mostly : the same reference code in this regard. That nobody reported any problems doesn't mean that it's not affected. There's no guarantee that things remain like this in the future, so I would omit this part. https://review.coreboot.org/c/coreboot/+/40877/3//COMMIT_MSG@26 PS3, Line 26: Thus, only skl gets changed. A more compelling reason to only change SKL for now is because it has been tested and works: as per IRC, this change fixes problems on two different types of platforms without any noticeable downsides. https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… PS3, Line 264: (link) Why the parentheses? https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… PS3, Line 264: * For unknown reasons FSP skips SATA init steps, resulting in (link) errors, unaligned write > line over 96 characters Please fix https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… PS3, Line 264: unaligned write What's an unaligned write error? https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… PS3, Line 264: For unknown reasons FSP skips SATA init steps Does it always skip those SATA init steps? If not, when does it skip such steps? The current wording of this sentence does not make this clear enough. https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… PS3, Line 265: the SATA SIR Only one SATA SIR? -- To view, visit https://review.coreboot.org/c/coreboot/+/40877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Gerrit-Change-Number: 40877 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pena Galvão <mragalvao(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 May 2020 15:41:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiogapass: Implement port 80h direct to GPIO and init UART pins
by 9elements QA (Code Review) 01 May '20

01 May '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40481 ) Change subject: mb/ocp/tiogapass: Implement port 80h direct to GPIO and init UART pins ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2946 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2945 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2944 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2943 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/40481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7 Gerrit-Change-Number: 40481 Gerrit-PatchSet: 5 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 15:30:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/voteer: Enable DevSlp for SATA port1
by Wonkyu Kim (Code Review) 01 May '20

01 May '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40584 ) Change subject: mb/google/voteer: Enable DevSlp for SATA port1 ...................................................................... mb/google/voteer: Enable DevSlp for SATA port1 BUG=b:152893285 BRANCH=none TEST=Build and boot to OS volteer with Intel SATA and reboot from OS console Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/40584/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 28931e4..88e4247 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -77,6 +77,7 @@ register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/40584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438 Gerrit-Change-Number: 40584 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl: always enable SataPwrOptEnable
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40877 ) Change subject: soc/intel/skl: always enable SataPwrOptEnable ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/40877/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/40877/2/src/soc/intel/skylake/chip… PS2, Line 261: params->SataPwrOptEnable = 1; > Agreed. e.g.: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Gerrit-Change-Number: 40877 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pena Galvão <mragalvao(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 May 2020 15:07:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: always enable SataPwrOptEnable
by build bot (Jenkins) (Code Review) 01 May '20

01 May '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40877 ) Change subject: soc/intel/skl: always enable SataPwrOptEnable ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… PS3, Line 264: * For unknown reasons FSP skips SATA init steps, resulting in (link) errors, unaligned write line over 96 characters https://review.coreboot.org/c/coreboot/+/40877/3/src/soc/intel/skylake/chip… PS3, Line 265: * errors and others. Enabling this makes FSP write the SATA SIR, which solves these problems. line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/40877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Gerrit-Change-Number: 40877 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pena Galvão <mragalvao(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 May 2020 15:07:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2020