coreboot-gerrit May 2020

coreboot-gerrit@coreboot.org

1 participants
2588 discussions

Change in coreboot[master]: mb/tiogapass: use common driver to configure GPIO
by Andrey Petrov (Code Review) 01 May '20

01 May '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39427 ) Change subject: mb/tiogapass: use common driver to configure GPIO ...................................................................... Patch Set 42: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Gerrit-Change-Number: 39427 Gerrit-PatchSet: 42 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 21:29:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/tiogapass: use common driver to configure GPIO
by Maxim Polyakov (Code Review) 01 May '20

01 May '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39427 to look at the new patch set (#42). Change subject: mb/tiogapass: use common driver to configure GPIO ...................................................................... mb/tiogapass: use common driver to configure GPIO According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with AMI firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/gpio.h M src/mainboard/ocp/tiogapass/romstage.c 3 files changed, 552 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/39427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Gerrit-Change-Number: 39427 Gerrit-PatchSet: 42 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: payloads/external/GRUB2: prevent rebuild without actual changes
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40955 ) Change subject: payloads/external/GRUB2: prevent rebuild without actual changes ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/40955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf5a316d0c9761426ec2ee306d78cd56d4bf19b5 Gerrit-Change-Number: 40955 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 21:23:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix checkout hint
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40954 ) Change subject: payloads/external/GRUB2: Makefile: fix checkout hint ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/40954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1277c3788a141b25cd9f22ec0476ee56b64aea4d Gerrit-Change-Number: 40954 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 21:23:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix check for changed files
by Michael Niewöhner (Code Review) 01 May '20

01 May '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40953 ) Change subject: payloads/external/GRUB2: Makefile: fix check for changed files ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/40953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie126e3d604990b2346f1f004f912080104e2789d Gerrit-Change-Number: 40953 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 21:22:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/ocp/sonorapass: Populate FSP-M parameters
by 9elements QA (Code Review) 01 May '20

01 May '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40554 ) Change subject: mb/ocp/sonorapass: Populate FSP-M parameters ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3064 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3063 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3062 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3061 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/40554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea Gerrit-Change-Number: 40554 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 20:01:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40846 ) Change subject: soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register Change-Id: I353daf35c843521b089ff8411a9ba8c801605ff9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/scc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40846/1 diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index e475def..e5b0e87 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -43,7 +43,7 @@ { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index a01310e..247bb18 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -21,7 +21,7 @@ { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 3d5c501..552d27d 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -74,7 +74,7 @@ { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, -- To view, visit https://review.coreboot.org/c/coreboot/+/40846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I353daf35c843521b089ff8411a9ba8c801605ff9 Gerrit-Change-Number: 40846 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: src/cpu/x86/mtrr/earlymtrr: Validate MTRR arguments
by Raul Rangel (Code Review) 01 May '20

01 May '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40762 ) Change subject: src/cpu/x86/mtrr/earlymtrr: Validate MTRR arguments ...................................................................... src/cpu/x86/mtrr/earlymtrr: Validate MTRR arguments The AMD64 Architecture Programmer's Manual, Volume 2: Systems Programming says the following about variable MTRRs: Variable Range Size and Alignment. The size and alignment of variable memory-ranges (MTRRs) and I/O ranges (IORRs) are restricted as follows: * The boundary on which a variable range is aligned must be equal to the range size. For example, a memory range of 16 Mbytes must be aligned on a 16-Mbyte boundary. * The range size must be a power of 2 (2 n , 52 > n > 11), with a minimum allowable size of 4 Kbytes. For example, 4 Mbytes and 8 Mbytes are allowable memory range sizes, but 6 Mbytes is not allowable. Print out errors if these conditions are violated. I didn't assert since `set_var_mtrr` can be used in boot block before the serial console is enabled. BUG=b:147042464 TEST=Boot trembyle and see MTRR errors: MTRR Error: base 0xcc800000 must be aligned to size 0x1000000 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8b8c734c7599bd89cf9f212ed43c2dd5b2c8ba7b --- M src/cpu/x86/mtrr/earlymtrr.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40762/1 diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 4d14a8d..1fa0936 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -5,6 +5,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <console/console.h> +#include <lib.h> /* Get first available variable MTRR. * Returns var# if available, else returns -1. @@ -35,6 +37,14 @@ /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ /* FIXME: It only support 4G less range */ msr_t basem, maskm; + + if (!is_power_of_two(size)) + printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); + if (size < 4 * KiB) + printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size); + if (base % size != 0) + printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base, size); + basem.lo = base | type; basem.hi = 0; wrmsr(MTRR_PHYS_BASE(reg), basem); @@ -42,3 +52,4 @@ maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); } + -- To view, visit https://review.coreboot.org/c/coreboot/+/40762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b8c734c7599bd89cf9f212ed43c2dd5b2c8ba7b Gerrit-Change-Number: 40762 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: documentation: Add documentation ideas for season of docs
by Christian Walter (Code Review) 01 May '20

01 May '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40662 ) Change subject: documentation: Add documentation ideas for season of docs ...................................................................... documentation: Add documentation ideas for season of docs Lets gather some documentation ideas for the season of docs. I reused the project ideas style (thanks patrick). This is WIP - feel free to add new project ideas. I will complete the project description in the next days. Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- A Documentation/contributing/documentation_ideas.md 1 file changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40662/1 diff --git a/Documentation/contributing/documentation_ideas.md b/Documentation/contributing/documentation_ideas.md new file mode 100644 index 0000000..08541d1 --- /dev/null +++ b/Documentation/contributing/documentation_ideas.md @@ -0,0 +1,107 @@ +# Project Ideas + +This section collects ideas to improve the coreboot documentation and +should serve as a pool of ideas for people who want to improve the current +documentation status of coreboot. + +The main purpose of this document is to gather documentation ideas for technical +writers of the seasons of docs. Nevertheless anyone who wants to help improving +the current documentation situation can take one of the projects. + +Each entry should outline what would be done, the benefit it brings +to the project, the pre-requisites, both in knowledge and parts. They +should also list people interested in supporting people who want to work +on them. + +## Refactor Existing Documentation + +The goal is to improve the user experience and structure the documentation more +logically. The current situation makes it very hard for beginners, but also for +experienced developers to find anything in the coreboot documentation. + +One possible approach to restructure the documentation is to split it up such +that we divide the group of users into: + +* (End-)users +Most probably users which _just_ want to use coreboot as fast as possible. This +section should include guidelines on how to build coreboot, how to flash coreboot +and also which hardware is currently supported. + +* Developers +This section should more focus on the developer side-of-view. This section would +include how to get started developing coreboot, explaining the basic concepts of +coreboot and also give guideance on how to proceed after the first steps. + +* Knowledge area +This section is very tighlight coupled to the developer section and might be merged +into the developers section. The _Knowledge area_ can give a technical deep dive +on various drivers, technologies, etc. + +* Community area +This section gives some room for the community: Youtube channels, conferences, +meetups, forums, chat, etc. + +A [https://review.coreboot.org/c/coreboot/+/40327](first approach) has already been made here and might be a basis for the work. +Most of the documentation is already there, but scattered around the documentation +folder. + +### Requirements +* Understanding on how a different groups of users might use the documentation area +* Basic understanding of how coreboot works (Can be worked out _on-the-fly_) + +### Mentors +* christian.walter(a)9elements.com +* TBD + +## Update Howto/guides + +* Toolchain Building (various distros) +* Logging/Debugging +* VBoot + +### Requirements +* One +* Two + +### Mentors +* TBD +* TBD + +## How to Board Support + +Desc + +### Requirements +* One +* Two + +### Mentors +* TBD +* TBD + +## Payloads + +* Document all known Payloads +* Propose payloads for different use-cases (OS Support, UEFI, etc.) +* How-to build payloads? + +### Requirements +* One +* Two + +### Mentors +* TBD +* TBD + + +## coerboot util documentation + +* Update util documentation + +### Requirements +* One +* Two + +### Mentors +* TBD +* TBD \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/40662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5 Gerrit-Change-Number: 40662 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

7 26

Change in coreboot[master]: sb/intel/i82801gx: Fix 16-bit PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40741 ) Change subject: sb/intel/i82801gx: Fix 16-bit PCI_COMMAND register ...................................................................... sb/intel/i82801gx: Fix 16-bit PCI_COMMAND register Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c 6 files changed, 20 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40741/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 4a2b50e..775326c 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -230,8 +230,7 @@ pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 1a5366f..77161f5 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -54,23 +54,23 @@ void i82801gx_enable(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide this device if possible */ ich_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_SERR; + pci_write_config16(dev, PCI_COMMAND, reg16); if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) { printk(BIOS_DEBUG, "Set SATA mode early\n"); diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index b6b30ef..dadcbb9 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -14,6 +14,7 @@ static void ide_init(struct device *dev) { u16 ideTimingConfig; + u16 reg16; u32 reg32; u32 enable_primary, enable_secondary; @@ -30,8 +31,8 @@ enable_secondary = config->ide_enable_secondary; } - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER); + reg16 = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, reg16 | PCI_COMMAND_IO | PCI_COMMAND_MASTER); /* Native Capable, but not enabled. */ pci_write_config8(dev, 0x09, 0x8a); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 4398ad5..4de62e2 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -47,9 +47,7 @@ printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index d4b559a..0a0c8ae 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -10,14 +10,14 @@ static void usb_init(struct device *dev) { - u32 reg32; + u16 reg16; u8 reg8; /* USB Specification says the device must be Bus Master */ printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + reg16 = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, reg16 | PCI_COMMAND_MASTER); // Erratum pci_write_config8(dev, 0xca, 0x00); diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index d127496..d246de5 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -14,14 +14,15 @@ { struct resource *res; u8 *base; + u16 reg16; u32 reg32; u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + reg16 |= PCI_COMMAND_SERR; + pci_write_config16(dev, PCI_COMMAND, reg16); reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 31) | (1 << 27); -- To view, visit https://review.coreboot.org/c/coreboot/+/40741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd Gerrit-Change-Number: 40741 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 13

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2020