coreboot-gerrit May 2020

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Change in coreboot[master]: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
by Andrey Petrov (Code Review) 02 May '20

02 May '20

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40917 ) Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ...................................................................... mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21. Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f --- M src/mainboard/intel/cedarisland_crb/romstage.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40917/1 diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index 94af1b6..b53b2b3 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,8 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <arch/mmio.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *start = (void*) m_cfg; + + // BoardId + write8(start + 140, 0x1d); + + // BoardTypeBitmask + write32(start + 104, 0x11111111); + + // DebugPrintLevel + write8(start + 45, 8); + + // KtiLinkSpeedMode + write8(start + 64, 0); + + // KtiPrefetchEn + write8(start + 53, 2); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Gerrit-Change-Number: 40917 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: md/ocp/tiogapass: move local *.h to include dir
by Maxim Polyakov (Code Review) 02 May '20

02 May '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40733 ) Change subject: md/ocp/tiogapass: move local *.h to include dir ...................................................................... md/ocp/tiogapass: move local *.h to include dir Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/bootblock.c R src/mainboard/ocp/tiogapass/include/gpio.h R src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h M src/mainboard/ocp/tiogapass/ramstage.c M src/mainboard/ocp/tiogapass/romstage.c 5 files changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/40733/1 diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index 1fee5e5..bb884c0 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -9,7 +9,7 @@ #include <soc/pcr_ids.h> #include <superio/aspeed/ast2400/ast2400.h> #include <superio/aspeed/common/aspeed.h> -#include "gpio.h" +#include "include/gpio.h" /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ #define PCR_DMI_LPCIOD 0x2770 diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/include/gpio.h similarity index 100% rename from src/mainboard/ocp/tiogapass/gpio.h rename to src/mainboard/ocp/tiogapass/include/gpio.h diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h similarity index 100% rename from src/mainboard/ocp/tiogapass/skxsp_tp_iio.h rename to src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index fba1d80..637f709 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -14,7 +14,7 @@ */ #include <soc/ramstage.h> #include <bootstate.h> -#include "gpio.h" +#include "include/gpio.h" void mainboard_silicon_init_params(FSPS_UPD *params) { diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 818bbcf..ab27df3 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -16,8 +16,7 @@ #include <fsp/api.h> #include <FspmUpd.h> #include <soc/romstage.h> - -#include "skxsp_tp_iio.h" +#include "include/skxsp_tp_iio.h" static void mainboard_config_iio(FSPM_UPD *mupd) { -- To view, visit https://review.coreboot.org/c/coreboot/+/40733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51 Gerrit-Change-Number: 40733 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 17

Change in coreboot[master]: mb/ocp/tiogapass: rework GPIOs configuration using macros
by Maxim Polyakov (Code Review) 02 May '20

02 May '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40731 ) Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ...................................................................... mb/ocp/tiogapass: rework GPIOs configuration using macros This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. However, the PAD_CFG_GPO_GPIO_DRIVER() macros are still used, since these macros were added to the project for a long time ago and some motherboards use them in the configuration. The issue related to these macros should be resolved in a separate patch. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 241 insertions(+), 241 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40731/1 diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h index 823f797..77ae5ff 100644 --- a/src/mainboard/ocp/tiogapass/gpio.h +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -11,534 +11,534 @@ /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - GPIO */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A2 - LAD1 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A3 - LAD2 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A4 - LAD3 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A5 - LFRAME# */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A6 - SERIRQ */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A7 - PIRQA# */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A8 - CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000500, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A9 - CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A10 - GPIO */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ - _PAD_CFG_STRUCT(GPP_A12, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, DRIVER), /* GPP_A13 - GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, DEEP, OFF, DRIVER), /* GPP_A14 - GPIO */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, DRIVER), /* GPP_A15 - GPIO */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A16, NONE, DEEP, OFF, DRIVER), /* GPP_A17 - GPIO */ - _PAD_CFG_STRUCT(GPP_A17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, DRIVER), /* GPP_A18 - GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, DRIVER), /* GPP_A19 - RESERVED */ /* GPP_A20 - GPIO */ - _PAD_CFG_STRUCT(GPP_A20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, DRIVER), /* GPP_A21 - GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* GPP_A22 - GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, DRIVER), /* GPP_A23 - GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B1 - CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B2 - GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, DRIVER), /* GPP_B4 - GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, DRIVER), /* GPP_B5 - GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, DRIVER), /* GPP_B6 - GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, DRIVER), /* GPP_B7 - GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, DRIVER), /* GPP_B8 - GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, DRIVER), /* GPP_B9 - GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, DRIVER), /* GPP_B10 - GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, DRIVER), /* GPP_B11 - GPIO */ - _PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 1, DEEP, NONE), /* GPP_B12 - GLB_RST_WARN_N# */ - _PAD_CFG_STRUCT(GPP_B12, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B13 - PLTRST# */ - _PAD_CFG_STRUCT(GPP_B13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B14 - SPKR */ - _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B15 - GPIO */ - _PAD_CFG_STRUCT(GPP_B15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, DEEP, OFF, DRIVER), /* GPP_B17 - GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, DEEP, OFF, DRIVER), /* GPP_B18 - GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, DRIVER), /* GPP_B19 - GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B19, 1, DEEP, NONE), /* GPP_B20 - GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 0, DEEP, NONE), /* GPP_B21 - GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), /* GPP_B22 - GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x44000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B22, 0, DEEP, NONE), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, 0x00000a00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ - _PAD_CFG_STRUCT(GPP_F0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, DRIVER), /* GPP_F1 - GPIO */ - _PAD_CFG_STRUCT(GPP_F1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, DRIVER), /* GPP_F2 - GPIO */ - _PAD_CFG_STRUCT(GPP_F2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, DRIVER), /* GPP_F3 - GPIO */ - _PAD_CFG_STRUCT(GPP_F3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, DRIVER), /* GPP_F4 - GPIO */ - _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_F6 - GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x84000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 0, PLTRST, NONE), /* GPP_F7 - GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x84000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 0, PLTRST, NONE), /* GPP_F8 - GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x84000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 0, PLTRST, NONE), /* GPP_F9 - GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F10, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F11 - SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F11, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F12 - GPIO */ - _PAD_CFG_STRUCT(GPP_F12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F14 - SSATA_LED# */ - _PAD_CFG_STRUCT(GPP_F14, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F15 - GPIO */ - _PAD_CFG_STRUCT(GPP_F15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ - _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, DRIVER), /* GPP_F17 - GPIO */ - _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, DEEP, OFF, DRIVER), /* GPP_F18 - GPIO */ - _PAD_CFG_STRUCT(GPP_F18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - _PAD_CFG_STRUCT(GPP_F19, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F20 - LAN_SMBDATA */ - _PAD_CFG_STRUCT(GPP_F20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F21 - LAN_SMBALRT# */ - _PAD_CFG_STRUCT(GPP_F21, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F22 - SSATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F22, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F23 - SSATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F23, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF), /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - _PAD_CFG_STRUCT(GPP_C2, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ - _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x00000000), + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, DEEP, OFF, DRIVER), /* GPP_C9 - GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_C9, 1, DEEP, NONE), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x86000103, 0x00000000), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_C11 - GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C14 - GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x80080102, 0x00000000), + PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), /* GPP_C15 - GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, DRIVER), /* GPP_C16 - GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, DEEP, OFF, DRIVER), /* GPP_C17 - GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, DEEP, OFF, DRIVER), /* GPP_C18 - GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, DEEP, OFF, DRIVER), /* GPP_C19 - GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, DEEP, OFF, DRIVER), /* GPP_C20 - RESERVED */ /* GPP_C21 - GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, DEEP, OFF, DRIVER), /* GPP_C22 - GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x80040102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), /* GPP_C23 - GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x40840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - _PAD_CFG_STRUCT(GPP_D0, 0x80840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), /* GPP_D1 - GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 0, DEEP, NONE), /* GPP_D2 - GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, DRIVER), /* GPP_D3 - GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, DRIVER), /* GPP_D4 - GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 1, DEEP, NONE), /* GPP_D5 - GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, DRIVER), /* GPP_D6 - GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, DRIVER), /* GPP_D7 - GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, DRIVER), /* GPP_D8 - GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, DRIVER), /* GPP_D9 - GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, DRIVER), /* GPP_D10 - GPIO */ - _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, DRIVER), /* GPP_D11 - GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, OFF, DRIVER), /* GPP_D12 - GPIO */ - _PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, OFF, DRIVER), /* GPP_D13 - GPIO */ - _PAD_CFG_STRUCT(GPP_D13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, DRIVER), /* GPP_D14 - GPIO */ - _PAD_CFG_STRUCT(GPP_D14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - _PAD_CFG_STRUCT(GPP_D15, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_D16 - GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, DRIVER), /* GPP_D18 - GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, DRIVER), /* GPP_D19 - GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, DEEP, NONE), /* GPP_D20 - GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, DRIVER), /* GPP_D21 - GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, DEEP, OFF, DRIVER), /* GPP_D22 - GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, DRIVER), /* GPP_D23 - GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - GPIO */ - _PAD_CFG_STRUCT(GPP_E0, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E0, NONE, DEEP, LEVEL, NONE), /* GPP_E1 - GPIO */ - _PAD_CFG_STRUCT(GPP_E1, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E1, NONE, DEEP, LEVEL, NONE), /* GPP_E2 - GPIO */ - _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - _PAD_CFG_STRUCT(GPP_E3, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E4 - GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, DRIVER), /* GPP_E6 - GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, DRIVER), /* GPP_E7 - GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E8, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_E9 - USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E9, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E10 - GPIO */ - _PAD_CFG_STRUCT(GPP_E10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ - _PAD_CFG_STRUCT(GPP_E11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, DRIVER), /* GPP_E12 - GPIO */ - _PAD_CFG_STRUCT(GPP_E12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - GPIO */ - _PAD_CFG_STRUCT(GPD1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, RSMRST, OFF, ACPI), /* GPD2 - GPIO */ - _PAD_CFG_STRUCT(GPD2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD4 - SLP_S3# */ - _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD5 - SLP_S4# */ - _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD6 - GPIO */ - _PAD_CFG_STRUCT(GPD6, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, 0x04000103, 0x00000000), + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPD8 - GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ - _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - GPIO */ - _PAD_CFG_STRUCT(GPD10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - _PAD_CFG_STRUCT(GPD11, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - _PAD_CFG_STRUCT(GPP_I0, 0x44000900, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I1 - LAN_TCK */ - _PAD_CFG_STRUCT(GPP_I1, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I2 - LAN_TMS */ - _PAD_CFG_STRUCT(GPP_I2, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I3 - LAN_TDI */ - _PAD_CFG_STRUCT(GPP_I3, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, DEEP, OFF, DRIVER), /* GPP_I6 - GPIO */ - _PAD_CFG_STRUCT(GPP_I6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - _PAD_CFG_STRUCT(GPP_I7, 0x44000902, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I8 - GPIO */ - _PAD_CFG_STRUCT(GPP_I8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ - _PAD_CFG_STRUCT(GPP_I9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, DEEP, OFF, DRIVER), /* GPP_I10 - GPIO */ - _PAD_CFG_STRUCT(GPP_I10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - _PAD_CFG_STRUCT(GPP_J0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J1 - LAN_LED_P0_1 */ - _PAD_CFG_STRUCT(GPP_J1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J2 - LAN_LED_P1_0 */ - _PAD_CFG_STRUCT(GPP_J2, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J3 - LAN_LED_P1_1 */ - _PAD_CFG_STRUCT(GPP_J3, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J4 - LAN_LED_P2_0 */ - _PAD_CFG_STRUCT(GPP_J4, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J5 - LAN_LED_P2_1 */ - _PAD_CFG_STRUCT(GPP_J5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J6 - LAN_LED_P3_0 */ - _PAD_CFG_STRUCT(GPP_J6, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J7 - LAN_LED_P3_1 */ - _PAD_CFG_STRUCT(GPP_J7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - _PAD_CFG_STRUCT(GPP_J8, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - _PAD_CFG_STRUCT(GPP_J9, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - _PAD_CFG_STRUCT(GPP_J10, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - _PAD_CFG_STRUCT(GPP_J11, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - _PAD_CFG_STRUCT(GPP_J12, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - _PAD_CFG_STRUCT(GPP_J13, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - _PAD_CFG_STRUCT(GPP_J14, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - _PAD_CFG_STRUCT(GPP_J15, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J16 - LAN_SDP_P0_0 */ - _PAD_CFG_STRUCT(GPP_J16, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J17 - GPIO */ - _PAD_CFG_STRUCT(GPP_J17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - _PAD_CFG_STRUCT(GPP_J18, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J19 - GPIO */ - _PAD_CFG_STRUCT(GPP_J19, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - _PAD_CFG_STRUCT(GPP_J20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J21 - GPIO */ - _PAD_CFG_STRUCT(GPP_J21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - _PAD_CFG_STRUCT(GPP_J22, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J23 - GPIO */ - _PAD_CFG_STRUCT(GPP_J23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - GPIO */ - _PAD_CFG_STRUCT(GPP_K0, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, DEEP, OFF, DRIVER), /* GPP_K1 - GPIO */ - _PAD_CFG_STRUCT(GPP_K1, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, DEEP, OFF, DRIVER), /* GPP_K2 - GPIO */ - _PAD_CFG_STRUCT(GPP_K2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, DEEP, OFF, DRIVER), /* GPP_K3 - GPIO */ - _PAD_CFG_STRUCT(GPP_K3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, DEEP, OFF, DRIVER), /* GPP_K4 - GPIO */ - _PAD_CFG_STRUCT(GPP_K4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, DRIVER), /* GPP_K5 - GPIO */ - _PAD_CFG_STRUCT(GPP_K5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, DRIVER), /* GPP_K6 - GPIO */ - _PAD_CFG_STRUCT(GPP_K6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - _PAD_CFG_STRUCT(GPP_K7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K8 - LAN_NCSI_ARB_IN */ - _PAD_CFG_STRUCT(GPP_K8, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - _PAD_CFG_STRUCT(GPP_K9, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K10 - PE_RST# */ - _PAD_CFG_STRUCT(GPP_K10, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF), /* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - _PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), /* GPP_G1 - GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), /* GPP_G2 - GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), /* GPP_G3 - GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), /* GPP_G4 - GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, DEEP, OFF, DRIVER), /* GPP_G5 - GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, DEEP, OFF, DRIVER), /* GPP_G6 - GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, DEEP, OFF, DRIVER), /* GPP_G7 - GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, DRIVER), /* GPP_G8 - GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, DEEP, OFF, DRIVER), /* GPP_G9 - GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, DEEP, OFF, DRIVER), /* GPP_G10 - GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, DRIVER), /* GPP_G11 - GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G17 - ADR_COMPLETE */ - _PAD_CFG_STRUCT(GPP_G17, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ - _PAD_CFG_STRUCT(GPP_G18, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G19 - SMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), /* GPP_G22 - GPIO */ - _PAD_CFG_STRUCT(GPP_G22, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_G22, 1, DEEP, NONE), /* GPP_G23 - GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, DEEP, OFF, DRIVER), /* GPP_H1 - GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, DRIVER), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, DRIVER), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, DRIVER), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, DEEP, OFF, DRIVER), /* GPP_H5 - RESERVED */ /* GPP_H6 - GPIO */ - _PAD_CFG_STRUCT(GPP_H6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, DEEP, OFF, DRIVER), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, DEEP, OFF, DRIVER), /* GPP_H8 - GPIO */ - _PAD_CFG_STRUCT(GPP_H8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, DEEP, OFF, DRIVER), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, DEEP, OFF, DRIVER), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ - _PAD_CFG_STRUCT(GPP_H12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, DEEP, OFF, DRIVER), /* GPP_H13 - RESERVED */ /* GPP_H14 - RESERVED */ /* GPP_H15 - GPIO */ - _PAD_CFG_STRUCT(GPP_H15, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, DRIVER), /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ /* GPP_H18 - GPIO */ - _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, DEEP, OFF, DRIVER), /* GPP_H19 - GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, DRIVER), /* GPP_H20 - GPIO */ - _PAD_CFG_STRUCT(GPP_H20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, DRIVER), /* GPP_H21 - GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, DRIVER), /* GPP_H22 - GPIO */ - _PAD_CFG_STRUCT(GPP_H22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, DRIVER), /* GPP_H23 - GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, DRIVER), /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* GPP_L2 - GPIO */ - _PAD_CFG_STRUCT(GPP_L2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */ - _PAD_CFG_STRUCT(GPP_L3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, DRIVER), /* GPP_L4 - GPIO */ - _PAD_CFG_STRUCT(GPP_L4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, DRIVER), /* GPP_L5 - GPIO */ - _PAD_CFG_STRUCT(GPP_L5, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, DRIVER), /* GPP_L6 - GPIO */ - _PAD_CFG_STRUCT(GPP_L6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER), /* GPP_L7 - GPIO */ - _PAD_CFG_STRUCT(GPP_L7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, DRIVER), /* GPP_L8 - GPIO */ - _PAD_CFG_STRUCT(GPP_L8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, DEEP, OFF, DRIVER), /* GPP_L9 - GPIO */ - _PAD_CFG_STRUCT(GPP_L9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L9, NONE, DEEP, OFF, DRIVER), /* GPP_L10 - GPIO */ - _PAD_CFG_STRUCT(GPP_L10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L10, NONE, DEEP, OFF, DRIVER), /* GPP_L11 - GPIO */ - _PAD_CFG_STRUCT(GPP_L11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L11, NONE, DEEP, OFF, DRIVER), /* GPP_L12 - GPIO */ - _PAD_CFG_STRUCT(GPP_L12, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L12, NONE, DEEP, OFF, DRIVER), /* GPP_L13 - GPIO */ - _PAD_CFG_STRUCT(GPP_L13, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L13, NONE, DEEP, OFF, DRIVER), /* GPP_L14 - GPIO */ - _PAD_CFG_STRUCT(GPP_L14, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L14, NONE, DEEP, OFF, DRIVER), /* GPP_L15 - GPIO */ - _PAD_CFG_STRUCT(GPP_L15, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L15, NONE, DEEP, OFF, DRIVER), /* GPP_L16 - GPIO */ - _PAD_CFG_STRUCT(GPP_L16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L16, NONE, DEEP, OFF, DRIVER), /* GPP_L17 - GPIO */ - _PAD_CFG_STRUCT(GPP_L17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L17, NONE, DEEP, OFF, DRIVER), /* GPP_L18 - GPIO */ - _PAD_CFG_STRUCT(GPP_L18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L18, NONE, DEEP, OFF, DRIVER), /* GPP_L19 - GPIO */ - _PAD_CFG_STRUCT(GPP_L19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L19, NONE, DEEP, OFF, DRIVER), }; #endif /* CFG_PCH_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Gerrit-Change-Number: 40731 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 19

Change in coreboot[master]: xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs
by Andrey Petrov (Code Review) 02 May '20

02 May '20

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39453 ) Change subject: xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs ...................................................................... xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h D src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h 2 files changed, 0 insertions(+), 1,315 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h deleted file mode 100644 index 44098b1..0000000 --- a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h +++ /dev/null @@ -1,1017 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SKXSP_TP_GPIO_H_ -#define _SKXSP_TP_GPIO_H_ - -#include <gpio_fsp.h> -#include <soc/gpio_soc_defs.h> - -/* - * OCP TiogaPass Gpio Pad Configuration - */ -static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = { - {GPIO_SKL_H_GPP_A0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N - {GPIO_SKL_H_GPP_A1, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_1_LAD_0_ESPI_IO_0 - {GPIO_SKL_H_GPP_A2, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_2_LAD_1_ESPI_IO_1 - {GPIO_SKL_H_GPP_A3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_3_LAD_2_ESPI_IO_2 - {GPIO_SKL_H_GPP_A4, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_4_LAD_3_ESPI_IO_3 - {GPIO_SKL_H_GPP_A5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N - {GPIO_SKL_H_GPP_A6, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N - {GPIO_SKL_H_GPP_A7, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N - {GPIO_SKL_H_GPP_A8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_8_FM_LPC_CLKRUN_N - {GPIO_SKL_H_GPP_A9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK - {GPIO_SKL_H_GPP_A10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_10_CLKOUT_LPC1 - {GPIO_SKL_H_GPP_A11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_11_FM_LPC_PME_N - {GPIO_SKL_H_GPP_A12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N - {GPIO_SKL_H_GPP_A13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK - {GPIO_SKL_H_GPP_A14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_14_ESPI_RESET_N - {GPIO_SKL_H_GPP_A15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_15_SUSACK_N - {GPIO_SKL_H_GPP_A16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_16_CLKOUT_LPC2 - {GPIO_SKL_H_GPP_A17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_17 - {GPIO_SKL_H_GPP_A18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_18 - // {GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME - {GPIO_SKL_H_GPP_A20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } },//GPP_A_20 - {GPIO_SKL_H_GPP_A21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_21 - {GPIO_SKL_H_GPP_A22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_22 - {GPIO_SKL_H_GPP_A23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_A_23 - - {GPIO_SKL_H_GPP_B0, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_0_CORE_VID_0 - {GPIO_SKL_H_GPP_B1, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_1_CORE_VID_1 - {GPIO_SKL_H_GPP_B2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_2_VRALERT_N - {GPIO_SKL_H_GPP_B3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_3_CPU_GP2 - {GPIO_SKL_H_GPP_B4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_4_CPU_GP3 - {GPIO_SKL_H_GPP_B5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_5_SRCCLKREQ0_N - {GPIO_SKL_H_GPP_B6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_6_SRCCLKREQ1_N - {GPIO_SKL_H_GPP_B7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_7_SRCCLKREQ2_N - {GPIO_SKL_H_GPP_B8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_8_SRCCLKREQ3_N - {GPIO_SKL_H_GPP_B9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_9_SRCCLKREQ4_N - {GPIO_SKL_H_GPP_B10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_10_SRCCLKREQ5_N - {GPIO_SKL_H_GPP_B11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_11 - {GPIO_SKL_H_GPP_B12, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_12_GLB_RST_WARN_N - {GPIO_SKL_H_GPP_B13, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_13_RST_PLTRST_N - {GPIO_SKL_H_GPP_B14, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR - {GPIO_SKL_H_GPP_B15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_15 - {GPIO_SKL_H_GPP_B16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_16 - {GPIO_SKL_H_GPP_B17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_17 - {GPIO_SKL_H_GPP_B18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_18 - {GPIO_SKL_H_GPP_B19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_19 - {GPIO_SKL_H_GPP_B20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_20 - {GPIO_SKL_H_GPP_B21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_21 - {GPIO_SKL_H_GPP_B22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_22 - {GPIO_SKL_H_GPP_B23, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N - -// {GPIO_SKL_H_GPP_C0, {} }, //GPP_C_0_SMBCLK, controlled by ME -// {GPIO_SKL_H_GPP_C1, {} }, //GPP_C_1_SMBDATA, controlled by ME - {GPIO_SKL_H_GPP_C2, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_2_SMBALERT_N -// {GPIO_SKL_H_GPP_C3, {} }, //GPP_C_3_SML0CLK_IE, controlled by ME -// {GPIO_SKL_H_GPP_C4, {} }, //GPP_C_4_SML0DATA_IE, controlled by ME - {GPIO_SKL_H_GPP_C5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_5_SML0ALERT_IE_N -// {GPIO_SKL_H_GPP_C6, {} }, //GPP_C_6_SML1CLK_IE, controlled by ME -// {GPIO_SKL_H_GPP_C7, {} }, //GPP_C_7_SML1DATA_IE, controlled by ME - {GPIO_SKL_H_GPP_C8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_8 - {GPIO_SKL_H_GPP_C9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_9 - {GPIO_SKL_H_GPP_C10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_10 - {GPIO_SKL_H_GPP_C11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_11 - {GPIO_SKL_H_GPP_C12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_12 - {GPIO_SKL_H_GPP_C13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_13 - {GPIO_SKL_H_GPP_C14, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_14 - {GPIO_SKL_H_GPP_C15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_15 - {GPIO_SKL_H_GPP_C16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_16 - {GPIO_SKL_H_GPP_C17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_17 - {GPIO_SKL_H_GPP_C18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_18 - {GPIO_SKL_H_GPP_C19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_19 -// {GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME - {GPIO_SKL_H_GPP_C21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_21 - {GPIO_SKL_H_GPP_C22, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_22 - {GPIO_SKL_H_GPP_C23, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_C_23 - - {GPIO_SKL_H_GPP_D0, { - GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_0 - {GPIO_SKL_H_GPP_D1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_1 - {GPIO_SKL_H_GPP_D2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_2 - {GPIO_SKL_H_GPP_D3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_3 - {GPIO_SKL_H_GPP_D4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_4 - {GPIO_SKL_H_GPP_D5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_5 - {GPIO_SKL_H_GPP_D6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_6 - {GPIO_SKL_H_GPP_D7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_7 - {GPIO_SKL_H_GPP_D8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_8 - {GPIO_SKL_H_GPP_D9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_9_SSATA_DEVSLP3 - {GPIO_SKL_H_GPP_D10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_10_SSATA_DEVSLP4 - {GPIO_SKL_H_GPP_D11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_11_SSATA_DEVSLP5 - {GPIO_SKL_H_GPP_D12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_12_SSATA_SDATAOUT1 - {GPIO_SKL_H_GPP_D13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_13_SML0BLCK_IE - {GPIO_SKL_H_GPP_D14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_14_SML0BDATA_IE - {GPIO_SKL_H_GPP_D15, { - GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_15_SSATA_SDATAOUT0 - {GPIO_SKL_H_GPP_D16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_16_SML0BALERT_IE_N - {GPIO_SKL_H_GPP_D17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_17 - {GPIO_SKL_H_GPP_D18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_18 - {GPIO_SKL_H_GPP_D19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock - } }, //GPP_D_19 - {GPIO_SKL_H_GPP_D20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_20_TP_PCH_GPP_D_20 - {GPIO_SKL_H_GPP_D21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_21_IE_URAT_RX - {GPIO_SKL_H_GPP_D22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_22_IE_URAT_TX - {GPIO_SKL_H_GPP_D23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_D_23 - - {GPIO_SKL_H_GPP_E0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_0_SATAXPCIE0_SATAGP0 - {GPIO_SKL_H_GPP_E1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_1_SATAXPCIE1_SATAGP1 - {GPIO_SKL_H_GPP_E2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_2_SATAXPCIE2_SATAGP2 - {GPIO_SKL_H_GPP_E3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_3_CPU_GP0 - {GPIO_SKL_H_GPP_E4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_4_SATA_DEVSLP0 - {GPIO_SKL_H_GPP_E5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_5_SATA_DEVSLP1 - {GPIO_SKL_H_GPP_E6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_6_SATA_DEVSLP2 - {GPIO_SKL_H_GPP_E7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_7_CPU_GP1 - {GPIO_SKL_H_GPP_E8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_8_SATA_LED_N - {GPIO_SKL_H_GPP_E9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_9_USB2_OC0_N - {GPIO_SKL_H_GPP_E10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_10_USB2_OC1_N - {GPIO_SKL_H_GPP_E11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_11_USB2_OC2_N - {GPIO_SKL_H_GPP_E12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_E_12_USB2_OC3_N - - {GPIO_SKL_H_GPP_F0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_0_SATAXPCIE3_SATAGP3 - {GPIO_SKL_H_GPP_F1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_1_SATAXPCIE4_SATAGP4 - {GPIO_SKL_H_GPP_F2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_2_SATAXPCIE5_SATAGP5 - {GPIO_SKL_H_GPP_F3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_3_SATAXPCIE6_SATAGP6 - {GPIO_SKL_H_GPP_F4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_4_SATAXPCIE7_SATAGP7 - {GPIO_SKL_H_GPP_F5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_5_SATA_DEVSLP3 - {GPIO_SKL_H_GPP_F6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_6_SATA_DEVSLP4 - {GPIO_SKL_H_GPP_F7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_7_SATA_DEVSLP5 - {GPIO_SKL_H_GPP_F8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_8_SATA_DEVSLP6 - {GPIO_SKL_H_GPP_F9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_9_SATA_DEVSLP7 - {GPIO_SKL_H_GPP_F10, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_10_SATA_SCLOCK - {GPIO_SKL_H_GPP_F11, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_11_SATA_SLOAD - {GPIO_SKL_H_GPP_F12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_12_SATA_SDATAOUT1 - {GPIO_SKL_H_GPP_F13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_13_SATA_SDATAOUT0 - {GPIO_SKL_H_GPP_F14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_14_SSATA_LED_N - {GPIO_SKL_H_GPP_F15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_15_USB2_OC4_N - {GPIO_SKL_H_GPP_F16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_16_USB2_OC5_N - {GPIO_SKL_H_GPP_F17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_17_USB2_OC6_N - {GPIO_SKL_H_GPP_F18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_18_USB2_OC7_N - {GPIO_SKL_H_GPP_F19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_19_LAN_SMBCLK - {GPIO_SKL_H_GPP_F20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_20_LAN_SMBDATA - {GPIO_SKL_H_GPP_F21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_21_LAN_SMBALERT_N - {GPIO_SKL_H_GPP_F22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_22_SSATA_SCLOCK - {GPIO_SKL_H_GPP_F23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_F_23_SSATA_SLOAD - - {GPIO_SKL_H_GPP_G0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_0_FANTACH0_FANTACH0IE - {GPIO_SKL_H_GPP_G1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_1_FANTACH1_FANTACH1IE - {GPIO_SKL_H_GPP_G2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_2_FANTACH2_FANTACH2IE - {GPIO_SKL_H_GPP_G3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_3_FANTACH3_FANTACH3IE - {GPIO_SKL_H_GPP_G4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_4_FANTACH4_FANTACH4IE - {GPIO_SKL_H_GPP_G5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_5_FANTACH5_FANTACH5IE - {GPIO_SKL_H_GPP_G6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_6_FANTACH6_FANTACH6IE - {GPIO_SKL_H_GPP_G7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_7_FANTACH7_FANTACH7IE - {GPIO_SKL_H_GPP_G8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_8_FANPWM0_FANPWM0IE - {GPIO_SKL_H_GPP_G9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_9_FANPWM1_FANPWM1IE - {GPIO_SKL_H_GPP_G10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_10_FANPWM2_FANPWM2IE - {GPIO_SKL_H_GPP_G11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_11_FANPWM3_FANPWM3IE - {GPIO_SKL_H_GPP_G12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_12 - {GPIO_SKL_H_GPP_G13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_13 - {GPIO_SKL_H_GPP_G14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_14 - {GPIO_SKL_H_GPP_G15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_15 - {GPIO_SKL_H_GPP_G16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_16 - {GPIO_SKL_H_GPP_G17, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_17_ADR_COMPLETE - {GPIO_SKL_H_GPP_G18, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_18_FM_NMI_EVENT_N - {GPIO_SKL_H_GPP_G19, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_19_FM_SMI_ACTIVE_N -// {GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME - {GPIO_SKL_H_GPP_G21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_21_SSATA_DEVSLP1 - {GPIO_SKL_H_GPP_G22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_22_SSATA_DEVSLP2 - {GPIO_SKL_H_GPP_G23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_G_23_SSATAXPCIE0_SSATAGP0 - - {GPIO_SKL_H_GPP_H0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_0_SRCCLKREQ6_N - {GPIO_SKL_H_GPP_H1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_1_SRCCLKREQ7_N - {GPIO_SKL_H_GPP_H2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_2_SRCCLKREQ8_N - {GPIO_SKL_H_GPP_H3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_3_SRCCLKREQ9_N - {GPIO_SKL_H_GPP_H4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_4_SRCCLKREQ10_N -// {GPIO_SKL_H_GPP_H5, {} }, //GPP_H_5_SRCCLKREQ11_N - {GPIO_SKL_H_GPP_H6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_6_SRCCLKREQ12_N - {GPIO_SKL_H_GPP_H7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_7_SRCCLKREQ13_N - {GPIO_SKL_H_GPP_H8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_8_SRCCLKREQ14_N - {GPIO_SKL_H_GPP_H9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_9_SRCCLKREQ15_N -// {GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE -// {GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE - {GPIO_SKL_H_GPP_H12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_12_SML2ALERT_N_IE -// {GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE -// {GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE - {GPIO_SKL_H_GPP_H15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_15_SML3ALERT_N_IE -// {GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE -// {GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE - {GPIO_SKL_H_GPP_H18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_18_SML4ALERT_N_IE - {GPIO_SKL_H_GPP_H19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_19_SSATAXPCIE1_SSATAGP1 - {GPIO_SKL_H_GPP_H20, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_20_SSATAXPCIE2_SSATAGP2 - {GPIO_SKL_H_GPP_H21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_21_SSATAXPCIE3_SSATAGP3 - {GPIO_SKL_H_GPP_H22, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_22_SSATAXPCIE4_SSATAGP4 - {GPIO_SKL_H_GPP_H23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_H_23_SSATAXPCIE5_SSATAGP5 - - {GPIO_SKL_H_GPP_I0, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_0_GBE_TDO - {GPIO_SKL_H_GPP_I1, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_1_GBE_TCK - {GPIO_SKL_H_GPP_I2, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_2_GBE_TMS - {GPIO_SKL_H_GPP_I3, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_3_GBE_TDI - {GPIO_SKL_H_GPP_I4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_4_DO_RESET_IN_N - {GPIO_SKL_H_GPP_I5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_5_DO_RESET_OUT_N - {GPIO_SKL_H_GPP_I6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_6_RESET_DONE - {GPIO_SKL_H_GPP_I7, { - GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_7_JTAG_GBE_TRST_N - {GPIO_SKL_H_GPP_I8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_8_GBE_PCI_DIS - {GPIO_SKL_H_GPP_I9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_9_GBE_LAN_DIS - {GPIO_SKL_H_GPP_I10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_I_10 - - {GPIO_SKL_H_GPP_J0, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_0_LAN_LED_P0_0 - {GPIO_SKL_H_GPP_J1, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_1_LAN_LED_P0_1 - {GPIO_SKL_H_GPP_J2, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_2_LAN_LED_P1_0 - {GPIO_SKL_H_GPP_J3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_3_LAN_LED_P1_1 - {GPIO_SKL_H_GPP_J4, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_4_LAN_LED_P2_0 - {GPIO_SKL_H_GPP_J5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_5_LAN_LED_P2_1 - {GPIO_SKL_H_GPP_J6, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_6_LAN_LED_P3_0 - {GPIO_SKL_H_GPP_J7, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_7_LAN_LED_P3_1 - {GPIO_SKL_H_GPP_J8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_8_LAN_I2C_SCL_MDC_P0 - {GPIO_SKL_H_GPP_J9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0 - {GPIO_SKL_H_GPP_J10, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_10_LAN_I2C_SCL_MDC_P1 - {GPIO_SKL_H_GPP_J11, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1 - {GPIO_SKL_H_GPP_J12, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_12_LAN_I2C_SCL_MDC_P2 - {GPIO_SKL_H_GPP_J13, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2 - {GPIO_SKL_H_GPP_J14, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_14_LAN_I2C_SCL_MDC_P3 - {GPIO_SKL_H_GPP_J15, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3 - {GPIO_SKL_H_GPP_J16, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_16_LAN_SDP_P0_0 - {GPIO_SKL_H_GPP_J17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_17_LAN_SDP_P0_1 - {GPIO_SKL_H_GPP_J18, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_18_LAN_SDP_P1_0 - {GPIO_SKL_H_GPP_J19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_19_LAN_SDP_P1_1 - {GPIO_SKL_H_GPP_J20, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_20_LAN_SDP_P2_0 - {GPIO_SKL_H_GPP_J21, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_21_LAN_SDP_P2_1 - {GPIO_SKL_H_GPP_J22, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_22_LAN_SDP_P3_0 - {GPIO_SKL_H_GPP_J23, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_J_23_LAN_SDP_P3_1 - - {GPIO_SKL_H_GPP_K0, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_0_LAN_NCSI_CLK_IN - {GPIO_SKL_H_GPP_K1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_1_LAN_NCSI_TXD0 - {GPIO_SKL_H_GPP_K2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_2_LAN_NCSI_TXD1 - {GPIO_SKL_H_GPP_K3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_3_LAN_NCSI_TX_EN - {GPIO_SKL_H_GPP_K4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_4_LAN_NCSI_CRS_DV - {GPIO_SKL_H_GPP_K5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_5_LAN_NCSI_RXD0 - {GPIO_SKL_H_GPP_K6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_6_LAN_NCSI_RXD1 - {GPIO_SKL_H_GPP_K7, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_7 - {GPIO_SKL_H_GPP_K8, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_8_LAN_NCSI_ARB_IN - {GPIO_SKL_H_GPP_K9, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_9_LAN_NCSI_ARB_OUT - {GPIO_SKL_H_GPP_K10, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_K_10_PE_RST_N - - {GPIO_SKL_H_GPP_L2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_2_TESTCH0_D0 - {GPIO_SKL_H_GPP_L3, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_3_TESTCH0_D1 - {GPIO_SKL_H_GPP_L4, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_4_TESTCH0_D2 - {GPIO_SKL_H_GPP_L5, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_5_TESTCH0_D3 - {GPIO_SKL_H_GPP_L6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_6_TESTCH0_D4 - {GPIO_SKL_H_GPP_L7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_7_TESTCH0_D5 - {GPIO_SKL_H_GPP_L8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_8_TESTCH0_D6 - {GPIO_SKL_H_GPP_L9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_9_TESTCH0_D7 - {GPIO_SKL_H_GPP_L10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_10_TESTCH0_CLK - {GPIO_SKL_H_GPP_L11, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_11_TESTCH1_D0 - {GPIO_SKL_H_GPP_L12, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_12_TESTCH1_D1 - {GPIO_SKL_H_GPP_L13, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_13_TESTCH1_D2 - {GPIO_SKL_H_GPP_L14, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_14_TESTCH1_D3 - {GPIO_SKL_H_GPP_L15, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_15_TESTCH1_D4 - {GPIO_SKL_H_GPP_L16, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_16_TESTCH1_D5 - {GPIO_SKL_H_GPP_L17, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_17_TESTCH1_D6 - {GPIO_SKL_H_GPP_L18, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_18_TESTCH1_D7 - {GPIO_SKL_H_GPP_L19, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock - } }, //GPP_L_19_TESTCH1_CLK - - {GPIO_SKL_H_GPD0, {} }, //GPD_0, controlled by ME - {GPIO_SKL_H_GPD1, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_1_ACPRESENT - {GPIO_SKL_H_GPD2, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_2_GBE_WAKE_N - {GPIO_SKL_H_GPD3, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_3_PWRBTNB_N - {GPIO_SKL_H_GPD4, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_4_SLP_S3B - {GPIO_SKL_H_GPD5, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_5_SLP_S4B - {GPIO_SKL_H_GPD6, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_6_SLPA_N - {GPIO_SKL_H_GPD7, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_7 - {GPIO_SKL_H_GPD8, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD - {GPIO_SKL_H_GPD9, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_9 - {GPIO_SKL_H_GPD10, { - GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_10_FM_SLPS5_N - {GPIO_SKL_H_GPD11, { - GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutLow, - GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock - } }, //GPD_11_GBEPHY -}; - -#endif /* _SKXSP_TP_GPIO_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h deleted file mode 100644 index ac230ef..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _GPIO_SOC_DEFS_H_ -#define _GPIO_SOC_DEFS_H_ - -/// -/// Skylake-SP chipset GPIO Groups -/// -#define GPIO_SKL_H_GROUP_GPP_A 0x0100 -#define GPIO_SKL_H_GROUP_GPP_B 0x0101 -#define GPIO_SKL_H_GROUP_GPP_C 0x0102 -#define GPIO_SKL_H_GROUP_GPP_D 0x0103 -#define GPIO_SKL_H_GROUP_GPP_E 0x0104 -#define GPIO_SKL_H_GROUP_GPP_F 0x0105 -#define GPIO_SKL_H_GROUP_GPP_G 0x0106 -#define GPIO_SKL_H_GROUP_GPP_H 0x0107 -#define GPIO_SKL_H_GROUP_GPP_I 0x0108 -#define GPIO_SKL_H_GROUP_GPP_J 0x0109 -#define GPIO_SKL_H_GROUP_GPP_K 0x010A -#define GPIO_SKL_H_GROUP_GPP_L 0x010B -#define GPIO_SKL_H_GROUP_GPD 0x010C - -/// -/// SKL H GPIO pins -/// -#define GPIO_SKL_H_GPP_A0 0x01000000 -#define GPIO_SKL_H_GPP_A1 0x01000001 -#define GPIO_SKL_H_GPP_A2 0x01000002 -#define GPIO_SKL_H_GPP_A3 0x01000003 -#define GPIO_SKL_H_GPP_A4 0x01000004 -#define GPIO_SKL_H_GPP_A5 0x01000005 -#define GPIO_SKL_H_GPP_A6 0x01000006 -#define GPIO_SKL_H_GPP_A7 0x01000007 -#define GPIO_SKL_H_GPP_A8 0x01000008 -#define GPIO_SKL_H_GPP_A9 0x01000009 -#define GPIO_SKL_H_GPP_A10 0x0100000A -#define GPIO_SKL_H_GPP_A11 0x0100000B -#define GPIO_SKL_H_GPP_A12 0x0100000C -#define GPIO_SKL_H_GPP_A13 0x0100000D -#define GPIO_SKL_H_GPP_A14 0x0100000E -#define GPIO_SKL_H_GPP_A15 0x0100000F -#define GPIO_SKL_H_GPP_A16 0x01000010 -#define GPIO_SKL_H_GPP_A17 0x01000011 -#define GPIO_SKL_H_GPP_A18 0x01000012 -#define GPIO_SKL_H_GPP_A19 0x01000013 -#define GPIO_SKL_H_GPP_A20 0x01000014 -#define GPIO_SKL_H_GPP_A21 0x01000015 -#define GPIO_SKL_H_GPP_A22 0x01000016 -#define GPIO_SKL_H_GPP_A23 0x01000017 -#define GPIO_SKL_H_GPP_B0 0x01010000 -#define GPIO_SKL_H_GPP_B1 0x01010001 -#define GPIO_SKL_H_GPP_B2 0x01010002 -#define GPIO_SKL_H_GPP_B3 0x01010003 -#define GPIO_SKL_H_GPP_B4 0x01010004 -#define GPIO_SKL_H_GPP_B5 0x01010005 -#define GPIO_SKL_H_GPP_B6 0x01010006 -#define GPIO_SKL_H_GPP_B7 0x01010007 -#define GPIO_SKL_H_GPP_B8 0x01010008 -#define GPIO_SKL_H_GPP_B9 0x01010009 -#define GPIO_SKL_H_GPP_B10 0x0101000A -#define GPIO_SKL_H_GPP_B11 0x0101000B -#define GPIO_SKL_H_GPP_B12 0x0101000C -#define GPIO_SKL_H_GPP_B13 0x0101000D -#define GPIO_SKL_H_GPP_B14 0x0101000E -#define GPIO_SKL_H_GPP_B15 0x0101000F -#define GPIO_SKL_H_GPP_B16 0x01010010 -#define GPIO_SKL_H_GPP_B17 0x01010011 -#define GPIO_SKL_H_GPP_B18 0x01010012 -#define GPIO_SKL_H_GPP_B19 0x01010013 -#define GPIO_SKL_H_GPP_B20 0x01010014 -#define GPIO_SKL_H_GPP_B21 0x01010015 -#define GPIO_SKL_H_GPP_B22 0x01010016 -#define GPIO_SKL_H_GPP_B23 0x01010017 -#define GPIO_SKL_H_GPP_C0 0x01020000 -#define GPIO_SKL_H_GPP_C1 0x01020001 -#define GPIO_SKL_H_GPP_C2 0x01020002 -#define GPIO_SKL_H_GPP_C3 0x01020003 -#define GPIO_SKL_H_GPP_C4 0x01020004 -#define GPIO_SKL_H_GPP_C5 0x01020005 -#define GPIO_SKL_H_GPP_C6 0x01020006 -#define GPIO_SKL_H_GPP_C7 0x01020007 -#define GPIO_SKL_H_GPP_C8 0x01020008 -#define GPIO_SKL_H_GPP_C9 0x01020009 -#define GPIO_SKL_H_GPP_C10 0x0102000A -#define GPIO_SKL_H_GPP_C11 0x0102000B -#define GPIO_SKL_H_GPP_C12 0x0102000C -#define GPIO_SKL_H_GPP_C13 0x0102000D -#define GPIO_SKL_H_GPP_C14 0x0102000E -#define GPIO_SKL_H_GPP_C15 0x0102000F -#define GPIO_SKL_H_GPP_C16 0x01020010 -#define GPIO_SKL_H_GPP_C17 0x01020011 -#define GPIO_SKL_H_GPP_C18 0x01020012 -#define GPIO_SKL_H_GPP_C19 0x01020013 -#define GPIO_SKL_H_GPP_C20 0x01020014 -#define GPIO_SKL_H_GPP_C21 0x01020015 -#define GPIO_SKL_H_GPP_C22 0x01020016 -#define GPIO_SKL_H_GPP_C23 0x01020017 -#define GPIO_SKL_H_GPP_D0 0x01030000 -#define GPIO_SKL_H_GPP_D1 0x01030001 -#define GPIO_SKL_H_GPP_D2 0x01030002 -#define GPIO_SKL_H_GPP_D3 0x01030003 -#define GPIO_SKL_H_GPP_D4 0x01030004 -#define GPIO_SKL_H_GPP_D5 0x01030005 -#define GPIO_SKL_H_GPP_D6 0x01030006 -#define GPIO_SKL_H_GPP_D7 0x01030007 -#define GPIO_SKL_H_GPP_D8 0x01030008 -#define GPIO_SKL_H_GPP_D9 0x01030009 -#define GPIO_SKL_H_GPP_D10 0x0103000A -#define GPIO_SKL_H_GPP_D11 0x0103000B -#define GPIO_SKL_H_GPP_D12 0x0103000C -#define GPIO_SKL_H_GPP_D13 0x0103000D -#define GPIO_SKL_H_GPP_D14 0x0103000E -#define GPIO_SKL_H_GPP_D15 0x0103000F -#define GPIO_SKL_H_GPP_D16 0x01030010 -#define GPIO_SKL_H_GPP_D17 0x01030011 -#define GPIO_SKL_H_GPP_D18 0x01030012 -#define GPIO_SKL_H_GPP_D19 0x01030013 -#define GPIO_SKL_H_GPP_D20 0x01030014 -#define GPIO_SKL_H_GPP_D21 0x01030015 -#define GPIO_SKL_H_GPP_D22 0x01030016 -#define GPIO_SKL_H_GPP_D23 0x01030017 -#define GPIO_SKL_H_GPP_E0 0x01040000 -#define GPIO_SKL_H_GPP_E1 0x01040001 -#define GPIO_SKL_H_GPP_E2 0x01040002 -#define GPIO_SKL_H_GPP_E3 0x01040003 -#define GPIO_SKL_H_GPP_E4 0x01040004 -#define GPIO_SKL_H_GPP_E5 0x01040005 -#define GPIO_SKL_H_GPP_E6 0x01040006 -#define GPIO_SKL_H_GPP_E7 0x01040007 -#define GPIO_SKL_H_GPP_E8 0x01040008 -#define GPIO_SKL_H_GPP_E9 0x01040009 -#define GPIO_SKL_H_GPP_E10 0x0104000A -#define GPIO_SKL_H_GPP_E11 0x0104000B -#define GPIO_SKL_H_GPP_E12 0x0104000C -#define GPIO_SKL_H_GPP_F0 0x01050000 -#define GPIO_SKL_H_GPP_F1 0x01050001 -#define GPIO_SKL_H_GPP_F2 0x01050002 -#define GPIO_SKL_H_GPP_F3 0x01050003 -#define GPIO_SKL_H_GPP_F4 0x01050004 -#define GPIO_SKL_H_GPP_F5 0x01050005 -#define GPIO_SKL_H_GPP_F6 0x01050006 -#define GPIO_SKL_H_GPP_F7 0x01050007 -#define GPIO_SKL_H_GPP_F8 0x01050008 -#define GPIO_SKL_H_GPP_F9 0x01050009 -#define GPIO_SKL_H_GPP_F10 0x0105000A -#define GPIO_SKL_H_GPP_F11 0x0105000B -#define GPIO_SKL_H_GPP_F12 0x0105000C -#define GPIO_SKL_H_GPP_F13 0x0105000D -#define GPIO_SKL_H_GPP_F14 0x0105000E -#define GPIO_SKL_H_GPP_F15 0x0105000F -#define GPIO_SKL_H_GPP_F16 0x01050010 -#define GPIO_SKL_H_GPP_F17 0x01050011 -#define GPIO_SKL_H_GPP_F18 0x01050012 -#define GPIO_SKL_H_GPP_F19 0x01050013 -#define GPIO_SKL_H_GPP_F20 0x01050014 -#define GPIO_SKL_H_GPP_F21 0x01050015 -#define GPIO_SKL_H_GPP_F22 0x01050016 -#define GPIO_SKL_H_GPP_F23 0x01050017 -#define GPIO_SKL_H_GPP_G0 0x01060000 -#define GPIO_SKL_H_GPP_G1 0x01060001 -#define GPIO_SKL_H_GPP_G2 0x01060002 -#define GPIO_SKL_H_GPP_G3 0x01060003 -#define GPIO_SKL_H_GPP_G4 0x01060004 -#define GPIO_SKL_H_GPP_G5 0x01060005 -#define GPIO_SKL_H_GPP_G6 0x01060006 -#define GPIO_SKL_H_GPP_G7 0x01060007 -#define GPIO_SKL_H_GPP_G8 0x01060008 -#define GPIO_SKL_H_GPP_G9 0x01060009 -#define GPIO_SKL_H_GPP_G10 0x0106000A -#define GPIO_SKL_H_GPP_G11 0x0106000B -#define GPIO_SKL_H_GPP_G12 0x0106000C -#define GPIO_SKL_H_GPP_G13 0x0106000D -#define GPIO_SKL_H_GPP_G14 0x0106000E -#define GPIO_SKL_H_GPP_G15 0x0106000F -#define GPIO_SKL_H_GPP_G16 0x01060010 -#define GPIO_SKL_H_GPP_G17 0x01060011 -#define GPIO_SKL_H_GPP_G18 0x01060012 -#define GPIO_SKL_H_GPP_G19 0x01060013 -#define GPIO_SKL_H_GPP_G20 0x01060014 -#define GPIO_SKL_H_GPP_G21 0x01060015 -#define GPIO_SKL_H_GPP_G22 0x01060016 -#define GPIO_SKL_H_GPP_G23 0x01060017 -#define GPIO_SKL_H_GPP_H0 0x01070000 -#define GPIO_SKL_H_GPP_H1 0x01070001 -#define GPIO_SKL_H_GPP_H2 0x01070002 -#define GPIO_SKL_H_GPP_H3 0x01070003 -#define GPIO_SKL_H_GPP_H4 0x01070004 -#define GPIO_SKL_H_GPP_H5 0x01070005 -#define GPIO_SKL_H_GPP_H6 0x01070006 -#define GPIO_SKL_H_GPP_H7 0x01070007 -#define GPIO_SKL_H_GPP_H8 0x01070008 -#define GPIO_SKL_H_GPP_H9 0x01070009 -#define GPIO_SKL_H_GPP_H10 0x0107000A -#define GPIO_SKL_H_GPP_H11 0x0107000B -#define GPIO_SKL_H_GPP_H12 0x0107000C -#define GPIO_SKL_H_GPP_H13 0x0107000D -#define GPIO_SKL_H_GPP_H14 0x0107000E -#define GPIO_SKL_H_GPP_H15 0x0107000F -#define GPIO_SKL_H_GPP_H16 0x01070010 -#define GPIO_SKL_H_GPP_H17 0x01070011 -#define GPIO_SKL_H_GPP_H18 0x01070012 -#define GPIO_SKL_H_GPP_H19 0x01070013 -#define GPIO_SKL_H_GPP_H20 0x01070014 -#define GPIO_SKL_H_GPP_H21 0x01070015 -#define GPIO_SKL_H_GPP_H22 0x01070016 -#define GPIO_SKL_H_GPP_H23 0x01070017 -#define GPIO_SKL_H_GPP_I0 0x01080000 -#define GPIO_SKL_H_GPP_I1 0x01080001 -#define GPIO_SKL_H_GPP_I2 0x01080002 -#define GPIO_SKL_H_GPP_I3 0x01080003 -#define GPIO_SKL_H_GPP_I4 0x01080004 -#define GPIO_SKL_H_GPP_I5 0x01080005 -#define GPIO_SKL_H_GPP_I6 0x01080006 -#define GPIO_SKL_H_GPP_I7 0x01080007 -#define GPIO_SKL_H_GPP_I8 0x01080008 -#define GPIO_SKL_H_GPP_I9 0x01080009 -#define GPIO_SKL_H_GPP_I10 0x0108000A - -#define GPIO_SKL_H_GPP_J0 0x01090000 -#define GPIO_SKL_H_GPP_J1 0x01090001 -#define GPIO_SKL_H_GPP_J2 0x01090002 -#define GPIO_SKL_H_GPP_J3 0x01090003 -#define GPIO_SKL_H_GPP_J4 0x01090004 -#define GPIO_SKL_H_GPP_J5 0x01090005 -#define GPIO_SKL_H_GPP_J6 0x01090006 -#define GPIO_SKL_H_GPP_J7 0x01090007 -#define GPIO_SKL_H_GPP_J8 0x01090008 -#define GPIO_SKL_H_GPP_J9 0x01090009 -#define GPIO_SKL_H_GPP_J10 0x0109000A -#define GPIO_SKL_H_GPP_J11 0x0109000B -#define GPIO_SKL_H_GPP_J12 0x0109000C -#define GPIO_SKL_H_GPP_J13 0x0109000D -#define GPIO_SKL_H_GPP_J14 0x0109000E -#define GPIO_SKL_H_GPP_J15 0x0109000F -#define GPIO_SKL_H_GPP_J16 0x01090010 -#define GPIO_SKL_H_GPP_J17 0x01090011 -#define GPIO_SKL_H_GPP_J18 0x01090012 -#define GPIO_SKL_H_GPP_J19 0x01090013 -#define GPIO_SKL_H_GPP_J20 0x01090014 -#define GPIO_SKL_H_GPP_J21 0x01090015 -#define GPIO_SKL_H_GPP_J22 0x01090016 -#define GPIO_SKL_H_GPP_J23 0x01090017 -#define GPIO_SKL_H_GPP_K0 0x010A0000 -#define GPIO_SKL_H_GPP_K1 0x010A0001 -#define GPIO_SKL_H_GPP_K2 0x010A0002 -#define GPIO_SKL_H_GPP_K3 0x010A0003 -#define GPIO_SKL_H_GPP_K4 0x010A0004 -#define GPIO_SKL_H_GPP_K5 0x010A0005 -#define GPIO_SKL_H_GPP_K6 0x010A0006 -#define GPIO_SKL_H_GPP_K7 0x010A0007 -#define GPIO_SKL_H_GPP_K8 0x010A0008 -#define GPIO_SKL_H_GPP_K9 0x010A0009 -#define GPIO_SKL_H_GPP_K10 0x010A000A -#define GPIO_SKL_H_GPP_L2 0x010B0002 -#define GPIO_SKL_H_GPP_L3 0x010B0003 -#define GPIO_SKL_H_GPP_L4 0x010B0004 -#define GPIO_SKL_H_GPP_L5 0x010B0005 -#define GPIO_SKL_H_GPP_L6 0x010B0006 -#define GPIO_SKL_H_GPP_L7 0x010B0007 -#define GPIO_SKL_H_GPP_L8 0x010B0008 -#define GPIO_SKL_H_GPP_L9 0x010B0009 -#define GPIO_SKL_H_GPP_L10 0x010B000A -#define GPIO_SKL_H_GPP_L11 0x010B000B -#define GPIO_SKL_H_GPP_L12 0x010B000C -#define GPIO_SKL_H_GPP_L13 0x010B000D -#define GPIO_SKL_H_GPP_L14 0x010B000E -#define GPIO_SKL_H_GPP_L15 0x010B000F -#define GPIO_SKL_H_GPP_L16 0x010B0010 -#define GPIO_SKL_H_GPP_L17 0x010B0011 -#define GPIO_SKL_H_GPP_L18 0x010B0012 -#define GPIO_SKL_H_GPP_L19 0x010B0013 -#define GPIO_SKL_H_GPD0 0x010C0000 -#define GPIO_SKL_H_GPD1 0x010C0001 -#define GPIO_SKL_H_GPD2 0x010C0002 -#define GPIO_SKL_H_GPD3 0x010C0003 -#define GPIO_SKL_H_GPD4 0x010C0004 -#define GPIO_SKL_H_GPD5 0x010C0005 -#define GPIO_SKL_H_GPD6 0x010C0006 -#define GPIO_SKL_H_GPD7 0x010C0007 -#define GPIO_SKL_H_GPD8 0x010C0008 -#define GPIO_SKL_H_GPD9 0x010C0009 -#define GPIO_SKL_H_GPD10 0x010C000A -#define GPIO_SKL_H_GPD11 0x010C000B - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Gerrit-Change-Number: 39453 Gerrit-PatchSet: 42 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/tiogapass: fix advansed _PAD_CFG_STRUCT macros in config
by Maxim Polyakov (Code Review) 02 May '20

02 May '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40732 ) Change subject: mb/ocp/tiogapass: fix advansed _PAD_CFG_STRUCT macros in config ...................................................................... mb/ocp/tiogapass: fix advansed _PAD_CFG_STRUCT macros in config If the current pad configuration can not be determined using standard macros from the gpio_defs.h [1], then the intelp2m utility generates "advanced" _PAD_CFG_STRUCT() macros. However, often this configuration in the vendor’s firmware is erroneous. Change the extended macros to standard ones taking into account the information based on the schematic diagram and the previous GPIO configuration for FSP-M [2]. [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/40732/1 diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h index 77ae5ff..594ea6f 100644 --- a/src/mainboard/ocp/tiogapass/gpio.h +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -120,7 +120,7 @@ /* GPP_F4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, DEEP, OFF, DRIVER), /* GPP_F6 - GPIO */ PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 0, PLTRST, NONE), /* GPP_F7 - GPIO */ @@ -175,13 +175,13 @@ /* GPP_C9 - GPIO */ PAD_CFG_GPO_GPIO_DRIVER(GPP_C9, 1, DEEP, NONE), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, EDGE_BOTH, ACPI), /* GPP_C11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, DEEP, OFF, DRIVER), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, DEEP, OFF, DRIVER), /* GPP_C14 - GPIO */ PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), /* GPP_C15 - GPIO */ @@ -296,7 +296,7 @@ /* GPD6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ @@ -433,15 +433,15 @@ /* GPP_G11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, DEEP, OFF, DRIVER), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, DRIVER), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, DEEP, OFF, DRIVER), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, DEEP, OFF, DRIVER), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), /* GPP_G17 - ADR_COMPLETE */ PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805 Gerrit-Change-Number: 40732 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs
by Maxim Polyakov (Code Review) 02 May '20

02 May '20

Hello build bot (Jenkins), Andrey Petrov, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39453 to look at the new patch set (#41). Change subject: xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs ...................................................................... xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- D src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h D src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h 2 files changed, 0 insertions(+), 1,315 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/39453/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/39453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Gerrit-Change-Number: 39453 Gerrit-PatchSet: 41 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/tiogapass: use common driver to configure GPIO
by 9elements QA (Code Review) 02 May '20

02 May '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39427 ) Change subject: mb/tiogapass: use common driver to configure GPIO ...................................................................... Patch Set 43: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3070 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3069 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3068 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3067 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Gerrit-Change-Number: 39427 Gerrit-PatchSet: 43 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 22:03:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: xhci: Do not memcpy registers
by Julius Werner (Code Review) 02 May '20

02 May '20

Hello Duncan Laurie, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40895 to review the following change. Change subject: libpayload: xhci: Do not memcpy registers ...................................................................... libpayload: xhci: Do not memcpy registers memcpy() is meant to be used on normal memory and often implemented with architecture-specific optimizations to make that as performant as possible. MMIO registers often have special access restrictions that may be incompatible with whatever memcpy() does. For example, on arm64 it uses the LDP (load pair) to load 16 bytes at a time, which makes 4-byte MMIO registers unhappy. This patch removes the caching of the XHCI capreg registers and changes it back to a pointer. The CAP_GET() macro is still accessing a full (non-bitfield) uint32_t at the end so this should still generate a 4-byte access (which was the goal of the original change in CB:39838). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Id058c8813087a8e8cb85f570399e07fb8a597108 --- M payloads/libpayload/drivers/usb/xhci.c M payloads/libpayload/drivers/usb/xhci_private.h 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40895/1 diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 2f61f86..ef1d73f 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -185,15 +185,15 @@ goto _free_xhci; } - memcpy(&xhci->capreg, phys_to_virt(physical_bar), sizeof(xhci->capreg)); + xhci->capreg = phys_to_virt(physical_bar) + sizeof(xhci->capreg); xhci->opreg = phys_to_virt(physical_bar) + CAP_GET(CAPLEN, xhci->capreg); - xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg.rtsoff; - xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg.dboff; + xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg->rtsoff; + xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg->dboff; xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar); xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg)); - xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg.rtsoff); - xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg.dboff); + xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff); + xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff); xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n", CAP_GET(CAPVER_HI, xhci->capreg), CAP_GET(CAPVER_LO, xhci->capreg)); diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 65c3fdd..0264f1f 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -364,7 +364,7 @@ #define CAP_CSZ_LEN 1 #define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN) -#define CAP_GET(tok, cap) (((cap).CAP_##tok##_FIELD & CAP_MASK(tok)) \ +#define CAP_GET(tok, cap) (((cap)->CAP_##tok##_FIELD & CAP_MASK(tok)) \ >> CAP_##tok##_START) #define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32) @@ -378,7 +378,7 @@ u32 hccparams; u32 dboff; u32 rtsoff; - } __packed capreg; + } __packed *capreg; /* opreg is R/W is most places, so volatile access is necessary. volatile means that the compiler seeks byte writes if possible, -- To view, visit https://review.coreboot.org/c/coreboot/+/40895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id058c8813087a8e8cb85f570399e07fb8a597108 Gerrit-Change-Number: 40895 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/tiogapass: use common driver to configure GPIO
by Andrey Petrov (Code Review) 01 May '20

01 May '20

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39427 ) Change subject: mb/tiogapass: use common driver to configure GPIO ...................................................................... mb/tiogapass: use common driver to configure GPIO According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with AMI firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39427 Reviewed-by: Andrey Petrov <andrey.petrov(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/gpio.h M src/mainboard/ocp/tiogapass/romstage.c 3 files changed, 552 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Andrey Petrov: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index 67808ef..dbb3b6a 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -10,6 +10,7 @@ #include <soc/pcr_ids.h> #include <superio/aspeed/ast2400/ast2400.h> #include <superio/aspeed/common/aspeed.h> +#include "gpio.h" /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ #define PCR_DMI_LPCIOD 0x2770 @@ -53,6 +54,9 @@ void bootblock_mainboard_early_init(void) { + /* pre-configure Lewisburg PCH GPIO pads */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + /* Open IO windows */ enable_espi_lpc_io_windows(); diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h new file mode 100644 index 0000000..823f797 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -0,0 +1,544 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef CFG_PCH_GPIO_H +#define CFG_PCH_GPIO_H + +#include <soc/gpio.h> + +/* Pad configuration */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - GPIO */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), + /* GPP_A1 - LAD0 */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), + /* GPP_A2 - LAD1 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), + /* GPP_A3 - LAD2 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), + /* GPP_A4 - LAD3 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), + /* GPP_A5 - LFRAME# */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), + /* GPP_A6 - SERIRQ */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), + /* GPP_A7 - PIRQA# */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010), + /* GPP_A8 - CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000500, 0x00000010), + /* GPP_A9 - CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x00000010), + /* GPP_A10 - GPIO */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000102, 0x00000010), + /* GPP_A11 - GPIO */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + /* GPP_A12 - GPIO */ + _PAD_CFG_STRUCT(GPP_A12, 0x84000102, 0x00000010), + /* GPP_A13 - GPIO */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000102, 0x00000010), + /* GPP_A14 - GPIO */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000102, 0x00000010), + /* GPP_A15 - GPIO */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000102, 0x00000010), + /* GPP_A16 - GPIO */ + _PAD_CFG_STRUCT(GPP_A16, 0x44000102, 0x00000010), + /* GPP_A17 - GPIO */ + _PAD_CFG_STRUCT(GPP_A17, 0x44000102, 0x00000010), + /* GPP_A18 - GPIO */ + _PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x00000010), + /* GPP_A19 - RESERVED */ + /* GPP_A20 - GPIO */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000102, 0x00000010), + /* GPP_A21 - GPIO */ + _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x00000010), + /* GPP_A22 - GPIO */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000102, 0x00000010), + /* GPP_A23 - GPIO */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x00000010), + + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - CORE_VID0 */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000600, 0x00000010), + /* GPP_B1 - CORE_VID1 */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000600, 0x00000010), + /* GPP_B2 - GPIO */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000102, 0x00000010), + /* GPP_B3 - GPIO */ + _PAD_CFG_STRUCT(GPP_B3, 0x44000102, 0x00000010), + /* GPP_B4 - GPIO */ + _PAD_CFG_STRUCT(GPP_B4, 0x44000102, 0x00000010), + /* GPP_B5 - GPIO */ + _PAD_CFG_STRUCT(GPP_B5, 0x44000102, 0x00000010), + /* GPP_B6 - GPIO */ + _PAD_CFG_STRUCT(GPP_B6, 0x84000102, 0x00000010), + /* GPP_B7 - GPIO */ + _PAD_CFG_STRUCT(GPP_B7, 0x84000102, 0x00000010), + /* GPP_B8 - GPIO */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000102, 0x00000010), + /* GPP_B9 - GPIO */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000102, 0x00000010), + /* GPP_B10 - GPIO */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x00000010), + /* GPP_B11 - GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x00000010), + /* GPP_B12 - GLB_RST_WARN_N# */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000600, 0x00000010), + /* GPP_B13 - PLTRST# */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000600, 0x00000010), + /* GPP_B14 - SPKR */ + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x00000010), + /* GPP_B15 - GPIO */ + _PAD_CFG_STRUCT(GPP_B15, 0x44000102, 0x00000010), + /* GPP_B16 - GPIO */ + _PAD_CFG_STRUCT(GPP_B16, 0x44000102, 0x00000010), + /* GPP_B17 - GPIO */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000102, 0x00000010), + /* GPP_B18 - GPIO */ + _PAD_CFG_STRUCT(GPP_B18, 0x44000102, 0x00000010), + /* GPP_B19 - GPIO */ + _PAD_CFG_STRUCT(GPP_B19, 0x44000201, 0x00000010), + /* GPP_B20 - GPIO */ + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x00000010), + /* GPP_B21 - GPIO */ + _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x00000010), + /* GPP_B22 - GPIO */ + _PAD_CFG_STRUCT(GPP_B22, 0x44000200, 0x00000010), + /* GPP_B23 - PCHHOT# */ + _PAD_CFG_STRUCT(GPP_B23, 0x00000a00, 0x00000010), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - GPIO */ + _PAD_CFG_STRUCT(GPP_F0, 0x44000102, 0x00000010), + /* GPP_F1 - GPIO */ + _PAD_CFG_STRUCT(GPP_F1, 0x44000102, 0x00000010), + /* GPP_F2 - GPIO */ + _PAD_CFG_STRUCT(GPP_F2, 0x44000102, 0x00000010), + /* GPP_F3 - GPIO */ + _PAD_CFG_STRUCT(GPP_F3, 0x44000102, 0x00000010), + /* GPP_F4 - GPIO */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x00000010), + /* GPP_F5 - GPIO */ + _PAD_CFG_STRUCT(GPP_F5, 0x44000101, 0x00000010), + /* GPP_F6 - GPIO */ + _PAD_CFG_STRUCT(GPP_F6, 0x84000200, 0x00000010), + /* GPP_F7 - GPIO */ + _PAD_CFG_STRUCT(GPP_F7, 0x84000200, 0x00000010), + /* GPP_F8 - GPIO */ + _PAD_CFG_STRUCT(GPP_F8, 0x84000200, 0x00000010), + /* GPP_F9 - GPIO */ + _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000010), + /* GPP_F10 - SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F10, 0x44000600, 0x00000010), + /* GPP_F11 - SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F11, 0x44000600, 0x00000010), + /* GPP_F12 - GPIO */ + _PAD_CFG_STRUCT(GPP_F12, 0x44000102, 0x00000010), + /* GPP_F13 - SATA_SDATAOUT2 */ + _PAD_CFG_STRUCT(GPP_F13, 0x44000600, 0x00000010), + /* GPP_F14 - SSATA_LED# */ + _PAD_CFG_STRUCT(GPP_F14, 0x44000e00, 0x00000010), + /* GPP_F15 - GPIO */ + _PAD_CFG_STRUCT(GPP_F15, 0x44000102, 0x00000010), + /* GPP_F16 - GPIO */ + _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x00000010), + /* GPP_F17 - GPIO */ + _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x00000010), + /* GPP_F18 - GPIO */ + _PAD_CFG_STRUCT(GPP_F18, 0x44000102, 0x00000010), + /* GPP_F19 - LAN_SMBCLK */ + _PAD_CFG_STRUCT(GPP_F19, 0x44000502, 0x00000010), + /* GPP_F20 - LAN_SMBDATA */ + _PAD_CFG_STRUCT(GPP_F20, 0x44000502, 0x00000010), + /* GPP_F21 - LAN_SMBALRT# */ + _PAD_CFG_STRUCT(GPP_F21, 0x44000602, 0x00000010), + /* GPP_F22 - SSATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F22, 0x44000e00, 0x00000010), + /* GPP_F23 - SSATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F23, 0x44000e00, 0x00000010), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + /* GPP_C2 - SMBALERT# */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000502, 0x00000010), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + /* GPP_C5 - GPIO */ + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x00000000), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + /* GPP_C8 - GPIO */ + _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x00000010), + /* GPP_C9 - GPIO */ + _PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x00000010), + /* GPP_C10 - GPIO */ + _PAD_CFG_STRUCT(GPP_C10, 0x86000103, 0x00000000), + /* GPP_C11 - GPIO */ + _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x00000010), + /* GPP_C12 - GPIO */ + _PAD_CFG_STRUCT(GPP_C12, 0x44000103, 0x00000010), + /* GPP_C13 - GPIO */ + _PAD_CFG_STRUCT(GPP_C13, 0x44000103, 0x00000010), + /* GPP_C14 - GPIO */ + _PAD_CFG_STRUCT(GPP_C14, 0x80080102, 0x00000000), + /* GPP_C15 - GPIO */ + _PAD_CFG_STRUCT(GPP_C15, 0x44000102, 0x00000010), + /* GPP_C16 - GPIO */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000102, 0x00000010), + /* GPP_C17 - GPIO */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000102, 0x00000010), + /* GPP_C18 - GPIO */ + _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x00000010), + /* GPP_C19 - GPIO */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x00000010), + /* GPP_C20 - RESERVED */ + /* GPP_C21 - GPIO */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x00000010), + /* GPP_C22 - GPIO */ + _PAD_CFG_STRUCT(GPP_C22, 0x80040102, 0x00000000), + /* GPP_C23 - GPIO */ + _PAD_CFG_STRUCT(GPP_C23, 0x40840102, 0x00000000), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + _PAD_CFG_STRUCT(GPP_D0, 0x80840102, 0x00000000), + /* GPP_D1 - GPIO */ + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x00000010), + /* GPP_D2 - GPIO */ + _PAD_CFG_STRUCT(GPP_D2, 0x84000102, 0x00000010), + /* GPP_D3 - GPIO */ + _PAD_CFG_STRUCT(GPP_D3, 0x84000102, 0x00000010), + /* GPP_D4 - GPIO */ + _PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x00000010), + /* GPP_D5 - GPIO */ + _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x00000010), + /* GPP_D6 - GPIO */ + _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x00000010), + /* GPP_D7 - GPIO */ + _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x00000010), + /* GPP_D8 - GPIO */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x00000010), + /* GPP_D9 - GPIO */ + _PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x00000010), + /* GPP_D10 - GPIO */ + _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x00000010), + /* GPP_D11 - GPIO */ + _PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x00000010), + /* GPP_D12 - GPIO */ + _PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x00000010), + /* GPP_D13 - GPIO */ + _PAD_CFG_STRUCT(GPP_D13, 0x44000102, 0x00000010), + /* GPP_D14 - GPIO */ + _PAD_CFG_STRUCT(GPP_D14, 0x44000102, 0x00000010), + /* GPP_D15 - SSATA_SDATAOUT0 */ + _PAD_CFG_STRUCT(GPP_D15, 0x44000e00, 0x00000010), + /* GPP_D16 - GPIO */ + _PAD_CFG_STRUCT(GPP_D16, 0x44000102, 0x00000010), + /* GPP_D17 - GPIO */ + _PAD_CFG_STRUCT(GPP_D17, 0x44000102, 0x00000010), + /* GPP_D18 - GPIO */ + _PAD_CFG_STRUCT(GPP_D18, 0x44000102, 0x00000010), + /* GPP_D19 - GPIO */ + _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x00000010), + /* GPP_D20 - GPIO */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000102, 0x00000010), + /* GPP_D21 - GPIO */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x00000010), + /* GPP_D22 - GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0x44000102, 0x00000010), + /* GPP_D23 - GPIO */ + _PAD_CFG_STRUCT(GPP_D23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - GPIO */ + _PAD_CFG_STRUCT(GPP_E0, 0x40040102, 0x00000010), + /* GPP_E1 - GPIO */ + _PAD_CFG_STRUCT(GPP_E1, 0x40040102, 0x00000010), + /* GPP_E2 - GPIO */ + _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x00000010), + /* GPP_E3 - CPU_GP0 */ + _PAD_CFG_STRUCT(GPP_E3, 0x44000502, 0x00000010), + /* GPP_E4 - GPIO */ + _PAD_CFG_STRUCT(GPP_E4, 0x44000102, 0x00000010), + /* GPP_E5 - GPIO */ + _PAD_CFG_STRUCT(GPP_E5, 0x44000102, 0x00000010), + /* GPP_E6 - GPIO */ + _PAD_CFG_STRUCT(GPP_E6, 0x44000102, 0x00000010), + /* GPP_E7 - GPIO */ + _PAD_CFG_STRUCT(GPP_E7, 0x44000102, 0x00000010), + /* GPP_E8 - SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000600, 0x00000010), + /* GPP_E9 - USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E9, 0x44000502, 0x00000010), + /* GPP_E10 - GPIO */ + _PAD_CFG_STRUCT(GPP_E10, 0x44000102, 0x00000010), + /* GPP_E11 - GPIO */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000102, 0x00000010), + /* GPP_E12 - GPIO */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000102, 0x00000010), + + /* ------- GPIO Community 2 ------- */ + /* -------- GPIO Group GPD -------- */ + /* GPD0 - RESERVED */ + /* GPD1 - GPIO */ + _PAD_CFG_STRUCT(GPD1, 0x04000102, 0x00000000), + /* GPD2 - GPIO */ + _PAD_CFG_STRUCT(GPD2, 0x04000102, 0x00000000), + /* GPD3 - PWRBTN# */ + _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + /* GPD4 - SLP_S3# */ + _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + /* GPD5 - SLP_S4# */ + _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + /* GPD6 - GPIO */ + _PAD_CFG_STRUCT(GPD6, 0x04000100, 0x00000000), + /* GPD7 - GPIO */ + _PAD_CFG_STRUCT(GPD7, 0x04000103, 0x00000000), + /* GPD8 - GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + /* GPD9 - GPIO */ + _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + /* GPD10 - GPIO */ + _PAD_CFG_STRUCT(GPD10, 0x04000102, 0x00000000), + /* GPD11 - GBEPHY */ + _PAD_CFG_STRUCT(GPD11, 0x04000500, 0x00000000), + + /* ------- GPIO Community 3 ------- */ + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - LAN_TDO */ + _PAD_CFG_STRUCT(GPP_I0, 0x44000900, 0x00000010), + /* GPP_I1 - LAN_TCK */ + _PAD_CFG_STRUCT(GPP_I1, 0x44000a02, 0x00000010), + /* GPP_I2 - LAN_TMS */ + _PAD_CFG_STRUCT(GPP_I2, 0x44000a02, 0x00000010), + /* GPP_I3 - LAN_TDI */ + _PAD_CFG_STRUCT(GPP_I3, 0x44000a02, 0x00000010), + /* GPP_I4 - GPIO */ + _PAD_CFG_STRUCT(GPP_I4, 0x44000102, 0x00000010), + /* GPP_I5 - GPIO */ + _PAD_CFG_STRUCT(GPP_I5, 0x44000102, 0x00000010), + /* GPP_I6 - GPIO */ + _PAD_CFG_STRUCT(GPP_I6, 0x44000102, 0x00000010), + /* GPP_I7 - LAN_TRST_IN */ + _PAD_CFG_STRUCT(GPP_I7, 0x44000902, 0x00000010), + /* GPP_I8 - GPIO */ + _PAD_CFG_STRUCT(GPP_I8, 0x44000102, 0x00000010), + /* GPP_I9 - GPIO */ + _PAD_CFG_STRUCT(GPP_I9, 0x44000102, 0x00000010), + /* GPP_I10 - GPIO */ + _PAD_CFG_STRUCT(GPP_I10, 0x44000102, 0x00000010), + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_J ------- */ + /* GPP_J0 - LAN_LED_P0_0 */ + _PAD_CFG_STRUCT(GPP_J0, 0x44000600, 0x00000010), + /* GPP_J1 - LAN_LED_P0_1 */ + _PAD_CFG_STRUCT(GPP_J1, 0x44000600, 0x00000010), + /* GPP_J2 - LAN_LED_P1_0 */ + _PAD_CFG_STRUCT(GPP_J2, 0x44000600, 0x00000010), + /* GPP_J3 - LAN_LED_P1_1 */ + _PAD_CFG_STRUCT(GPP_J3, 0x44000600, 0x00000010), + /* GPP_J4 - LAN_LED_P2_0 */ + _PAD_CFG_STRUCT(GPP_J4, 0x44000600, 0x00000010), + /* GPP_J5 - LAN_LED_P2_1 */ + _PAD_CFG_STRUCT(GPP_J5, 0x44000600, 0x00000010), + /* GPP_J6 - LAN_LED_P3_0 */ + _PAD_CFG_STRUCT(GPP_J6, 0x44000600, 0x00000010), + /* GPP_J7 - LAN_LED_P3_1 */ + _PAD_CFG_STRUCT(GPP_J7, 0x44000600, 0x00000010), + /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ + _PAD_CFG_STRUCT(GPP_J8, 0x44000602, 0x00000010), + /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ + _PAD_CFG_STRUCT(GPP_J9, 0x44000402, 0x00000010), + /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ + _PAD_CFG_STRUCT(GPP_J10, 0x44000602, 0x00000010), + /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ + _PAD_CFG_STRUCT(GPP_J11, 0x44000402, 0x00000010), + /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ + _PAD_CFG_STRUCT(GPP_J12, 0x44000602, 0x00000010), + /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ + _PAD_CFG_STRUCT(GPP_J13, 0x44000402, 0x00000010), + /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ + _PAD_CFG_STRUCT(GPP_J14, 0x44000602, 0x00000010), + /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ + _PAD_CFG_STRUCT(GPP_J15, 0x44000402, 0x00000010), + /* GPP_J16 - LAN_SDP_P0_0 */ + _PAD_CFG_STRUCT(GPP_J16, 0x44000502, 0x00000010), + /* GPP_J17 - GPIO */ + _PAD_CFG_STRUCT(GPP_J17, 0x44000102, 0x00000010), + /* GPP_J18 - LAN_SDP_P1_0 */ + _PAD_CFG_STRUCT(GPP_J18, 0x44000502, 0x00000010), + /* GPP_J19 - GPIO */ + _PAD_CFG_STRUCT(GPP_J19, 0x44000102, 0x00000010), + /* GPP_J20 - LAN_SDP_P2_0 */ + _PAD_CFG_STRUCT(GPP_J20, 0x44000502, 0x00000010), + /* GPP_J21 - GPIO */ + _PAD_CFG_STRUCT(GPP_J21, 0x44000102, 0x00000010), + /* GPP_J22 - LAN_SDP_P3_0 */ + _PAD_CFG_STRUCT(GPP_J22, 0x44000502, 0x00000010), + /* GPP_J23 - GPIO */ + _PAD_CFG_STRUCT(GPP_J23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_K ------- */ + /* GPP_K0 - GPIO */ + _PAD_CFG_STRUCT(GPP_K0, 0x44000100, 0x00000010), + /* GPP_K1 - GPIO */ + _PAD_CFG_STRUCT(GPP_K1, 0x44000100, 0x00000010), + /* GPP_K2 - GPIO */ + _PAD_CFG_STRUCT(GPP_K2, 0x44000100, 0x00000010), + /* GPP_K3 - GPIO */ + _PAD_CFG_STRUCT(GPP_K3, 0x44000100, 0x00000010), + /* GPP_K4 - GPIO */ + _PAD_CFG_STRUCT(GPP_K4, 0x44000100, 0x00000010), + /* GPP_K5 - GPIO */ + _PAD_CFG_STRUCT(GPP_K5, 0x44000102, 0x00000010), + /* GPP_K6 - GPIO */ + _PAD_CFG_STRUCT(GPP_K6, 0x44000102, 0x00000010), + /* GPP_K7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_K7, 0x44000600, 0x00000010), + /* GPP_K8 - LAN_NCSI_ARB_IN */ + _PAD_CFG_STRUCT(GPP_K8, 0x44000502, 0x00000010), + /* GPP_K9 - LAN_NCSI_ARB_OUT */ + _PAD_CFG_STRUCT(GPP_K9, 0x44000602, 0x00000010), + /* GPP_K10 - PE_RST# */ + _PAD_CFG_STRUCT(GPP_K10, 0x44000502, 0x00000010), + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_G ------- */ + /* GPP_G0 - GPIO */ + _PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x00000010), + /* GPP_G1 - GPIO */ + _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x00000010), + /* GPP_G2 - GPIO */ + _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000010), + /* GPP_G3 - GPIO */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000010), + /* GPP_G4 - GPIO */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000102, 0x00000010), + /* GPP_G5 - GPIO */ + _PAD_CFG_STRUCT(GPP_G5, 0x44000102, 0x00000010), + /* GPP_G6 - GPIO */ + _PAD_CFG_STRUCT(GPP_G6, 0x44000102, 0x00000010), + /* GPP_G7 - GPIO */ + _PAD_CFG_STRUCT(GPP_G7, 0x44000102, 0x00000010), + /* GPP_G8 - GPIO */ + _PAD_CFG_STRUCT(GPP_G8, 0x44000102, 0x00000010), + /* GPP_G9 - GPIO */ + _PAD_CFG_STRUCT(GPP_G9, 0x44000102, 0x00000010), + /* GPP_G10 - GPIO */ + _PAD_CFG_STRUCT(GPP_G10, 0x44000102, 0x00000010), + /* GPP_G11 - GPIO */ + _PAD_CFG_STRUCT(GPP_G11, 0x44000102, 0x00000010), + /* GPP_G12 - GPIO */ + _PAD_CFG_STRUCT(GPP_G12, 0x44000103, 0x00000010), + /* GPP_G13 - GPIO */ + _PAD_CFG_STRUCT(GPP_G13, 0x44000103, 0x00000010), + /* GPP_G14 - GPIO */ + _PAD_CFG_STRUCT(GPP_G14, 0x44000101, 0x00000010), + /* GPP_G15 - GPIO */ + _PAD_CFG_STRUCT(GPP_G15, 0x44000101, 0x00000010), + /* GPP_G16 - GPIO */ + _PAD_CFG_STRUCT(GPP_G16, 0x44000101, 0x00000010), + /* GPP_G17 - ADR_COMPLETE */ + _PAD_CFG_STRUCT(GPP_G17, 0x44000600, 0x00000010), + /* GPP_G18 - NMI# */ + _PAD_CFG_STRUCT(GPP_G18, 0x44000600, 0x00000010), + /* GPP_G19 - SMI# */ + _PAD_CFG_STRUCT(GPP_G19, 0x44000600, 0x00000010), + /* GPP_G20 - RESERVED */ + /* GPP_G21 - GPIO */ + _PAD_CFG_STRUCT(GPP_G21, 0x44000100, 0x00000010), + /* GPP_G22 - GPIO */ + _PAD_CFG_STRUCT(GPP_G22, 0x44000201, 0x00000010), + /* GPP_G23 - GPIO */ + _PAD_CFG_STRUCT(GPP_G23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + _PAD_CFG_STRUCT(GPP_H0, 0x44000102, 0x00000010), + /* GPP_H1 - GPIO */ + _PAD_CFG_STRUCT(GPP_H1, 0x44000102, 0x00000010), + /* GPP_H2 - GPIO */ + _PAD_CFG_STRUCT(GPP_H2, 0x44000102, 0x00000010), + /* GPP_H3 - GPIO */ + _PAD_CFG_STRUCT(GPP_H3, 0x44000102, 0x00000010), + /* GPP_H4 - GPIO */ + _PAD_CFG_STRUCT(GPP_H4, 0x44000102, 0x00000010), + /* GPP_H5 - RESERVED */ + /* GPP_H6 - GPIO */ + _PAD_CFG_STRUCT(GPP_H6, 0x44000102, 0x00000010), + /* GPP_H7 - GPIO */ + _PAD_CFG_STRUCT(GPP_H7, 0x44000102, 0x00000010), + /* GPP_H8 - GPIO */ + _PAD_CFG_STRUCT(GPP_H8, 0x44000102, 0x00000010), + /* GPP_H9 - GPIO */ + _PAD_CFG_STRUCT(GPP_H9, 0x44000102, 0x00000010), + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + /* GPP_H12 - GPIO */ + _PAD_CFG_STRUCT(GPP_H12, 0x44000102, 0x00000010), + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + /* GPP_H15 - GPIO */ + _PAD_CFG_STRUCT(GPP_H15, 0x84000102, 0x00000010), + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + /* GPP_H18 - GPIO */ + _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x00000010), + /* GPP_H19 - GPIO */ + _PAD_CFG_STRUCT(GPP_H19, 0x84000102, 0x00000010), + /* GPP_H20 - GPIO */ + _PAD_CFG_STRUCT(GPP_H20, 0x44000102, 0x00000010), + /* GPP_H21 - GPIO */ + _PAD_CFG_STRUCT(GPP_H21, 0x44000102, 0x00000010), + /* GPP_H22 - GPIO */ + _PAD_CFG_STRUCT(GPP_H22, 0x44000102, 0x00000010), + /* GPP_H23 - GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x44000102, 0x00000010), + + /* ------- GPIO Group GPP_L ------- */ + /* GPP_L0 - RESERVED */ + /* GPP_L1 - CSME_INTR_OUT */ + _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + /* GPP_L2 - GPIO */ + _PAD_CFG_STRUCT(GPP_L2, 0x44000100, 0x00000010), + /* GPP_L3 - GPIO */ + _PAD_CFG_STRUCT(GPP_L3, 0x44000100, 0x00000010), + /* GPP_L4 - GPIO */ + _PAD_CFG_STRUCT(GPP_L4, 0x44000100, 0x00000010), + /* GPP_L5 - GPIO */ + _PAD_CFG_STRUCT(GPP_L5, 0x44000100, 0x00000010), + /* GPP_L6 - GPIO */ + _PAD_CFG_STRUCT(GPP_L6, 0x44000102, 0x00000010), + /* GPP_L7 - GPIO */ + _PAD_CFG_STRUCT(GPP_L7, 0x44000102, 0x00000010), + /* GPP_L8 - GPIO */ + _PAD_CFG_STRUCT(GPP_L8, 0x44000102, 0x00000010), + /* GPP_L9 - GPIO */ + _PAD_CFG_STRUCT(GPP_L9, 0x44000102, 0x00000010), + /* GPP_L10 - GPIO */ + _PAD_CFG_STRUCT(GPP_L10, 0x44000100, 0x00000010), + /* GPP_L11 - GPIO */ + _PAD_CFG_STRUCT(GPP_L11, 0x44000100, 0x00000010), + /* GPP_L12 - GPIO */ + _PAD_CFG_STRUCT(GPP_L12, 0x44000100, 0x00000010), + /* GPP_L13 - GPIO */ + _PAD_CFG_STRUCT(GPP_L13, 0x44000100, 0x00000010), + /* GPP_L14 - GPIO */ + _PAD_CFG_STRUCT(GPP_L14, 0x44000100, 0x00000010), + /* GPP_L15 - GPIO */ + _PAD_CFG_STRUCT(GPP_L15, 0x44000100, 0x00000010), + /* GPP_L16 - GPIO */ + _PAD_CFG_STRUCT(GPP_L16, 0x44000100, 0x00000010), + /* GPP_L17 - GPIO */ + _PAD_CFG_STRUCT(GPP_L17, 0x44000100, 0x00000010), + /* GPP_L18 - GPIO */ + _PAD_CFG_STRUCT(GPP_L18, 0x44000100, 0x00000010), + /* GPP_L19 - GPIO */ + _PAD_CFG_STRUCT(GPP_L19, 0x44000100, 0x00000010), +}; + +#endif /* CFG_PCH_GPIO_H */ diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index e4a188d..41f7856 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -20,7 +20,6 @@ #include <gpio.h> #include <soc/lewisburg_pch_gpio_defs.h> -#include "skxsp_tp_gpio.h" #include "skxsp_tp_iio.h" static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; @@ -39,16 +38,6 @@ = IIO_BIFURCATE_xxx8xxx8; } -/* -* Configure GPIO depend on platform -*/ -static void mainboard_config_gpios(FSPM_UPD *mupd) -{ - mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table; - mupd->FspmConfig.GpioConfig.NumberOfEntries = - sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG); -} - static void mainboard_config_iio(FSPM_UPD *mupd) { memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); @@ -74,6 +63,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - mainboard_config_gpios(mupd); mainboard_config_iio(mupd); + + /* do not configure GPIO controller inside FSP-M */ + mupd->FspmConfig.GpioConfig.GpioTable = NULL; + mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Gerrit-Change-Number: 39427 Gerrit-PatchSet: 43 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/postcar: Add x86_64 support
by Raul Rangel (Code Review) 01 May '20

01 May '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 25: Code-Review+1 (1 comment) > Patch Set 25: > > > Patch Set 25: > > > > What's the status of this patchset? > > The whole patch chain waits for review and testing. As there was no feedback in month I dropped the interest in this. It was successfully tested on QEMU and Intel Nehalem platforms, so it's definitely working on blob free platforms. With the patches you have landed, is it possible to enable paging on x86_32? Would be nice to have it to catch stack overflows or writes to random sections of memory. https://review.coreboot.org/c/coreboot/+/30500/25/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S: https://review.coreboot.org/c/coreboot/+/30500/25/src/arch/x86/exit_car.S@39 PS25, Line 39: edx_eax Can you swap the edx and eax in the name so it reads like the operations are executing. -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 25 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 21:36:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2020