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Change in coreboot[master]: mb/purism/librem_bdw: Convert to use override devicetree
by Matt DeVillier (Code Review) 02 May '20

02 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40915 ) Change subject: mb/purism/librem_bdw: Convert to use override devicetree ...................................................................... mb/purism/librem_bdw: Convert to use override devicetree Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I07fb5a09e578bf299081b26e010317385a6c5f7f --- M src/mainboard/purism/librem_bdw/Kconfig R src/mainboard/purism/librem_bdw/devicetree.cb D src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb A src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb A src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 5 files changed, 31 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40915/1 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 7a8bc22..1f17f75 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -17,9 +17,9 @@ default "librem13v1" if BOARD_PURISM_LIBREM13_V1 default "librem15v2" if BOARD_PURISM_LIBREM15_V2 -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config DRIVERS_PS2_KEYBOARD def_bool y diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb similarity index 90% rename from src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb rename to src/mainboard/purism/librem_bdw/devicetree.cb index cbd59be..13b9e5e 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -21,14 +21,6 @@ register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" - # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device cpu_cluster 0 on device lapic 0 on end end @@ -58,7 +50,7 @@ device pci 1c.3 on end # PCIe Port #4 - WiFi device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 on end # USB2 EHCI + device pci 1d.0 off end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip ec/purism/librem diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb deleted file mode 100644 index 98b5163..0000000 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DDI1 Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - - # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port 0 tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal - end -end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb new file mode 100644 index 0000000..d3d0ae7 --- /dev/null +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -0,0 +1,14 @@ +chip soc/intel/broadwell + + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device domain 0 on + device pci 1c.2 on end # PCIe Port #3 - LAN + end +end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb new file mode 100644 index 0000000..c0c8d03 --- /dev/null +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -0,0 +1,14 @@ +chip soc/intel/broadwell + + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device domain 0 on + device pci 1d.0 on end # USB2 EHCI + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/40915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07fb5a09e578bf299081b26e010317385a6c5f7f Gerrit-Change-Number: 40915 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_bdw: cleanup 15v2 devicetree
by Matt DeVillier (Code Review) 02 May '20

02 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40914 ) Change subject: mb/purism/librem_bdw: cleanup 15v2 devicetree ...................................................................... mb/purism/librem_bdw: cleanup 15v2 devicetree The Librem 15v2 only uses SATA ports 0/1, so the DTLE settings for ports 2/3 have no consequence. Drop them to make overridetree conversion cleaner. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I4145feecb389be90f317249426e58752c03aef76 --- M src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40914/1 diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb index 32c3ed1..cbd59be 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb @@ -28,8 +28,6 @@ # Port tuning for link stability register "sata_port0_gen3_dtle" = "7" register "sata_port1_gen3_dtle" = "9" - register "sata_port2_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "7" device cpu_cluster 0 on device lapic 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/40914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4145feecb389be90f317249426e58752c03aef76 Gerrit-Change-Number: 40914 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/google/kahlee: Add hook for early wlan rst gpio init
by Kevin Chiu (Code Review) 02 May '20

02 May '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40944 to review the following change. Change subject: mainboard/google/kahlee: Add hook for early wlan rst gpio init ...................................................................... mainboard/google/kahlee: Add hook for early wlan rst gpio init Base on the grunt board schematic, gpio70 is an alternative way for wlan rst. Add hook for variants to override default state. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: Ic3f1c016357dd5090e6adedf96e7593abff29a0c --- M src/mainboard/google/kahlee/bootblock/bootblock.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h 3 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/40944/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 613b35b..f3016b7 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -17,6 +17,9 @@ /* Enable the EC as soon as we have visibility */ mainboard_ec_init(); + gpios = variant_wlan_rst_early_gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); + gpios = variant_early_gpio_table(&num_gpios); program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 4fb60b1..fe0744a 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -42,9 +42,6 @@ /* GPIO_40 - EMMC_BRIDGE_RST */ PAD_GPO(GPIO_40, LOW), - /* GPIO_70 - WLAN_PE_RST_L */ - PAD_GPO(GPIO_70, HIGH), - /* GPIO_74 - LPC_CLK0_EC_R */ PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN), @@ -77,6 +74,11 @@ PAD_GPI(GPIO_142, PULL_NONE), }; +static const struct soc_amd_gpio gpio_wlan_rst_early_reset[] = { + /* GPIO_70 - WLAN_PE_RST_L */ + PAD_GPO(GPIO_70, HIGH), +}; + static const struct soc_amd_gpio gpio_set_stage_rom[] = { /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */ PAD_GPO(GPIO_133, HIGH), @@ -248,6 +250,13 @@ } const __weak +struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_wlan_rst_early_reset); + return gpio_wlan_rst_early_reset; +} + +const __weak struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_rom); diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 02d413f..8b78992 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,7 @@ int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size); const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size); const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/40944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f1c016357dd5090e6adedf96e7593abff29a0c Gerrit-Change-Number: 40944 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/seabios: Add Hardware IRQ Kconfig
by Matt DeVillier (Code Review) 02 May '20

02 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39869 ) Change subject: payloads/seabios: Add Hardware IRQ Kconfig ...................................................................... payloads/seabios: Add Hardware IRQ Kconfig Certain Intel SoC platforms require SeaBIOS' HARDWARE_IRQ option to be deselected in order for the platform to boot. Add a Kconfig to properly select the HARDWARE_IRQ enablement based on platform, and write to SeaBIOS' .config file in cases where it needs to be disabled. Test: build/boot google/clapper (Baytrail) and google/cyan (Braswell), verify boards boot vs hanging at boot menu prompt. Change-Id: I23e9b30d2d1042c86bd10f134d6fe361edaf8cb2 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/SeaBIOS/Kconfig M payloads/external/SeaBIOS/Makefile 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39869/1 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index e816775..abe8815 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -51,6 +51,17 @@ variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_HARDWARE_IRQ + prompt "Hardware Interrupts" + default n if SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || SOC_INTEL_APOLLOLAKE + default y + bool + help + Program and support hardware interrupts using the i8259 + programmable interrupt controller (PIC). This option should + be enabled for all platforms except for those which require + it to be disabled (eg, Baytrail/Braswell and successors) + config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" default y if !VENDOR_EMULATION diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 0086775..cd646d9 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -72,6 +72,9 @@ ifneq ($(CONFIG_SEABIOS_DEBUG_LEVEL),-1) echo "CONFIG_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL)" >> seabios/.config endif +ifneq ($(CONFIG_SEABIOS_HARDWARE_IRQ),y) + echo "# CONFIG_HARDWARE_IRQ is not set" >> seabios/.config +endif # This shows how to force a previously set .config option *off* # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ -- To view, visit https://review.coreboot.org/c/coreboot/+/39869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23e9b30d2d1042c86bd10f134d6fe361edaf8cb2 Gerrit-Change-Number: 39869 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/stm: Place resource list right below MSEG
by Name of user not set (Code Review) 02 May '20

02 May '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40437 ) Change subject: intel/stm: Place resource list right below MSEG ...................................................................... intel/stm: Place resource list right below MSEG Suggested by Nico Huber in CL 38765. This placement makes the address calculation simpler and makes its location indepedent of the number of CPUs. Change-Id: I9ee2747474df02b0306530048bdec75e95413b5d Signed-off-by: Eugene D Myers <cedarhouse(a)comcast.net> --- M src/cpu/x86/smm/smm_module_loader.c M src/security/intel/stm/StmPlatformSmm.c 2 files changed, 8 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/40437/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 7c23ef8..c50e97d 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -308,13 +308,13 @@ /* The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size - * | stacks | - * +-----------------+ <- smram + size - total_stack_size - * | fxsave area | - * +-----------------+ <- smram + size - total_stack_size - fxsave_size * | BIOS resource | * | list (STM) | - * +-----------------+ <- .. - CONFIG_BIOS_RESOURCE_LIST_SIZE + * +-----------------+ <- smram + size - CONFIG_BIOS_RESOURCE_LIST_SIZE + * | stacks | + * +-----------------+ <- .. - total_stack_size + * | fxsave area | + * +-----------------+ <- .. - total_stack_size - fxsave_size * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE * | handler | @@ -355,11 +355,10 @@ /* Stacks start at the top of the region. */ base = smram; + base += size; if (CONFIG(STM)) - base += size - CONFIG_MSEG_SIZE; // take out the mseg - else - base += size; + base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; params->stack_top = base; @@ -389,9 +388,6 @@ /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - /* Account for the BIOS resource list */ - if (CONFIG(STM)) - total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; if (total_size > size) return -1; diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 45db0e0..248ccc0 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -177,12 +177,7 @@ // need to create the BIOS resource list once // first calculate the location in SMRAM - addr_calc = (mseg - (CONFIG_SMM_MODULE_STACK_SIZE * num_cpus)); - - if (CONFIG(SSE)) - addr_calc -= FXSAVE_SIZE * num_cpus; - - addr_calc -= CONFIG_BIOS_RESOURCE_LIST_SIZE; + addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); -- To view, visit https://review.coreboot.org/c/coreboot/+/40437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee2747474df02b0306530048bdec75e95413b5d Gerrit-Change-Number: 40437 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/reef: add default non-ChromeOS FMAP
by Matt DeVillier (Code Review) 02 May '20

02 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40907 ) Change subject: mb/google/reef: add default non-ChromeOS FMAP ...................................................................... mb/google/reef: add default non-ChromeOS FMAP Add a FMAP which supports SMMSTORE and non-ChromeOS payloads, since Apollo Lake-based devices like Reef cannot use an automatically-generated FMAP due to strict layout requirements. Change-Id: If570f92f4f81c0e29777c87756fc5e45af549064 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/reef/Kconfig A src/mainboard/google/reef/default.fmd 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/40907/1 diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5d782b1..6b970b2 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -100,4 +100,7 @@ default 0xe00 if CHROMEOS default 0xc00 +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS + endif # BOARD_GOOGLE_REEF diff --git a/src/mainboard/google/reef/default.fmd b/src/mainboard/google/reef/default.fmd new file mode 100644 index 0000000..6e6b64f --- /dev/null +++ b/src/mainboard/google/reef/default.fmd @@ -0,0 +1,24 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xf6f000 { + IFWI@0x0 0x1ff000 + # SMMSTORE requires 64k alignment + SMMSTORE@0xa5e000 0x40000 + RW_MRC_CACHE 0x10000 + FMAP 0x300 + COREBOOT(CBFS) + BIOS_UNUSABLE 0x4f000 + } + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If570f92f4f81c0e29777c87756fc5e45af549064 Gerrit-Change-Number: 40907 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11: drop DeepSx config from devicetree
by Patrick Georgi (Code Review) 02 May '20

02 May '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40858 ) Change subject: mb/supermicro/x11: drop DeepSx config from devicetree ...................................................................... mb/supermicro/x11: drop DeepSx config from devicetree Drop the DeepSx config as it's unsupported and disabled for the boards. Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40858 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 998f3dd..0dd37ee 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -2,7 +2,6 @@ register "deep_s5_enable_ac" = "0" register "deep_s5_enable_dc" = "0" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/40858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Gerrit-Change-Number: 40858 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i440bx: Clean up register_values table
by Keith Hui (Code Review) 02 May '20

02 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40391 ) Change subject: nb/intel/i440bx: Clean up register_values table ...................................................................... nb/intel/i440bx: Clean up register_values table The table of initial i440BX register values has a bitmask that allows preserving certain bits as they are programmed. This feature has been unused since day one and probably will never be used. Drop it to save some bytes. Also dropping DRB, RPS, PGPOL registers from the table as they will be programmed during RAM init. TEST=Boot tested on asus/p2b-ls, i440bx config did not change Change-Id: I020f616455bb671fe284993a488beb6386a03d0d Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 20 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40391/1 diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index e2db5e7..cdfc4f6 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -60,7 +60,7 @@ 1, 5, 5, 2, 3, 4 }; -/* Table format: register, bitmask, value. */ +/* Table format: register, value. */ static const u8 register_values[] = { /* NBXCFG - NBX Configuration Register * 0x50 - 0x53 @@ -122,11 +122,11 @@ * 0 = A7# is sampled asserted (i.e., 0) * [01:00] Reserved */ - NBXCFG + 0, 0x00, 0x0c, + NBXCFG + 0, 0x0c, // TODO: Bit 15 should be 0 for multiprocessor boards - NBXCFG + 1, 0x00, 0x80, - NBXCFG + 2, 0x00, 0x00, - NBXCFG + 3, 0x00, 0xff, + NBXCFG + 1, 0x80, + NBXCFG + 2, 0x00, + NBXCFG + 3, 0xff, /* DRAMC - DRAM Control Register * 0x57 @@ -156,7 +156,7 @@ * 111 = Reserved */ /* Choose SDRAM (not registered), and disable refresh for now. */ - DRAMC, 0x00, 0x08, + DRAMC, 0x08, /* * PAM[6:0] - Programmable Attribute Map Registers @@ -190,13 +190,13 @@ * registers are not set here appropriately, the RAM in that region * will not be accessible, thus a RAM check of it will also fail. */ - PAM0, 0x00, 0x30, - PAM1, 0x00, 0x33, - PAM2, 0x00, 0x33, - PAM3, 0x00, 0x33, - PAM4, 0x00, 0x33, - PAM5, 0x00, 0x33, - PAM6, 0x00, 0x33, + PAM0, 0x30, + PAM1, 0x33, + PAM2, 0x33, + PAM3, 0x33, + PAM4, 0x33, + PAM5, 0x33, + PAM6, 0x33, /* DRB[0:7] - DRAM Row Boundary Registers * 0x60 - 0x67 @@ -214,14 +214,6 @@ * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) */ /* DRBs will be set later. */ - DRB0, 0x00, 0x00, - DRB1, 0x00, 0x00, - DRB2, 0x00, 0x00, - DRB3, 0x00, 0x00, - DRB4, 0x00, 0x00, - DRB5, 0x00, 0x00, - DRB6, 0x00, 0x00, - DRB7, 0x00, 0x00, /* FDHC - Fixed DRAM Hole Control Register * 0x68 @@ -236,7 +228,7 @@ * [5:0] Reserved */ /* No memory holes. */ - FDHC, 0x00, 0x00, + FDHC, 0x00, /* RPS - SDRAM Row Page Size Register * 0x74 - 0x75 @@ -261,8 +253,6 @@ * [15:14] DRB[7], row 7 */ /* Power on defaults to 2KB. Will be set later. */ - // RPS + 0, 0x00, 0x00, - // RPS + 1, 0x00, 0x00, /* SDRAMC - SDRAM Control Register * 0x76 - 0x77 @@ -298,9 +288,9 @@ * 1 = 2 clocks of RAS# precharge */ #if CONFIG(SDRAMPWR_4DIMM) - SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ + SDRAMC + 0, 0x10, /* The board has 4 DIMM slots. */ #else - SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */ + SDRAMC + 0, 0x00, /* The board has 3 DIMM slots. */ #endif /* PGPOL - Paging Policy Register @@ -325,8 +315,6 @@ * 0111 = 32 clocks * 1xxx = Infinite (pages are not closed for idle condition) */ - PGPOL + 0, 0x00, 0x00, - PGPOL + 1, 0x00, 0xff, /* PMCR - Power Management Control Register * 0x7a @@ -355,10 +343,10 @@ * 1 = Enable * 0 = Disable */ - /* PMCR will be set later. */ + /* PGPOL and PMCR will be set later. */ /* Enable SCRR.SRRAEN and let BX choose the SRR. */ - SCRR + 1, 0x00, 0x10, + SCRR + 1, 0x10, }; /*----------------------------------------------------------------------------- @@ -666,7 +654,6 @@ static void sdram_set_registers(void) { int i, max; - uint8_t reg; PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); @@ -674,11 +661,8 @@ max = ARRAY_SIZE(register_values); /* Set registers as specified in the register_values[] array. */ - for (i = 0; i < max; i += 3) { - reg = pci_read_config8(NB, register_values[i]); - reg &= register_values[i + 1]; - reg |= register_values[i + 2] & ~(register_values[i + 1]); - pci_write_config8(NB, register_values[i], reg); + for (i = 0; i < max; i += 2) { + pci_write_config8(NB, register_values[i], register_values[i + 1]); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I020f616455bb671fe284993a488beb6386a03d0d Gerrit-Change-Number: 40391 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Nico Huber (Code Review) 02 May '20

02 May '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chi… File src/soc/intel/skylake/chip.h: https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chi… PS14, Line 286: PcieRpAspm > I see the issue. In your opinion, should they be renamed? Sure, that's what I meant. > > Regarding CamelCase, there doesn't seem to be an aversion to following FSP identifiers when it comes to UPDs. Yes and it often turned out to be a bad idea. Sometimes the UPDs collide with some of coreboot's code or concepts. But the people adding their copies to `chip.h` don't know coreboot, and don't care if they create a shim around FSP instead of a proper coreboot. In this case, though, I really just wanted to point out that you use the same name with different values. Actually, I don't expect anybody to fall into this trap. But everytime somebody does some- thing like this, it's another bad example in the tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 14 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 May 2020 13:42:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Change power_res_dev_states[] to be non-static
by Furquan Shaikh (Code Review) 02 May '20

02 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40935 ) Change subject: arch/x86: Change power_res_dev_states[] to be non-static ...................................................................... arch/x86: Change power_res_dev_states[] to be non-static Jenkins complains that power_res_dev_states[] should be a const pointer since it is marked static. However, this doesn't really need to be static. Hence, the change drops static keyword. BUG=b:155428745 Change-Id: Ice2fff6ab3bcd72a059bc905b7462a681f2e6aaf Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/arch/x86/acpi_device.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40935/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index b4016ef..653e124 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -527,7 +527,7 @@ /* PowerResource() with Enable and/or Reset control */ void acpi_device_add_power_res(const struct acpi_power_res_params *params) { - static const char *power_res_dev_states[] = { "_PR0", "_PR3" }; + const char *power_res_dev_states[] = { "_PR0", "_PR3" }; unsigned int reset_gpio = params->reset_gpio ? params->reset_gpio->pins[0] : 0; unsigned int enable_gpio = params->enable_gpio ? params->enable_gpio->pins[0] : 0; unsigned int stop_gpio = params->stop_gpio ? params->stop_gpio->pins[0] : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/40935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2fff6ab3bcd72a059bc905b7462a681f2e6aaf Gerrit-Change-Number: 40935 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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