May 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix checkout hint
by Werner Zeh (Code Review) May 4, 2020

May 4, 2020

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40954 ) Change subject: payloads/external/GRUB2: Makefile: fix checkout hint ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1277c3788a141b25cd9f22ec0476ee56b64aea4d Gerrit-Change-Number: 40954 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 06:02:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: WIP, DONOTMERGE: Add inteltool support to dump GPIOs
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29459 ) Change subject: WIP, DONOTMERGE: Add inteltool support to dump GPIOs ...................................................................... Abandoned Does no longer apply cleanly -- To view, visit https://review.coreboot.org/c/coreboot/+/29459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b0d49a175e656ef88d66c559239cac17e51b880 Gerrit-Change-Number: 29459 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/asus/p8h61-m_pro: Fix integrated network
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34124 ) Change subject: mb/asus/p8h61-m_pro: Fix integrated network ...................................................................... mb/asus/p8h61-m_pro: Fix integrated network Looks like this select makes the internal NIC not work. Not sure why, though. Change-Id: I92e603c86d9bfe9be9e53918e8f1477a9a1dcf99 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p8h61-m_pro/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34124/1 diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index e8a6f64..d3d1c67 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -31,7 +31,6 @@ select HAVE_CMOS_DEFAULT select DRIVERS_ASMEDIA_ASPM_BLACKLIST select MAINBOARD_HAS_LPC_TPM - select REALTEK_8168_RESET select RT8168_SET_LED_MODE select INTEL_GMA_HAVE_VBT -- To view, visit https://review.coreboot.org/c/coreboot/+/34124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92e603c86d9bfe9be9e53918e8f1477a9a1dcf99 Gerrit-Change-Number: 34124 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] Tag boards with a new MAINBOARD_HAS_SUPERIO_UART symbol
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37726 ) Change subject: [RFC] Tag boards with a new MAINBOARD_HAS_SUPERIO_UART symbol ...................................................................... Abandoned Literally nobody seems to care -- To view, visit https://review.coreboot.org/c/coreboot/+/37726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c93ed77afc7fe226ddc19d6745d75876031b170 Gerrit-Change-Number: 37726 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/intel/glkrvp: Simplify FMAP file
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38664 ) Change subject: mb/intel/glkrvp: Simplify FMAP file ...................................................................... mb/intel/glkrvp: Simplify FMAP file Tested with BUILD_TIMELESS, no changes. Change-Id: Iac1d1e16be5db7bfbadc5929057cc2d93b5cd876 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/glkrvp/chromeos.fmd 1 file changed, 31 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/38664/1 diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 8f3c63a..cfde802 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -1,41 +1,41 @@ FLASH 16M { - WP_RO@0x0 0x400000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD(PRESERVE)@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x1ab000 - GBB@0x1ac000 0x40000 - RO_UNUSED@0x1ec000 0x10000 + WP_RO 0x400000 { + SI_DESC 0x1000 + IFWI 0x1ff000 + RO_VPD(PRESERVE) 0x4000 + RO_SECTION 0x1fc000 { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + COREBOOT(CBFS) + GBB 0x40000 + RO_UNUSED 0x10000 } } - MISC_RW@0x400000 0x4a000 { - UNIFIED_MRC_CACHE@0x0 0x31000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - RW_VAR_MRC_CACHE@0x30000 0x1000 + MISC_RW 0x4a000 { + UNIFIED_MRC_CACHE 0x31000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x20000 + RW_VAR_MRC_CACHE 0x1000 } - RW_ELOG(PRESERVE)@0x31000 0x4000 - RW_SHARED@0x35000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE) 0x4000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 } - RW_VPD(PRESERVE)@0x39000 0x2000 - FPF_STATUS@0x3B000 0x1000 - TMP_UNUSED_HOLE@0x3C000 0xE000 + RW_VPD(PRESERVE) 0x2000 + FPF_STATUS 0x1000 + TMP_UNUSED_HOLE 0xe000 } - RW_SECTION_A@0x44a000 0x477800 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + RW_SECTION_A 0x477800 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + RW_SECTION_B 0x477800 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 } RW_NVRAM(PRESERVE)@0xd39000 0x6000 SMMSTORE(PRESERVE)@0xd40000 0x40000 -- To view, visit https://review.coreboot.org/c/coreboot/+/38664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac1d1e16be5db7bfbadc5929057cc2d93b5cd876 Gerrit-Change-Number: 38664 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x/pcie.c: Replace ASSERT with check
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40018 ) Change subject: sb/intel/bd82x6x/pcie.c: Replace ASSERT with check ...................................................................... sb/intel/bd82x6x/pcie.c: Replace ASSERT with check The ASSERT statement includes a reference to the line number, which breaks timeless builds when the line it is on changes. To ease the verification of subsequent changes, use a regular check instead. Change-Id: I605793e2ca9a956c18c3abc20192b158a7959210 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/40018/1 diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 84309a4..957d4e5 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -21,7 +21,6 @@ #include <device/pciexp.h> #include <device/pci_ids.h> #include <southbridge/intel/common/pciehp.h> -#include <assert.h> #include "chip.h" #include "pch.h" @@ -289,9 +288,7 @@ static const char *pch_pcie_acpi_name(const struct device *dev) { - ASSERT(dev); - - if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) { + if (dev && PCI_SLOT(dev->path.pci.devfn) == 0x1c) { static const char *names[] = { "RP01", "RP02", "RP03", -- To view, visit https://review.coreboot.org/c/coreboot/+/40018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I605793e2ca9a956c18c3abc20192b158a7959210 Gerrit-Change-Number: 40018 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Tidy up code and comments
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40020 ) Change subject: sb/intel/bd82x6x: Tidy up code and comments ...................................................................... sb/intel/bd82x6x: Tidy up code and comments - Reformat and reflow many lines of code - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Add some macros to factor out clutter With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: Ie38c4ed7c2956bf96cffd84276ab48d4b9eab5db Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c 25 files changed, 491 insertions(+), 560 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40020/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 316fafc..d904d33 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -31,9 +31,7 @@ reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -95,8 +93,8 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) @@ -116,9 +114,8 @@ } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the codec is non-operative. */ static int wait_for_valid(u8 *base) @@ -135,8 +132,7 @@ int timeout = 1000; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index ef2ee0e..e8d8520 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -22,7 +22,7 @@ static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ - RCBA32(GCS) &= (~0x04); + RCBA32(GCS) &= ~(1 << 2); } static void set_spi_speed(void) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 94715de..a83d1b3 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -88,4 +88,4 @@ struct intel_swseq_spi_config spi; }; -#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 184f72a..91856a5 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -137,7 +137,7 @@ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); - printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); + printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", (me_fws2 & 0x1)); printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1); printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3); printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4); @@ -208,7 +208,7 @@ me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); - printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); + printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", (me_fws2 & 0x1)); printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1); printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3); printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 530f11a..05f93db 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -19,15 +19,13 @@ #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) -static void -wait_iobp(void) +static void wait_iobp(void) { while (RCBA8(IOBPS) & 1) ; // implement timeout? } -static u32 -read_iobp(u32 address) +static u32 read_iobp(u32 address) { u32 ret; @@ -40,12 +38,13 @@ return ret; } -static void -write_iobp(u32 address, u32 val) +static void write_iobp(u32 address, u32 val) { - /* this function was probably pch_iobp_update with the andvalue - * being 0. So either the IOBP read can be removed or this function - * and the pch_iobp_update function in ramstage could be merged */ + /* + * This function was probably pch_iobp_update with the andvalue being 0. + * So, either the IOBP read can be removed or this function and the + * pch_iobp_update function in ramstage could be merged + */ read_iobp(address); RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); @@ -88,15 +87,17 @@ * serialice traces. */ - /* Virtual Channel 0 Resource Control Register. + /* + * Virtual Channel 0 Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC0 and TC3 and TC4 to VC0. */ - RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + /* FIXME: Read back? */ - /* Virtual Channel 1 Resource Control Register. + /* + * Virtual Channel 1 Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC1 and TC5 to VC1. @@ -105,7 +106,8 @@ /* Read back register */ RCBA32(V1CTL); - /* Virtual Channel private Resource Control Register. + /* + * Virtual Channel private Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC2 and TC6 to VCp. @@ -114,12 +116,14 @@ /* Read back register */ RCBA32(CIR31); - /* Virtual Channel ME Resource Control Register. + /* + * Virtual Channel ME Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC7 to VCm. */ RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); + /* FIXME: Read back? */ /* Lock Virtual Channel Resource control register. */ RCBA32(CIR0) |= TCLOCKDN; @@ -137,11 +141,9 @@ ; } -void -early_pch_init_native (void) +void early_pch_init_native (void) { - pci_write_config8 (SOUTHBRIDGE, 0xa6, - pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); + pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2); RCBA32(CIR1) = 0x00109000; RCBA32(REC); // !!! = 0x00000000 @@ -278,9 +280,9 @@ * - 0x3f8-0x3ff COMA */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF1_LPC_EN | COMA_LPC_EN | LPT_LPC_EN | KBC_LPC_EN | + CNF2_LPC_EN | COMB_LPC_EN | FDD_LPC_EN | MC_LPC_EN); const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 915a935..9785e2c 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -5,21 +5,18 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include "pch.h" -void -southbridge_configure_default_intmap(void) +void southbridge_configure_default_intmap(void) { /* - * For the PCH internal PCI functions, provide a reasonable - * default IRQ mapping that utilizes only PIRQ A to D. Higher - * PIRQs are sometimes used for other on-board chips that - * require an edge triggered interrupt which is not shareable. + * For the PCH internal PCI functions, provide a reasonable default IRQ mapping that + * utilizes only PIRQ A to D. Higher PIRQs are sometimes used for other on-board chips + * that require an edge triggered interrupt which is not shareable. */ /* - * We use a linear mapping for the pin numbers. They are not - * physical pins, and thus, have no relation between the dif- - * ferent devices. Only rule we must obey is that a single- - * function device has to use pin A. + * We use a linear mapping for the pin numbers. They are not physical pins, and thus, + * have no relation between the different devices. Only rule we must obey is that a + * single-function device has to use pin A. */ RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); @@ -35,19 +32,18 @@ RCBA32(D20IP) = (INTA << D20IP_XHCIIP); /* - * For the PIRQ allocation the following was taken into - * account: - * o Interrupts of the PCIe root ports are only about - * events at the ports, not downstream devices. So we - * don't expect many interrupts there and ignore them. - * o We don't expect to talk constantly to the ME either - * so ignore that, too. Same for SMBus and the thermal - * device. - * o Second SATA interface is only used in non-AHCI mode - * so unlikely to coexist with modern interfaces (e.g. - * xHCI). - * o An OS that knows USB3 will likely also know how to - * use MSI. + * For the PIRQ allocation the following was taken into account: + * + * o Interrupts of the PCIe root ports are only about events at the ports, not + * downstream devices. So we don't expect many interrupts there and ignore them. + * + * o We don't expect to talk constantly to the ME either so ignore that, too. Same + * for SMBus and the thermal device. + * + * o Second SATA interface is only used in non-AHCI mode so unlikely to coexist with + * modern interfaces (e.g. xHCI). + * + * o An OS that knows USB3 will likely also know how to use MSI. * * The functions that might matter first: * @@ -83,8 +79,7 @@ (void) RCBA16(OIC); } -void -southbridge_rcba_config(void) +void southbridge_rcba_config(void) { RCBA32(FD) = PCH_DISABLE_ALWAYS; } diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index f3151af..c19a9d9 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <device/smbus_host.h> #include "pch.h" @@ -14,15 +15,14 @@ int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 8de31e6..ebf3e80 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -1,69 +1,68 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <device/mmio.h> -#include <device/pci_ops.h> -#include "pch.h" -#include "cpu/intel/model_206ax/model_206ax.h" #include <cpu/x86/msr.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include "cpu/intel/model_206ax/model_206ax.h" +#include "pch.h" -static void write8p(uintptr_t addr, uint32_t val) +static void write8p(uintptr_t addr, const uint32_t val) { write8((u8 *)addr, val); } -static void write16p(uintptr_t addr, uint32_t val) +static void write16p(uintptr_t addr, const uint32_t val) { write16((u16 *)addr, val); } -static uint16_t read16p (uintptr_t addr) +static uint16_t read16p(const uintptr_t addr) { return read16((u16 *)addr); } -/* Early thermal init, must be done prior to giving ME its memory - which is done at the end of raminit. */ +/* We use this temporary BAR to program some registers in the Thermal device's MMIO window */ +#define THERMAL_BASE (0x40000000) + +/* Early thermal init, must be done before giving ME its memory, which is done after raminit */ void early_thermal_init(void) { - pci_devfn_t dev; + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 6); msr_t msr; - dev = PCI_DEV(0x0, 0x1f, 0x6); + /* Program address for temporary BAR */ + pci_write_config32(dev, 0x40, THERMAL_BASE); /* TBARB */ + pci_write_config32(dev, 0x44, 0); /* TBARBH */ - /* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); - pci_write_config32(dev, 0x44, 0x0); + /* Activate temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); - /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) | 5); + write16p(THERMAL_BASE + 0x04, 0x3a2b); /* TSTTP */ + write8p(THERMAL_BASE + 0x0c, 0xff); /* TSES */ + write8p(THERMAL_BASE + 0x0d, 0x00); /* TSGPEN */ + write8p(THERMAL_BASE + 0x0e, 0x40); /* TSPC */ + write8p(THERMAL_BASE + 0x82, 0x00); /* TSPIEN */ + write8p(THERMAL_BASE + 0x01, 0xba); /* TSE */ - write16p (0x40000004, 0x3a2b); - write8p (0x4000000c, 0xff); - write8p (0x4000000d, 0x00); - write8p (0x4000000e, 0x40); - write8p (0x40000082, 0x00); - write8p (0x40000001, 0xba); - - /* Perform init. */ - /* Configure TJmax. */ + /* Perform init */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); - /* Northbridge temperature slope and offset. */ - write16p(0x40000016, 0x808c); + /* Configure TJmax */ + write16p(THERMAL_BASE + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* CTA */ - write16p (0x40000014, 0xde87); + /* Northbridge temperature slope and offset */ + write16p(THERMAL_BASE + 0x16, 0x808c); /* MGTA */ - /* Enable thermal data reporting, processor, PCH and northbridge. */ - write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); + write16p(THERMAL_BASE + 0x14, 0xde87); /* PTA */ - /* Disable temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) & ~1); + /* Enable thermal data reporting, processor, PCH and northbridge in TRC */ + write16p(THERMAL_BASE + 0x1a, (read16p(THERMAL_BASE + 0x1a) & ~0xf) | 0x10f0); + + /* Disable temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_write_config32(dev, 0x40, 0); - write32 (DEFAULT_RCBA + 0x38b0, - (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); + write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); } diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 31aad17..4d8b66a 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -17,43 +17,54 @@ /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, - 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, - 0x20000353 }; + const u32 currents[] = { + 0x20000153, 0x20000f57, 0x2000055b, + 0x20000f51, 0x2000094a, 0x2000035f, + 0x20000f53, 0x20000357, 0x20000353, + }; int i; - /* Unlock registers. */ + /* Unlock registers */ write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; + for (i = 0; i < 10; i++) RCBA32(0x3538 + 4 * i) = 0; for (i = 0; i < 8; i++) RCBA32(0x3560 + 4 * i) = rcba_dump[i]; + for (i = 0; i < 8; i++) RCBA32(0x3580 + 4 * i) = 0; + reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); + RCBA32(USBPDO) = reg32; + reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + RCBA32(USBOCM1) = reg32; + reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + RCBA32(USBOCM2) = reg32; + for (i = 0; i < 22; i++) RCBA32(0x35a8 + 4 * i) = 0; - pci_write_config32(PCH_XHCI_DEV, 0xe4, 0x00000000); + pci_write_config32(PCH_XHCI_DEV, 0xe4, 0); - /* Relock registers. */ + /* Relock registers */ write_pmbase16(UPRWC, 0); } diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index 719f94b..e8431ee 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -9,28 +9,23 @@ #define PCH_EHCI2_TEMP_BAR0 0xe8000400 /* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. - * - * The BAR will be re-assigned during device - * enumeration so these are only temporary. + * Setup USB controller MMIO BAR to prevent the reference code from resetting the controller. + * The BAR will be re-assigned during device enumeration so these are only temporary. */ void enable_usb_bar(void) { - pci_devfn_t usb0 = PCH_EHCI1_DEV; - pci_devfn_t usb1 = PCH_EHCI2_DEV; + const pci_devfn_t usb0 = PCH_EHCI1_DEV; + const pci_devfn_t usb1 = PCH_EHCI2_DEV; u32 cmd; /* USB Controller 1 */ - pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); + pci_write_config32(usb0, PCI_BASE_ADDRESS_0, PCH_EHCI1_TEMP_BAR0); cmd = pci_read_config32(usb0, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb0, PCI_COMMAND, cmd); /* USB Controller 2 */ - pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI2_TEMP_BAR0); + pci_write_config32(usb1, PCI_BASE_ADDRESS_0, PCH_EHCI2_TEMP_BAR0); cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd); diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index dc5da79..4e5edc2 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -13,7 +13,7 @@ void pch_log_state(void) { - u16 pm1_sts, gen_pmcon_3, tco2_sts; + u16 tco2_sts, pm1_sts, gen_pmcon_3; u32 gpe0_sts, gpe0_en; u8 gen_pmcon_2; int i; @@ -21,11 +21,11 @@ if (!lpc) return; - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); + gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); - gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); + gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); /* PWR_FLR Power Failure */ @@ -62,8 +62,7 @@ /* ACPI Wake */ if (pm1_sts & (1 << 15)) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_is_wakeup_s3() ? 3 : 5); /* * Wake sources diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 3b6c030..803acf8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -41,15 +41,14 @@ u32 reg32; /* Assign unique bus/dev/fn for I/O APIC */ - pci_write_config16(dev, LPC_IBDF, - PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); + pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); set_ioapic_id(VIO_APIC_VADDR, 0x02); - /* affirm full set of redirection table entries ("write once") */ + /* Affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); io_apic_write(VIO_APIC_VADDR, 0x01, reg32); @@ -63,11 +62,10 @@ static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + #if !CONFIG(SERIRQ_CONTINUOUS_MODE) - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif } @@ -88,6 +86,7 @@ * 0x0D - 1101 = Reserved * 0x0E - 1110 = IRQ14 * 0x0F - 1111 = IRQ15 + * * PIRQ[n]_ROUT[7] - PIRQ Routing Control * 0x80 - The PIRQ is not routed. */ @@ -95,12 +94,12 @@ static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - /* Interrupt 11 is not used by legacy devices and so can always be used for - PCI interrupts. Full legacy IRQ routing is complicated and hard to - get right. Fortunately all modern OS use MSI and so it's not that big of - an issue anyway. Still we have to provide a reasonable default. Using - interrupt 11 for it everywhere is a working default. ACPI-aware OS can - move it to any interrupt and others will just leave them at default. + /* + * Interrupt 11 is not used by legacy devices, so it can always be used for PCI devices. + * Full legacy IRQ routing is complicated and hard to get right. Fortunately, all modern + * OSes use MSI, so it's not that big of an issue anyway. Even then, we have to provide + * a reasonable default. Using interrupt 11 everywhere is a working default, because + * ACPI-aware OSes can move it to any interrupt and others will leave them at default. */ const u8 pirq_routing = 11; @@ -135,19 +134,17 @@ config_t *config = dev->chip_info; u32 reg32 = 0; - /* An array would be much nicer here, or some - * other method of doing this. - */ - reg32 |= (config->gpi0_routing & 0x03) << 0; - reg32 |= (config->gpi1_routing & 0x03) << 2; - reg32 |= (config->gpi2_routing & 0x03) << 4; - reg32 |= (config->gpi3_routing & 0x03) << 6; - reg32 |= (config->gpi4_routing & 0x03) << 8; - reg32 |= (config->gpi5_routing & 0x03) << 10; - reg32 |= (config->gpi6_routing & 0x03) << 12; - reg32 |= (config->gpi7_routing & 0x03) << 14; - reg32 |= (config->gpi8_routing & 0x03) << 16; - reg32 |= (config->gpi9_routing & 0x03) << 18; + /* An array would be much nicer here, or some other method of doing this */ + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; reg32 |= (config->gpi10_routing & 0x03) << 20; reg32 |= (config->gpi11_routing & 0x03) << 22; reg32 |= (config->gpi12_routing & 0x03) << 24; @@ -170,11 +167,12 @@ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; - /* Which state do we want to goto after g3 (power restored)? + /* + * Which state do we want to go to after exiting G3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * - * If the option is not existent (Laptops), use Kconfig setting. + * If the option is not set, use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail"); @@ -198,12 +196,12 @@ } reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); @@ -232,15 +230,14 @@ reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); // SMI# rate 1 minute reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME + #if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - reg16 |= (3 << 0); // Periodic SMI every 8s + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs. */ + reg16 |= (3 << 0); // Periodic SMI every 8s #endif pci_write_config16(dev, GEN_PMCON_1, reg16); - // Set the board's GPI routing. + /* Set the board's GPI routing */ pch_gpi_routing(dev); pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -249,14 +246,14 @@ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN + reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04); /* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(PRSTS); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); + reg32 |= (1 << 4) | (1 << 5) | (1 << 0); RCBA32(PRSTS) = reg32; reg32 = RCBA32(0x3f02); @@ -264,7 +261,7 @@ RCBA32(0x3f02) = reg32; } -/* CougarPoint PCH Power Management init */ +/* Cougar Point PCH Power Management init */ static void cpt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "CougarPoint PM init\n"); @@ -306,23 +303,23 @@ RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } -/* PantherPoint PCH Power Management init */ +/* Panther Point PCH Power Management init */ static void ppt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "PantherPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); RCBA32_AND_OR(CIR30, ~0UL, (1 << 0)); RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); - RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR3, ~0UL, (1 << 13) | (1 << 14)); RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); RCBA32(DMC) = 0xc03b8400; - RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR6, ~0UL, (1 << 5) | (1 << 18)); + RCBA32_AND_OR(CIR9, ~0UL, (1 << 15) | (1 << 1)); RCBA32_AND_OR(CIR7, ~0x1f, 0xf); RCBA32(PM_CFG) = 0x054f0000; RCBA32(CIR8) = 0x04000000; RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); - RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)|(1 << 0)); + RCBA32_AND_OR(CIR11, ~0UL, (1 << 1) | (1 << 0)); RCBA32(CIR12) = 0x0001c000; RCBA32(CIR14) = 0x00061100; RCBA32(CIR15) = 0x7f8fdfff; @@ -361,7 +358,7 @@ /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable + reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; } @@ -377,10 +374,10 @@ reg16 |= (1 << 2) | (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xeb007f07, ~0UL, (1 << 31)); + pch_iobp_update(0xeb004000, ~0UL, (1 << 7)); + pch_iobp_update(0xec007f07, ~0UL, (1 << 31)); + pch_iobp_update(0xec004000, ~0UL, (1 << 7)); reg32 = RCBA32(CG); reg32 |= (1 << 31); @@ -434,7 +431,7 @@ * Enable DMI ASPM in the PCH */ RCBA32_AND_OR(DMC, ~(1 << 10), 0); - RCBA32_OR(LCAP, (1 << 11)|(1 << 10)); + RCBA32_OR(LCAP, (1 << 11) | (1 << 10)); RCBA32_OR(LCTL, 0x3); } @@ -446,6 +443,7 @@ if (config->spi_uvscc) RCBA32(0x3800 + 0xc8) = config->spi_uvscc; + if (config->spi_lvscc) RCBA32(0x3800 + 0xc4) = config->spi_lvscc; @@ -457,51 +455,51 @@ u16 dev_id; const char *dev_name; } pch_table[] = { - /* 6-series PCI ids from - * Intel® 6 Series Chipset and - * Intel® C200 Series Chipset - * Specification Update - NDA + /* + * 6-series PCI IDs from: + * Intel® 6 Series Chipset and Intel® C200 Series Chipset Specification Update - NDA * October 2013 * CDI / IBP#: 440377 */ - {0x1C41, "SFF Sample"}, - {0x1C42, "Desktop Sample"}, - {0x1C43, "Mobile Sample"}, - {0x1C44, "Z68"}, - {0x1C46, "P67"}, - {0x1C47, "UM67"}, - {0x1C49, "HM65"}, - {0x1C4A, "H67"}, - {0x1C4B, "HM67"}, - {0x1C4C, "Q65"}, - {0x1C4D, "QS67"}, - {0x1C4E, "Q67"}, - {0x1C4F, "QM67"}, - {0x1C50, "B65"}, - {0x1C52, "C202"}, - {0x1C54, "C204"}, - {0x1C56, "C206"}, - {0x1C5C, "H61"}, - /* 7-series PCI ids from Intel document 472178 */ - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, + {0x1c41, "SFF Sample"}, + {0x1c42, "Desktop Sample"}, + {0x1c43, "Mobile Sample"}, + {0x1c44, "Z68"}, + {0x1c46, "P67"}, + {0x1c47, "UM67"}, + {0x1c49, "HM65"}, + {0x1c4a, "H67"}, + {0x1c4b, "HM67"}, + {0x1c4c, "Q65"}, + {0x1c4d, "QS67"}, + {0x1c4e, "Q67"}, + {0x1c4f, "QM67"}, + {0x1c50, "B65"}, + {0x1c52, "C202"}, + {0x1c54, "C204"}, + {0x1c56, "C206"}, + {0x1c5c, "H61"}, + + /* 7-series PCI IDs from Intel document 472178 */ + {0x1e41, "Desktop Sample"}, + {0x1e42, "Mobile Sample"}, + {0x1e43, "SFF Sample"}, + {0x1e44, "Z77"}, + {0x1e45, "H71"}, + {0x1e46, "Z75"}, + {0x1e47, "Q77"}, + {0x1e48, "Q75"}, + {0x1e49, "B75"}, + {0x1e4a, "H77"}, + {0x1e53, "C216"}, + {0x1e55, "QM77"}, + {0x1e56, "QS77"}, + {0x1e58, "UM77"}, + {0x1e57, "HM77"}, + {0x1e59, "HM76"}, + {0x1e5d, "HM75"}, + {0x1e5e, "HM70"}, + {0x1e5f, "NM70"}, }; static void report_pch_info(struct device *dev) @@ -543,10 +541,10 @@ /* Initialize power management */ switch (pch_silicon_type()) { - case PCH_TYPE_CPT: /* CougarPoint */ + case PCH_TYPE_CPT: /* Cougar Point */ cpt_pm_init(dev); break; - case PCH_TYPE_PPT: /* PantherPoint */ + case PCH_TYPE_PPT: /* Panther Point */ ppt_pm_init(dev); break; default: @@ -583,69 +581,66 @@ pch_spi_init(dev); } +#define ASSIGNED_FIXED (IORESOURCE_ASSIGNED | IORESOURCE_FIXED) static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; u8 io_index = 0; - /* Get the normal PCI resources of this device. */ + /* Get the normal PCI resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* Add an extra subtractive resource for both memory and I/O */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0; res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0xff000000; - /* Some systems (e.g. X230) have 12 MiB flash. - SPI controller supports up to 2 x 16 MiB of flash but - address map limits this to 16MiB. */ + /* + * Some systems (e.g. X230) have 12 MiB flash. The SPI controller supports + * up to 2 x 16 MiB of flash but address map limits this to 16MiB. + */ res->size = 0x01000000; /* 16 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | ASSIGNED_FIXED; /* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen1_dec & 0xFFFC; res->size = (config->gen1_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; } if ((config->gen2_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen2_dec & 0xFFFC; res->size = (config->gen2_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; } if ((config->gen3_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen3_dec & 0xFFFC; res->size = (config->gen3_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; } if ((config->gen4_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen4_dec & 0xFFFC; res->size = (config->gen4_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; } } +#undef ASSIGNED_FIXED static void pch_lpc_enable(struct device *dev) { @@ -682,7 +677,7 @@ /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); - /* Add it to DSDT. */ + /* Add it to DSDT */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_pop_len(); @@ -746,6 +741,7 @@ ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } @@ -839,15 +835,12 @@ /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { - if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || - acpi_is_wakeup_s3()) { + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) outb(APM_CNT_FINALIZE, APM_CNT); - } } } -void intel_southbridge_override_spi( - struct intel_swseq_spi_config *spi_config) +void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) { struct device *dev = pcidev_on_root(0x1f, 0); @@ -883,10 +876,9 @@ }; -/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and - * Intel C200 Series Chipset +/* + * IDs for LPC device of Intel 6 Series, Intel 7 Series, and Intel C200 Series Chipsets */ - static const unsigned short pci_device_ids[] = { 0x1c40, 0x1c41, 0x1c42, 0x1c43, 0x1c44, 0x1c45, 0x1c46, 0x1c47, 0x1c48, 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c51, @@ -898,7 +890,8 @@ 0x1e53, 0x1e54, 0x1e55, 0x1e56, 0x1e57, 0x1e58, 0x1e59, 0x1e5a, 0x1e5b, 0x1e5c, 0x1e5d, 0x1e5e, 0x1e5f, - 0 }; + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b1f3bfe..2816f90 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -2,11 +2,10 @@ /* This file is part of the coreboot project. */ /* - * This is a ramstage driver for the Intel Management Engine found in the - * 6-series chipset. It handles the required boot-time messages over the - * MMIO-based Management Engine Interface to tell the ME that the BIOS is - * finished with POST. Additional messages are defined for debug but are - * not used unless the console loglevel is high enough. + * This is a ramstage driver for the Intel Management Engine found in the 6-series chipset. + * It handles the required boot-time messages over the MMIO-based Management Engine Interface + * to tell the ME that the BIOS is finished with POST. Additional messages are defined for + * debug but are not used unless the console loglevel is high enough. */ #include <arch/acpi.h> @@ -78,7 +77,6 @@ /* * ME/MEI access helpers using memcpy to avoid aliasing. */ - static inline void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset/sizeof(u32))); @@ -235,8 +233,8 @@ return mei_wait_for_me_ready(); } -static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, void *rsp_data, + int rsp_bytes) { struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; @@ -259,12 +257,13 @@ read_me_csr(&me); if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) break; + udelay(ME_DELAY); } if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", + expected, me.buffer_write_ptr - me.buffer_read_ptr); + return -1; } @@ -279,6 +278,7 @@ ndata = mei_rsp.length >> 2; if (mei_rsp.length & 3) ndata++; + if (ndata != (expected - 1)) { printk(BIOS_ERR, "ME: response is missing data\n"); return -1; @@ -286,21 +286,21 @@ /* Read and verify MKHI response header from the ME */ mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || + if (!mkhi_rsp.is_response || mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, command %u ?= %u, " + "is_response %u\n", mkhi->group_id, mkhi_rsp.group_id, mkhi->command, + mkhi_rsp.command, mkhi_rsp.is_response); + return -1; } ndata--; /* MKHI header has been read */ /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); + return -1; } @@ -318,13 +318,15 @@ return mei_wait_for_me_ready(); } -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, + void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; + if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0) return -1; + return 0; } @@ -385,8 +387,7 @@ static inline void print_cap(const char *name, int state) { - printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", - name, state ? "en" : "dis"); + printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", name, state ? "en" : "dis"); } /* Get ME Firmware Capabilities */ @@ -411,24 +412,22 @@ return -1; } - print_cap("Full Network manageability", cap.caps_sku.full_net); - print_cap("Regular Network manageability", cap.caps_sku.std_net); - print_cap("Manageability", cap.caps_sku.manageability); - print_cap("Small business technology", cap.caps_sku.small_business); - print_cap("Level III manageability", cap.caps_sku.l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", - cap.caps_sku.intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", - cap.caps_sku.intel_mpc); - print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); - print_cap("IPV6", cap.caps_sku.ipv6); - print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); - print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); - print_cap("TLS", cap.caps_sku.tls); - print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); + print_cap("Full Network manageability", cap.caps_sku.full_net); + print_cap("Regular Network manageability", cap.caps_sku.std_net); + print_cap("Manageability", cap.caps_sku.manageability); + print_cap("Small business technology", cap.caps_sku.small_business); + print_cap("Level III manageability", cap.caps_sku.l3manageability); + print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap.caps_sku.intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); + print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("IPV6", cap.caps_sku.ipv6); + print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); + print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); + print_cap("TLS", cap.caps_sku.tls); + print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); return 0; } @@ -473,8 +472,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (u32 *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) @@ -485,8 +483,7 @@ memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || + if (hfs.fpt_bad || hfs.working_state != ME_HFS_CWS_NORMAL || hfs.operation_mode != ME_HFS_MODE_NORMAL) return; @@ -495,8 +492,7 @@ /* Make sure IO is disabled */ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ @@ -578,8 +574,7 @@ .current_state = gmes.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); - elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, - &data, sizeof(data)); + elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); } return path; @@ -699,8 +694,7 @@ } /* - * Leave the ME unlocked in this path. - * It will be locked via SMI command later. + * Leave the ME unlocked in this path. It will be locked via SMI command later. */ break; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 054c29f..d78802c 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -44,7 +44,6 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; - static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -144,6 +143,7 @@ read_me_csr(&me); if (me.ready) return 0; + udelay(ME_DELAY); } @@ -207,7 +207,7 @@ /* * This implementation does not handle splitting large messages - * across multiple transactions. Ensure the requested length + * across multiple transactions. Ensure the requested length * will fit in the available circular buffer depth. */ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { @@ -238,8 +238,7 @@ return mei_wait_for_me_ready(); } -static int mei_recv_msg(struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) { struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; @@ -255,7 +254,7 @@ /* * The interrupt status bit does not appear to indicate that the - * message has actually been received. Instead we wait until the + * message has actually been received. Instead we wait until the * expected number of dwords are present in the circular buffer. */ for (n = ME_RETRY; n; --n) { @@ -265,9 +264,8 @@ udelay(ME_DELAY); } if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", + expected, me.buffer_write_ptr - me.buffer_read_ptr); return -1; } @@ -282,6 +280,7 @@ ndata = mei_rsp.length >> 2; if (mei_rsp.length & 3) ndata++; + if (ndata != (expected - 1)) { printk(BIOS_ERR, "ME: response is missing data %d != %d\n", ndata, (expected - 1)); @@ -290,21 +289,20 @@ /* Read and verify MKHI response header from the ME */ mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || + if (!mkhi_rsp.is_response || mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u,command %u ?= %u, " + "is_response %u\n", mkhi->group_id, mkhi_rsp.group_id, mkhi->command, + mkhi_rsp.command, mkhi_rsp.is_response); return -1; } ndata--; /* MKHI header has been read */ /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); + return -1; } @@ -322,11 +320,12 @@ return mei_wait_for_me_ready(); } -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, + void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; + if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) return -1; return 0; @@ -334,8 +333,7 @@ static inline void print_cap(const char *name, int state) { - printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); + printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", name, state ? " en" : "dis"); } static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) @@ -385,22 +383,22 @@ return; } - print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("Small business technology", cap->small_business); - print_cap("Level III manageability", cap->l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("Small business technology", cap->small_business); + print_cap("Level III manageability", cap->l3manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); } #if CONFIG(CHROMEOS) && 0 /* DISABLED */ @@ -469,8 +467,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (void *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + mei_base_address = (void *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) @@ -481,8 +478,7 @@ memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || + if (hfs.fpt_bad || hfs.working_state != ME_HFS_CWS_NORMAL || hfs.operation_mode != ME_HFS_MODE_NORMAL) return; @@ -491,8 +487,7 @@ /* Make sure IO is disabled */ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ @@ -566,8 +561,7 @@ .current_state = gmes.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); - elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, - &data, sizeof(data)); + elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); } return path; @@ -703,8 +697,7 @@ } /* - * Leave the ME unlocked in this path. - * It will be locked via SMI command later. + * Leave the ME unlocked in this path. It will be locked via SMI command later. */ break; @@ -763,10 +756,8 @@ (csr.buffer_depth - 1); } #endif -/* - * mbp seems to be following its own flow, let's retrieve it in a dedicated - * function. - */ + +/* mbp seems to be following its own flow, let's retrieve it in a dedicated function */ static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index a19fc01..9ecfc28 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -5,56 +5,56 @@ #include "me.h" /* HFS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { +static const char *me_cws_strs[] = { [ME_HFS_CWS_RESET] = "Reset", [ME_HFS_CWS_INIT] = "Initializing", [ME_HFS_CWS_REC] = "Recovery", [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", }; /* HFS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { +static const char *me_opstate_strs[] = { [ME_HFS_STATE_PREBOOT] = "Preboot", [ME_HFS_STATE_M0_UMA] = "M0 with UMA", [ME_HFS_STATE_M3] = "M3 without UMA", [ME_HFS_STATE_M0] = "M0 without UMA", [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error", }; /* HFS[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { +static const char *me_opmode_strs[] = { [ME_HFS_MODE_NORMAL] = "Normal", [ME_HFS_MODE_DEBUG] = "Debug or Disabled by AltDisableBit", [ME_HFS_MODE_DIS] = "Soft Temporary Disable", [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message", }; /* HFS[15:12] Error Code Values */ -static const char *me_error_values[] = { +static const char *me_error_strs[] = { [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" + [ME_HFS_ERROR_DEBUG] = "Debug Failure", }; /* GMES[31:28] ME Progress Code */ -static const char *me_progress_values[] = { +static const char *me_progress_strs[] = { [ME_GMES_PHASE_ROM] = "ROM Phase", [ME_GMES_PHASE_BUP] = "BUP Phase", [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", [ME_GMES_PHASE_POLICY] = "Policy Module", [ME_GMES_PHASE_MODULE] = "Module Loading", [ME_GMES_PHASE_UNKNOWN] = "Unknown", - [ME_GMES_PHASE_HOST] = "Host Communication" + [ME_GMES_PHASE_HOST] = "Host Communication", }; /* GMES[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { +static const char *me_pmevent_strs[] = { [0x00] = "Clean Moff->Mx wake", [0x01] = "Moff->Mx wake after an error", [0x02] = "Clean global reset", @@ -67,17 +67,17 @@ [0x09] = "Non-power cycle reset", [0x0a] = "Power cycle reset through M3", [0x0b] = "Power cycle reset through Moff", - [0x0c] = "Sx/Mx->Sx/Moff" + [0x0c] = "Sx/Mx->Sx/Moff", }; /* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { +static const char *me_progress_rom_strs[] = { [0x00] = "BEGIN", - [0x06] = "DISABLE" + [0x06] = "DISABLE", }; /* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { +static const char *me_progress_bup_strs[] = { [0x00] = "Initialization starts", [0x01] = "Disable the host wake event", [0x04] = "Flow determination start process", @@ -105,7 +105,7 @@ }; /* Progress Code 3 states */ -static const char *me_progress_policy_values[] = { +static const char *me_progress_policy_strs[] = { [0x00] = "Entery into Policy Module", [0x03] = "Received S3 entry", [0x04] = "Received S4 entry", @@ -128,53 +128,41 @@ if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) return; +#define PRINT_ME(...) printk(BIOS_DEBUG, __VA_ARGS__) /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); - printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[gmes->progress_code]); - printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[gmes->current_pmevent]); + PRINT_ME("ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); + PRINT_ME("ME: Bringup Loader Failure : %s\n", hfs->ft_bup_ld_flr ? "YES" : "NO"); + PRINT_ME("ME: Firmware Init Complete : %s\n", hfs->fw_init_complete ? "YES" : "NO"); + PRINT_ME("ME: Manufacturing Mode : %s\n", hfs->mfg_mode ? "YES" : "NO"); + PRINT_ME("ME: Boot Options Present : %s\n", hfs->boot_options_present ? "YES" : "NO"); + PRINT_ME("ME: Update In Progress : %s\n", hfs->update_in_progress ? "YES" : "NO"); + PRINT_ME("ME: Current Working State : %s\n", me_cws_strs[hfs->working_state]); + PRINT_ME("ME: Current Operation State : %s\n", me_opstate_strs[hfs->operation_state]); + PRINT_ME("ME: Current Operation Mode : %s\n", me_opmode_strs[hfs->operation_mode]); + PRINT_ME("ME: Error Code : %s\n", me_error_strs[hfs->error_code]); + PRINT_ME("ME: Progress Phase : %s\n", me_progress_strs[gmes->progress_code]); + PRINT_ME("ME: Power Management Event : %s\n", me_pmevent_strs[gmes->current_pmevent]); + PRINT_ME("ME: Progress Phase State : "); +#undef PRINT_ME - printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (gmes->progress_code) { case ME_GMES_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - me_progress_rom_values[gmes->current_state]); + printk(BIOS_DEBUG, "%s", me_progress_rom_strs[gmes->current_state]); break; case ME_GMES_PHASE_BUP: /* Bringup Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[gmes->current_state]) + if (gmes->current_state < ARRAY_SIZE(me_progress_bup_strs) + && me_progress_bup_strs[gmes->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[gmes->current_state]); + me_progress_bup_strs[gmes->current_state]); else printk(BIOS_DEBUG, "0x%02x", gmes->current_state); break; case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values) - && me_progress_policy_values[gmes->current_state]) - printk(BIOS_DEBUG, "%s", - me_progress_policy_values[gmes->current_state]); + if (gmes->current_state < ARRAY_SIZE(me_progress_policy_strs) + && me_progress_policy_strs[gmes->current_state]) + printk(BIOS_DEBUG, "%s", me_progress_policy_strs[gmes->current_state]); else printk(BIOS_DEBUG, "0x%02x", gmes->current_state); break; diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 254c5b2..650010b 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -67,26 +67,26 @@ u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; + u8 rsvd5[9]; /* Backlight Control */ u8 blcs; /* 0x64 - Backlight Control possible */ u8 brtl; u8 odds; - u8 rsvd6[0x7]; + u8 rsvd6[7]; /* Ambient Light Sensors*/ u8 alse; /* 0x6e - ALS enable */ u8 alaf; u8 llow; u8 lhih; - u8 rsvd7[0x6]; + u8 rsvd7[6]; /* Extended Mobile Access */ u8 emae; /* 0x78 - EMA enable */ u16 emap; /* 0x79 - EMA pointer */ u16 emal; /* 0x7a - EMA Length */ - u8 rsvd8[0x5]; + u8 rsvd8[5]; /* MEF */ u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; + u8 rsvd9[9]; /* TPM support */ u8 tpmp; /* 0x8c - TPM */ u8 tpme; diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index cb31880..122fd80 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -52,6 +52,7 @@ /* CougarPoint minimum revision */ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) return 1; + /* PantherPoint any revision */ if (cur_type == PCH_TYPE_PPT) return 1; @@ -96,6 +97,7 @@ RCBA32(IOBPS) = IOBPS_RW_BX; else RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) return; @@ -119,6 +121,7 @@ RCBA32(IOBPS) = IOBPS_RW_BX; else RCBA32(IOBPS) = IOBPS_WRITE_AX; + if (!iobp_poll()) return; @@ -203,19 +206,15 @@ printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); - /* Go through static device tree list of devices - * because enumeration is still in progress */ + /* Go through static device tree list because enumeration is still in progress */ for (port = all_devices; port; port = port->next) { /* Only care about PCIe root ports */ - if (PCI_SLOT(port->path.pci.devfn) != - PCI_SLOT(dev->path.pci.devfn)) + if (PCI_SLOT(port->path.pci.devfn) != PCI_SLOT(dev->path.pci.devfn)) continue; /* Check if port is in range and enabled */ port_func = PCI_FUNC(port->path.pci.devfn); - if (port_func >= dev_func && - port_func < (dev_func + 4) && - port->enabled) + if (port_func >= dev_func && port_func < (dev_func + 4) && port->enabled) return 1; } @@ -231,8 +230,7 @@ { u32 old_rpfn = new_rpfn; - printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", - old_fn, new_fn); + printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", old_fn, new_fn); new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); @@ -242,60 +240,48 @@ } /* Update devicetree with new Root Port function number assignment */ -static void pch_pcie_devicetree_update( - struct southbridge_intel_bd82x6x_config *config) +static void pch_pcie_devicetree_update(struct southbridge_intel_bd82x6x_config *config) { struct device *dev; - /* - * hotplug map should also be updated along with their - * corresponding port - */ + /* Hotplug map should also be updated along with their corresponding port */ u8 new_hotplug_map[sizeof(config->pcie_hotplug_map)]; /* * Slots that didn't move need the hotplug setting copied too, * so "new_hotplug_map" is initialized with the values of the old map. */ - memcpy(new_hotplug_map, config->pcie_hotplug_map, - sizeof(new_hotplug_map)); + memcpy(new_hotplug_map, config->pcie_hotplug_map, sizeof(new_hotplug_map)); /* Update the function numbers in the static devicetree */ for (dev = all_devices; dev; dev = dev->next) { u8 new_devfn; /* Only care about PCH PCIe root ports */ - if (PCI_SLOT(dev->path.pci.devfn) != - PCH_PCIE_DEV_SLOT) + if (PCI_SLOT(dev->path.pci.devfn) != PCH_PCIE_DEV_SLOT) continue; /* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, - RPFN_FNGET(new_rpfn, - PCI_FUNC(dev->path.pci.devfn))); + RPFN_FNGET(new_rpfn, PCI_FUNC(dev->path.pci.devfn))); if (dev->path.pci.devfn != new_devfn) { - printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), + printk(BIOS_DEBUG, "PCH: PCIe map %02x.%1x -> %02x.%1x\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); /* - * Copy the flag to its new position along with - * the corresponding port + * Copy the flag to its new position along with the corresponding port */ new_hotplug_map[PCI_FUNC(new_devfn)] = - config->pcie_hotplug_map - [PCI_FUNC(dev->path.pci.devfn)]; + config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]; dev->path.pci.devfn = new_devfn; } } /* Copy the updated map back to its place */ - memcpy(config->pcie_hotplug_map, new_hotplug_map, - sizeof(new_hotplug_map)); + memcpy(config->pcie_hotplug_map, new_hotplug_map, sizeof(new_hotplug_map)); } /* Special handling for PCIe Root Port devices */ @@ -308,24 +294,22 @@ return; /* - * Save a copy of the Root Port Function Number map when - * starting to walk the list of PCIe Root Ports so it can - * be updated locally and written out when the last port + * Save a copy of the Root Port Function Number map when starting to walk the list of + * PCIe Root Ports so it can be updated locally and written out when the last port * has been processed. */ if (PCI_FUNC(dev->path.pci.devfn) == 0) { new_rpfn = RCBA32(RPFN); /* - * Enable Root Port coalescing if the first port is disabled - * or the other devices will not be enumerated by the OS. + * Enable Root Port coalescing if the first port is disabled. + * Otherwise, the other devices will not be enumerated by the OS. */ if (!dev->enabled) config->pcie_port_coalesce = 1; if (config->pcie_port_coalesce) - printk(BIOS_INFO, - "PCH: PCIe Root Port coalescing is enabled\n"); + printk(BIOS_INFO, "PCH: PCIe Root Port coalescing is enabled\n"); } if (!dev->enabled) { @@ -360,8 +344,7 @@ /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); /* Do not claim downstream transactions for PCIe ports */ @@ -377,13 +360,12 @@ * port in order to maintain linear order starting at zero. */ if (config->pcie_port_coalesce) { - for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { + for (fn = 0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { if (!(new_rpfn & RPFN_HIDE(fn))) continue; /* Swap places with this function */ - pch_pcie_function_swap( - PCI_FUNC(dev->path.pci.devfn), fn); + pch_pcie_function_swap(PCI_FUNC(dev->path.pci.devfn), fn); break; } } @@ -399,8 +381,7 @@ * update the Root Port Function Number and Hide register. */ if (PCI_FUNC(dev->path.pci.devfn) == 7) { - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - RCBA32(RPFN), new_rpfn); + printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", RCBA32(RPFN), new_rpfn); RCBA32(RPFN) = new_rpfn; /* Update static devictree with new function numbers */ @@ -422,8 +403,7 @@ /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); /* Hide this device if possible */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 18383f6..88b479a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -7,8 +7,8 @@ #include <arch/acpi.h> /* PCH types */ -#define PCH_TYPE_CPT 0x1c /* CougarPoint */ -#define PCH_TYPE_PPT 0x1e /* IvyBridge */ +#define PCH_TYPE_CPT 0x1c /* Cougar Point */ +#define PCH_TYPE_PPT 0x1e /* Panther Point */ /* PCH stepping values for LPC device */ #define PCH_STEP_A0 0 @@ -19,12 +19,10 @@ #define PCH_STEP_B3 5 /* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. + * It does not matter where we put the SMBus I/O base, as long as we keep it consistent and + * don't interfere with other devices. Stage2 will relocate this anyway. Our solution is to + * have SMBus initialization move the I/O to SMBUS_IO_BASE again. But handling static BARs + * is a generic problem that should be solved in the device allocator. */ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 @@ -237,7 +235,7 @@ #define PMBASE 0x40 #define CIR0 0x0050 /* 32bit */ -#define TCLOCKDN (1u << 31) +#define TCLOCKDN (1 << 31) #define RCTCL 0x0100 /* 32bit */ #define ESD 0x0104 /* 32bit */ @@ -381,9 +379,8 @@ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(x,a,b,c,d) \ - RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define DIR_ROUTE(x, a, b, c, d) \ + RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define PRSTS 0x3310 /* 32bit */ #define CIR7 0x3314 /* 32bit */ @@ -416,7 +413,7 @@ #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) +#define PCH_DISABLE_ALWAYS ((1 << 0) | (1 << 26)) #define PCH_DISABLE_P2P (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) @@ -499,7 +496,7 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only +#define PM2_CNT 0x50 /* Mobile only */ #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -559,5 +556,5 @@ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ -#endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ +#endif /* __ACPI__ */ +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 459ed46..2183dc6 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -37,7 +37,7 @@ /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); - //reg16 |= 0xf900; + // reg16 |= 0xf900; pci_write_config16(dev, PSTS, reg16); reg16 = pci_read_config16(dev, SECSTS); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index c70e09c..345797b 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -96,7 +96,7 @@ /* Adjust Common Clock exit latency */ reg32 = pci_read_config32(dev, 0xd8); reg32 &= ~(1 << 17); - reg32 |= (1 << 16) | (1 << 15); + reg32 |= (1 << 16) | (1 << 15); reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */ pci_write_config32(dev, 0xd8, reg32); @@ -215,8 +215,7 @@ reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Set Cache Line Size to 0x10 */ - // This has no effect but the OS might expect it + /* Set Cache Line Size to 0x10. This has no effect but the OS might expect it. */ pci_write_config8(dev, 0x0c, 0x10); reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); @@ -237,18 +236,16 @@ /* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); - //reg16 |= 0xf900; + // reg16 |= 0xf900; pci_write_config16(dev, 0x06, reg16); reg16 = pci_read_config16(dev, 0x1e); - //reg16 |= 0xf900; + // reg16 |= 0xf900; pci_write_config16(dev, 0x1e, reg16); /* Enable expresscard hotplug events. */ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - pci_write_config32(dev, 0xd8, - pci_read_config32(dev, 0xd8) - | (1 << 30)); + pci_write_config32(dev, 0xd8, pci_read_config32(dev, 0xd8) | (1 << 30)); pci_write_config16(dev, 0x42, 0x142); } } @@ -277,14 +274,9 @@ static const char *pch_pcie_acpi_name(const struct device *dev) { if (dev && PCI_SLOT(dev->path.pci.devfn) == 0x1c) { - static const char *names[] = { "RP01", - "RP02", - "RP03", - "RP04", - "RP05", - "RP06", - "RP07", - "RP08"}; + static const char *names[] = { + "RP01", "RP02", "RP03", "RP04", "RP05", "RP06", "RP07", "RP08", + }; return names[PCI_FUNC(dev->path.pci.devfn)]; } @@ -307,11 +299,12 @@ .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, - 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, - 0x1e10, 0x1e12, 0x1e14, 0x1e16, - 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c10, 0x1c12, 0x1c14, 0x1c16, 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, + 0x1e10, 0x1e12, 0x1e14, 0x1e16, 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, + + 0, +}; static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 3a2ed10..aa32d85 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -63,11 +63,11 @@ pci_write_config8(dev, INTR_LN, 0x0a); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); + + pci_write_config16(dev, IDE_TIM_SEC, + IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); @@ -79,41 +79,43 @@ /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ + reg16 &= ~0x3f; /* 6 ports SKU + ORM */ reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x0183); /* Initialize AHCI memory-mapped space */ abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ + + /* CAP (HBA Capabilities): enable power management */ reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS + reg32 |= 0x0c006000; /* Set PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* Clear SXS+EMS+PMS */ + /* Set ISS, if available */ - if (config->sata_interface_speed_support) - { + if (config->sata_interface_speed_support) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; + reg32 |= (config->sata_interface_speed_support & 0x03) << 20; } write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void) read32(abar + 0x0c); /* Read back 1 */ + (void) read32(abar + 0x0c); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); reg32 &= ~0x00000002; write32(abar + 0x24, reg32); + /* VSP (Vendor Specific Register */ reg32 = read32(abar + 0xa0); reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); + } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); @@ -126,9 +128,7 @@ reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - /* Native mode capable on both primary and secondary (0xa) - * or'ed with enabled (0x50) = 0xf - */ + /* Native mode capable on both primary and secondary or'ed with enabled */ pci_write_config8(dev, 0x09, 0x8f); /* Set Interrupt Line */ @@ -136,12 +136,11 @@ pci_write_config8(dev, INTR_LN, 0xff); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_SITRE | IDE_ISP_3_CLOCKS | - IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0 | IDE_PPE0); + + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0 | IDE_SITRE); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); @@ -158,8 +157,7 @@ pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x0183); } /* Set Gen3 Transmitter settings if needed */ @@ -176,12 +174,12 @@ sir_write(dev, 0x28, 0xa0000033); reg32 = sir_read(dev, 0x54); reg32 &= 0xff000000; - reg32 |= 0x5555aa; + reg32 |= 0x005555aa; sir_write(dev, 0x54, reg32); sir_write(dev, 0x64, 0xcccc8484); reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; - reg32 |= 0xcccc; + reg32 |= 0x0000cccc; sir_write(dev, 0x68, reg32); reg32 = sir_read(dev, 0x78); reg32 &= 0x0000ffff; @@ -247,14 +245,16 @@ = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &sata_pci_ops, .acpi_name = sata_acpi_name, }; -static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, - 0x1e00, 0x1e01, 0x1e02, 0x1e03, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c00, 0x1c01, 0x1c02, 0x1c03, 0x1e00, 0x1e01, 0x1e02, 0x1e03, + + 0, +}; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 11568b3..3af8555 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -53,12 +53,12 @@ } static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, }; static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 78ac08b..ec9a3d0 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -30,9 +30,10 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 + /* + * gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 */ gnvs->smif = 0; return 1; /* IO trap handled */ @@ -42,8 +43,7 @@ return 0; } -static void southbridge_gate_memory_reset_real(int offset, - u16 use, u16 io, u16 lvl) +static void southbridge_gate_memory_reset_real(int offset, u16 use, u16 io, u16 lvl) { u32 reg32; @@ -109,8 +109,7 @@ reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); - xhci_bar = pci_read_config32(PCH_XHCI_DEV, - PCI_BASE_ADDRESS_0) & ~0xFUL; + xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xfUL; if ((xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); @@ -141,15 +140,15 @@ void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; + + u32 trap_sts, trap_cycle, data, mask = 0; int i; trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -162,8 +161,8 @@ return; } - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ + /* IOTRAP(2) currently unused */ + /* IOTRAP(1) currently unused */ /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { @@ -179,7 +178,10 @@ } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i = 0; i < 4; i++) + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); @@ -200,8 +202,8 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); + const em64t101_smm_state_save_area_t *state = smi_apmc_find_state_save(apm_cnt); + if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (global_nvs_t *)((u32)state->rbx); diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 1d7120d..a6944fc 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -36,7 +36,7 @@ //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); - /* For others, done in MRC. */ + /* For others, done in MRC */ #if CONFIG(USE_NATIVE_RAMINIT) struct resource *res; u8 access_cntl; @@ -50,8 +50,7 @@ if (res) { /* Number of ports and companion controllers. */ reg32 = read32((void *)(uintptr_t)(res->base + 4)); - write32((void *)(uintptr_t)(res->base + 4), - (reg32 & 0xfff00000) | 3); + write32((void *)(uintptr_t)(res->base + 4), (reg32 & 0xfff00000) | 3); } /* Restore protection. */ @@ -61,19 +60,18 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl; access_cntl = pci_read_config8(dev, 0x80); - /* Enable writes to protected registers. */ + /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); pci_dev_set_subsystem(dev, vendor, device); - /* Restore protection. */ + /* Restore protection */ pci_write_config8(dev, 0x80, access_cntl); } @@ -89,7 +87,7 @@ } static struct pci_operations lops_pci = { - .set_subsystem = &usb_ehci_set_subsystem, + .set_subsystem = &usb_ehci_set_subsystem, }; static struct device_operations usb_ehci_ops = { @@ -97,13 +95,12 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, .acpi_name = usb_ehci_acpi_name, }; -static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, - 0 }; +static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, 0 }; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 8696d59..cd81bb8 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -5,10 +5,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "pch.h" #include <device/pci_ehci.h> #include <device/pci_ops.h> #include "chip.h" +#include "pch.h" static void usb_xhci_init(struct device *dev) { @@ -20,7 +20,7 @@ if (config->xhci_overcurrent_mapping) pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping); - /* lock overcurrent map */ + /* Lock overcurrent map */ reg32 = pci_read_config32(dev, 0x44); reg32 |= 1; pci_write_config32(dev, 0x44, reg32); @@ -31,9 +31,8 @@ /* Enable clock gating */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~((1 << 20) | (1 << 21)); - reg32 |= (1 << 19) | (1 << 18) | (1 << 17); - reg32 |= (1 << 10) | (1 << 9) | (1 << 8); - reg32 |= (1 << 31); /* lock */ + reg32 |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 10) | (1 << 9) | (1 << 8); + reg32 |= (1 << 31); /* lock */ pci_write_config32(dev, 0x40, reg32); printk(BIOS_DEBUG, "done.\n"); @@ -45,7 +44,7 @@ } static struct pci_operations xhci_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_xhci_ops = { @@ -53,7 +52,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &xhci_pci_ops, .acpi_name = xhci_acpi_name, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/40020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie38c4ed7c2956bf96cffd84276ab48d4b9eab5db Gerrit-Change-Number: 40020 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: [WIP] nb/intel/sandybridge: Use macros for DMI init
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39634 ) Change subject: [WIP] nb/intel/sandybridge: Use macros for DMI init ...................................................................... [WIP] nb/intel/sandybridge: Use macros for DMI init Put names to DMI registers, and use for-each style macros. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: I3c155f30b5642828c958cd2650aad5547b58d00b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_dmi.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 113 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/39634/1 diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 0ffabd1..82a1292 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -18,99 +18,99 @@ void early_init_dmi(void) { - int i; + int lane, bundle; - for (i = 0; i < 2; i++) { - DMIBAR32(0x0914 + (i << 5)) |= 1 << 31; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(LOADBUSCTL0(bundle)) |= 1 << 31; } - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000; - DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11); + FOR_EACH_P_LANE(lane) { + DMIBAR32(AFELNxCFG0(lane)) &= ~0x0c000000; + DMIBAR32(AFELNxCFG1(lane)) |= (1 << 11); } - DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30); + DMIBAR32(AFECMNCFG7) = (DMIBAR32(AFECMNCFG7) & 0x0fffffff) | (1 << 30); - for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000; - DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG1(bundle)) &= ~0x01c00000; + DMIBAR32(AFEBNDxCFG3(bundle)) &= ~0x000e0000; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG3(bundle)) &= ~0x01e00000; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec - DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec; - DMIBAR32(0x090c + (i << 5)); // !!! = 0x00000208 - DMIBAR32(0x090c + (i << 5)) = 0x00000128; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG1(bundle)); // !!! = 0x7a1842ec + DMIBAR32(AFEBNDxCFG1(bundle)) = 0x7a1842ec; + DMIBAR32(AFEBNDxCFG3(bundle)); // !!! = 0x00000208 + DMIBAR32(AFEBNDxCFG3(bundle)) = 0x00000128; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 - DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(MAGIC_CHICKEN(bundle)); // !!! = 0x46139008 + DMIBAR32(MAGIC_CHICKEN(bundle)) = 0x46139008; } DMIBAR32(0x0c04); // !!! = 0x2e680008 DMIBAR32(0x0c04) = 0x2e680008; - for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec - DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG1(bundle)); // !!! = 0x7a1842ec + DMIBAR32(AFEBNDxCFG1(bundle)) = 0x3a1842ec; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0910 + (i << 5)); // !!! = 0x00006300 - DMIBAR32(0x0910 + (i << 5)) = 0x00004300; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG4(bundle)); // !!! = 0x00006300 + DMIBAR32(AFEBNDxCFG4(bundle)) = 0x00004300; } - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042010 - DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + FOR_EACH_P_LANE(lane) { + DMIBAR32(AFELNxCFG0(lane)); // !!! = 0x03042010 + DMIBAR32(AFELNxCFG0(lane)) = 0x03042018; } DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a04 + (i << 4)); // !!! = 0x0c0708f0 - DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0; + FOR_EACH_P_LANE(lane) { + DMIBAR32(AFELNxCFG1(lane)); // !!! = 0x0c0708f0 + DMIBAR32(AFELNxCFG1(lane)) = 0x0c0718f0; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0900 + (i << 5)); // !!! = 0x50000000 - DMIBAR32(0x0900 + (i << 5)) = 0x50000000; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG0(bundle)); // !!! = 0x50000000 + DMIBAR32(AFEBNDxCFG0(bundle)) = 0x50000000; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff - DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG2(bundle)); // !!! = 0x51ffffff + DMIBAR32(AFEBNDxCFG2(bundle)) = 0x51ffffff; } - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 - DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + FOR_EACH_P_LANE(lane) { + DMIBAR32(AFELNxCFG0(lane)); // !!! = 0x03042018 + DMIBAR32(AFELNxCFG0(lane)) = 0x03042018; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 - DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(MAGIC_CHICKEN(bundle)); // !!! = 0x46139008 + DMIBAR32(MAGIC_CHICKEN(bundle)) = 0x46139008; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1842ec - DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG1(bundle)); // !!! = 0x3a1842ec + DMIBAR32(AFEBNDxCFG1(bundle)) = 0x3a1846ec; } - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 - DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + FOR_EACH_P_LANE(lane) { + DMIBAR32(AFELNxCFG0(lane)); // !!! = 0x03042018 + DMIBAR32(AFELNxCFG0(lane)) = 0x03042018; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff - DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG2(bundle)); // !!! = 0x51ffffff + DMIBAR32(AFEBNDxCFG2(bundle)) = 0x51ffffff; } DMIBAR32(0x0c00); // !!! = 0x29700c08 @@ -119,58 +119,58 @@ DMIBAR32(0x0c0c); // !!! = 0x16063400 DMIBAR32(0x0c0c) = 0x00063400; - for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 - DMIBAR32(0x0700 + (i << 5)) = 0x46339008; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(MAGIC_CHICKEN(bundle)); // !!! = 0x46139008 + DMIBAR32(MAGIC_CHICKEN(bundle)) = 0x46339008; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46339008 - DMIBAR32(0x0700 + (i << 5)) = 0x45339008; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(MAGIC_CHICKEN(bundle)); // !!! = 0x46339008 + DMIBAR32(MAGIC_CHICKEN(bundle)) = 0x45339008; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45339008 - DMIBAR32(0x0700 + (i << 5)) = 0x453b9008; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(MAGIC_CHICKEN(bundle)); // !!! = 0x45339008 + DMIBAR32(MAGIC_CHICKEN(bundle)) = 0x453b9008; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x453b9008 - DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(MAGIC_CHICKEN(bundle)); // !!! = 0x453b9008 + DMIBAR32(MAGIC_CHICKEN(bundle)) = 0x45bb9008; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45bb9008 - DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(MAGIC_CHICKEN(bundle)); // !!! = 0x45bb9008 + DMIBAR32(MAGIC_CHICKEN(bundle)) = 0x45fb9008; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 - DMIBAR32(0x0914 + (i << 5)) = 0x9021a280; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(LOADBUSCTL0(bundle)); // !!! = 0x9021a080 + DMIBAR32(LOADBUSCTL0(bundle)) = 0x9021a280; } - for (i = 0; i < 2; i++) { - DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 - DMIBAR32(0x0914 + (i << 5)) = 0x9821a280; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(LOADBUSCTL0(bundle)); // !!! = 0x9021a080 + DMIBAR32(LOADBUSCTL0(bundle)) = 0x9821a280; } - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 - DMIBAR32(0x0a00 + (i << 4)) = 0x03242018; + FOR_EACH_P_LANE(lane) { + DMIBAR32(AFELNxCFG0(lane)); // !!! = 0x03042018 + DMIBAR32(AFELNxCFG0(lane)) = 0x03242018; } - DMIBAR32(0x0258); // !!! = 0x40000600 - DMIBAR32(0x0258) = 0x60000600; + DMIBAR32(PEG_CFG4); // !!! = 0x40000600 + DMIBAR32(PEG_CFG4) = 0x60000600; - for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1846ec - DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec; - DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9821a280 - DMIBAR32(0x0914 + (i << 5)) = 0x98200280; + FOR_EACH_BUNDLE(bundle) { + DMIBAR32(AFEBNDxCFG1(bundle)); // !!! = 0x3a1846ec + DMIBAR32(AFEBNDxCFG1(bundle)) = 0x2a1846ec; + DMIBAR32(LOADBUSCTL0(bundle)); // !!! = 0x9821a280 + DMIBAR32(LOADBUSCTL0(bundle)) = 0x98200280; } - DMIBAR32(0x022c); // !!! = 0x00c26460 - DMIBAR32(0x022c) = 0x00c2403c; + DMIBAR32(PEG_L0SLAT); // !!! = 0x00c26460 + DMIBAR32(PEG_L0SLAT) = 0x00c2403c; early_pch_init_native_dmi_pre(); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8fb72cc..e40106c 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -115,7 +115,33 @@ /* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ -#define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */ +/* Per-bundle and per-lane register group helpers */ +#define BUNDLE(reg, bundle) ((reg) + ((bundle) << 5)) +#define P_LANE(reg, p_lane) ((reg) + ((p_lane) << 4)) + +/* Per-bundle and per-lane register group iterators */ +#define FOR_EACH_BUNDLE(bundle) for (bundle = 0; bundle < 2; bundle++) +#define FOR_EACH_P_LANE(p_lane) for (p_lane = 0; p_lane < 4; p_lane++) + +/* Register definitions */ +#define PEG_CFG4 0x258 /* PEG Config 4 */ +#define PEG_L0SLAT 0x22c /* PEG L0s Control */ + +#define MAGIC_CHICKEN(bundle) BUNDLE(0x700, bundle) /* Undocumented chicken bits */ + +#define AFEBNDxCFG0(bundle) BUNDLE(0x900, bundle) /* PEG AFE Bundle Config 0 */ +#define AFEBNDxCFG1(bundle) BUNDLE(0x904, bundle) /* PEG AFE Bundle Config 1 */ +#define AFEBNDxCFG2(bundle) BUNDLE(0x908, bundle) /* PEG AFE Bundle Config 2 */ +#define AFEBNDxCFG3(bundle) BUNDLE(0x90c, bundle) /* PEG AFE Bundle Config 3 */ +#define AFEBNDxCFG4(bundle) BUNDLE(0x910, bundle) /* PEG AFE Bundle Config 4 */ +#define LOADBUSCTL0(bundle) BUNDLE(0x914, bundle) /* PEG Load Bus Control */ + +#define AFELNxCFG0(lane) P_LANE(0xa00, lane) /* PEG AFE Lane Config 0 */ +#define AFELNxCFG1(lane) P_LANE(0xa04, lane) /* PEG AFE Lane Config 1 */ + +#define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */ + +#define AFECMNCFG7 0xc30 /* DMI AFE Common Config 7 */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c155f30b5642828c958cd2650aad5547b58d00b Gerrit-Change-Number: 39634 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/intel/skylake: Do cosmetic fixes
by Angel Pons (Code Review) May 3, 2020

May 3, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35172 ) Change subject: soc/intel/skylake: Do cosmetic fixes ...................................................................... soc/intel/skylake: Do cosmetic fixes This is mostly line reflowing to make use of the increased line length limit of 96 characters. Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/fspcar.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/vr_config.c 39 files changed, 561 insertions(+), 1,015 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index ccfc7b7..649220f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -191,8 +191,7 @@ /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif @@ -225,8 +224,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); return acpi_madt_irq_overrides(current); } @@ -526,15 +524,13 @@ /* Generate processor \_PR.CPUx */ acpigen_write_processor( - cpu_id*cores_per_package+core_id, - pcontrol_blk, plen); + cpu_id*cores_per_package+core_id, pcontrol_blk, plen); /* Generate C-state tables */ generate_c_state_entries(is_s0ix_enable); if (config->eist_enable) { /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); + generate_p_state_entries(core_id, cores_per_package); if (config->speed_shift_enable) acpigen_write_CPPC_method(); } @@ -569,8 +565,8 @@ /* Add RMRR entry */ tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_rmrr(current, 0, sa_get_gsm_base(), + sa_get_tolud_base() - 1); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_rmrr_fixup(tmp, current); } @@ -606,8 +602,7 @@ return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, - unsigned long current, +unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { const struct soc_intel_skylake_config *const config = config_of(dev); @@ -648,12 +643,10 @@ return current; } -unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - current = acpi_write_dbg2_pci_uart(rsdp, current, - uart_get_device(), + current = acpi_write_dbg2_pci_uart(rsdp, current, uart_get_device(), ACPI_ACCESS_SIZE_DWORD_ACCESS); current = acpi_write_hpet(device, current, rsdp); return acpi_align_current(current); diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index e9ca2d8..2b788c6 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. + * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..1ec9f5d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -93,19 +93,16 @@ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); /* - * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] - * to the same value programmed in PMC PCI Offset 48h bit[31:16], - * this has an implication of making sure the PWRMBASE to be - * 64KB aligned. + * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value + * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure + * the PWRMBASE to be 64KB aligned. * - * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] - * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an - * implication of making sure the memory allocated to PWRMBASE to be - * 64KB in size. + * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value + * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure + * the memory allocated to PWRMBASE to be 64KB in size. */ pcr_write32(PID_DMI, PCR_DMI_PMBASEA, - ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | - (PCH_PWRM_BASE_ADDRESS >> 16))); + ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); else @@ -116,10 +113,7 @@ { uint32_t dmi_control; - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ + /* This cycle decoding is only allowed to set when DMICTL.SRLOCK is 0. */ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); if (dmi_control & PCR_DMI_DMICTL_SRLOCK) return -1; @@ -128,8 +122,7 @@ void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) @@ -152,19 +145,13 @@ void pch_early_init(void) { - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, - * GPE0_STS, GPE0_EN registers. - */ + /* Enable ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, GPE0_STS, GPE0_EN registers. */ soc_config_acpibase(); - /* - * Enabling PWRM Base for accessing - * Global Reset Cause Register. - */ + /* Enable PWRM Base for accessing Global Reset Cause Register. */ soc_config_pwrmbase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); /* Program SMBUS_BASE_ADDRESS and Enable it */ diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 1e65d9a..c7c1c5e 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -94,12 +94,9 @@ { PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM, "Kabylake-U Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, "Kabylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU, "Kabylake Super Sku" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, - "Kabylake-Y iHDCP 2.2 Premium" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, - "Kabylake-U iHDCP 2.2 Premium" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22, - "Kabylake-U iHDCP 2.2 Base" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, "Kabylake-U iHDCP 2.2 Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22, "Kabylake-U iHDCP 2.2 Base" }, }; static struct { @@ -181,8 +178,7 @@ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; - printk(BIOS_DEBUG, - "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); } @@ -269,8 +265,7 @@ for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); printk(BIOS_DEBUG, " rank interleave %s\n", diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a7d5872..3a6decd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -100,18 +100,12 @@ sizeof(params->SerialIoDevMode)); for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -119,8 +113,7 @@ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; } if (config->usb3_ports[i].tx_downscale_amp) { params->Usb3HsioTxDownscaleAmpEnable[i] = 1; @@ -129,14 +122,12 @@ } } - memcpy(params->PcieRpEnable, config->PcieRpEnable, - sizeof(params->PcieRpEnable)); + memcpy(params->PcieRpEnable, config->PcieRpEnable, sizeof(params->PcieRpEnable)); memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); params->EnableLan = config->EnableLan; params->Cio2Enable = config->Cio2Enable; @@ -178,10 +169,8 @@ if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - params->WakeConfigWolEnableOverride = - config->WakeConfigWolEnableOverride; - params->WakeConfigPcieWakeFromDeepSx = - config->WakeConfigPcieWakeFromDeepSx; + params->WakeConfigWolEnableOverride = config->WakeConfigWolEnableOverride; + params->WakeConfigPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PmConfigDeepSxPol = config->PmConfigDeepSxPol; params->PmConfigSlpS3MinAssert = config->PmConfigSlpS3MinAssert; params->PmConfigSlpS4MinAssert = config->PmConfigSlpS4MinAssert; @@ -189,14 +178,11 @@ params->PmConfigSlpAMinAssert = config->PmConfigSlpAMinAssert; params->PmConfigPciClockRun = config->PmConfigPciClockRun; params->PmConfigSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PmConfigPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; + params->PmConfigPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PmConfigPwrCycDur = config->PmConfigPwrCycDur; params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF; - params->SerialIrqConfigSirqMode = - config->serirq_mode == SERIRQ_CONTINUOUS; - params->SerialIrqConfigStartFramePulse = - config->SerialIrqConfigStartFramePulse; + params->SerialIrqConfigSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; + params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; @@ -204,11 +190,9 @@ params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; /* - * To disable Heci, the Psf needs to be left unlocked - * by FSP after end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in Fsp, - * do the changes and then lock it back in coreboot - * + * To disable Heci, the Psf needs to be left unlocked by FSP after end of post + * sequence. Based on the devicetree setting, we set the appropriate PsfUnlock + * policy in Fsp, do the changes and then lock it back in coreboot. */ if (config->HeciEnabled == 0) params->PsfUnlock = 1; @@ -249,8 +233,8 @@ /* Display the parameters for SiliconInit */ printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); fsp_display_upd_value("LogoPtr", 4, - (uint32_t)original->LogoPtr, - (uint32_t)params->LogoPtr); + (uint32_t)original->LogoPtr, + (uint32_t)params->LogoPtr); fsp_display_upd_value("LogoSize", 4, (uint32_t)original->LogoSize, (uint32_t)params->LogoSize); @@ -266,8 +250,7 @@ fsp_display_upd_value("TurboMode", 1, (uint32_t)original->TurboMode, (uint32_t)params->TurboMode); - fsp_display_upd_value("Device4Enable", 1, - original->Device4Enable, + fsp_display_upd_value("Device4Enable", 1, original->Device4Enable, params->Device4Enable); fsp_display_upd_value("PcieRpEnable[0]", 1, original->PcieRpEnable[0], params->PcieRpEnable[0]); @@ -309,130 +292,89 @@ params->PcieRpEnable[18]); fsp_display_upd_value("PcieRpEnable[19]", 1, original->PcieRpEnable[19], params->PcieRpEnable[19]); - fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, - original->PcieRpClkReqSupport[0], + fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, original->PcieRpClkReqSupport[0], params->PcieRpClkReqSupport[0]); - fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, - original->PcieRpClkReqSupport[1], + fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, original->PcieRpClkReqSupport[1], params->PcieRpClkReqSupport[1]); - fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, - original->PcieRpClkReqSupport[2], + fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, original->PcieRpClkReqSupport[2], params->PcieRpClkReqSupport[2]); - fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, - original->PcieRpClkReqSupport[3], + fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, original->PcieRpClkReqSupport[3], params->PcieRpClkReqSupport[3]); - fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, - original->PcieRpClkReqSupport[4], + fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, original->PcieRpClkReqSupport[4], params->PcieRpClkReqSupport[4]); - fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, - original->PcieRpClkReqSupport[5], + fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, original->PcieRpClkReqSupport[5], params->PcieRpClkReqSupport[5]); - fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, - original->PcieRpClkReqSupport[6], + fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, original->PcieRpClkReqSupport[6], params->PcieRpClkReqSupport[6]); - fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, - original->PcieRpClkReqSupport[7], + fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, original->PcieRpClkReqSupport[7], params->PcieRpClkReqSupport[7]); - fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, - original->PcieRpClkReqSupport[8], + fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, original->PcieRpClkReqSupport[8], params->PcieRpClkReqSupport[8]); - fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, - original->PcieRpClkReqSupport[9], + fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, original->PcieRpClkReqSupport[9], params->PcieRpClkReqSupport[9]); - fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, - original->PcieRpClkReqSupport[10], + fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, original->PcieRpClkReqSupport[10], params->PcieRpClkReqSupport[10]); - fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, - original->PcieRpClkReqSupport[11], + fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, original->PcieRpClkReqSupport[11], params->PcieRpClkReqSupport[11]); - fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, - original->PcieRpClkReqSupport[12], + fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, original->PcieRpClkReqSupport[12], params->PcieRpClkReqSupport[12]); - fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, - original->PcieRpClkReqSupport[13], + fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, original->PcieRpClkReqSupport[13], params->PcieRpClkReqSupport[13]); - fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, - original->PcieRpClkReqSupport[14], + fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, original->PcieRpClkReqSupport[14], params->PcieRpClkReqSupport[14]); - fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, - original->PcieRpClkReqSupport[15], + fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, original->PcieRpClkReqSupport[15], params->PcieRpClkReqSupport[15]); - fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, - original->PcieRpClkReqSupport[16], + fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, original->PcieRpClkReqSupport[16], params->PcieRpClkReqSupport[16]); - fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, - original->PcieRpClkReqSupport[17], + fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, original->PcieRpClkReqSupport[17], params->PcieRpClkReqSupport[17]); - fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, - original->PcieRpClkReqSupport[18], + fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, original->PcieRpClkReqSupport[18], params->PcieRpClkReqSupport[18]); - fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, - original->PcieRpClkReqSupport[19], + fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, original->PcieRpClkReqSupport[19], params->PcieRpClkReqSupport[19]); - fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, - original->PcieRpClkReqNumber[0], + fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, original->PcieRpClkReqNumber[0], params->PcieRpClkReqNumber[0]); - fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, - original->PcieRpClkReqNumber[1], + fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, original->PcieRpClkReqNumber[1], params->PcieRpClkReqNumber[1]); - fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, - original->PcieRpClkReqNumber[2], + fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, original->PcieRpClkReqNumber[2], params->PcieRpClkReqNumber[2]); - fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, - original->PcieRpClkReqNumber[3], + fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, original->PcieRpClkReqNumber[3], params->PcieRpClkReqNumber[3]); - fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, - original->PcieRpClkReqNumber[4], + fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, original->PcieRpClkReqNumber[4], params->PcieRpClkReqNumber[4]); - fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, - original->PcieRpClkReqNumber[5], + fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, original->PcieRpClkReqNumber[5], params->PcieRpClkReqNumber[5]); - fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, - original->PcieRpClkReqNumber[6], + fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, original->PcieRpClkReqNumber[6], params->PcieRpClkReqNumber[6]); - fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, - original->PcieRpClkReqNumber[7], + fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, original->PcieRpClkReqNumber[7], params->PcieRpClkReqNumber[7]); - fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, - original->PcieRpClkReqNumber[8], + fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, original->PcieRpClkReqNumber[8], params->PcieRpClkReqNumber[8]); - fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, - original->PcieRpClkReqNumber[9], + fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, original->PcieRpClkReqNumber[9], params->PcieRpClkReqNumber[9]); - fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, - original->PcieRpClkReqNumber[10], + fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, original->PcieRpClkReqNumber[10], params->PcieRpClkReqNumber[10]); - fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, - original->PcieRpClkReqNumber[11], + fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, original->PcieRpClkReqNumber[11], params->PcieRpClkReqNumber[11]); - fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, - original->PcieRpClkReqNumber[12], + fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, original->PcieRpClkReqNumber[12], params->PcieRpClkReqNumber[12]); - fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, - original->PcieRpClkReqNumber[13], + fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, original->PcieRpClkReqNumber[13], params->PcieRpClkReqNumber[13]); - fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, - original->PcieRpClkReqNumber[14], + fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, original->PcieRpClkReqNumber[14], params->PcieRpClkReqNumber[14]); - fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, - original->PcieRpClkReqNumber[15], + fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, original->PcieRpClkReqNumber[15], params->PcieRpClkReqNumber[15]); - fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, - original->PcieRpClkReqNumber[16], + fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, original->PcieRpClkReqNumber[16], params->PcieRpClkReqNumber[16]); - fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, - original->PcieRpClkReqNumber[17], + fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, original->PcieRpClkReqNumber[17], params->PcieRpClkReqNumber[17]); - fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, - original->PcieRpClkReqNumber[18], + fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, original->PcieRpClkReqNumber[18], params->PcieRpClkReqNumber[18]); - fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, - original->PcieRpClkReqNumber[19], + fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, original->PcieRpClkReqNumber[19], params->PcieRpClkReqNumber[19]); - fsp_display_upd_value("EnableLan", 1, original->EnableLan, - params->EnableLan); - fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, - params->Cio2Enable); + + fsp_display_upd_value("EnableLan", 1, original->EnableLan, params->EnableLan); + fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, params->Cio2Enable); fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport, params->SataSalpSupport); fsp_display_upd_value("SataPortsEnable[0]", 1, @@ -467,10 +409,8 @@ original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]); fsp_display_upd_value("SataPortsDevSlp[7]", 1, original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]); - fsp_display_upd_value("EnableAzalia", 1, - original->EnableAzalia, params->EnableAzalia); - fsp_display_upd_value("DspEnable", 1, original->DspEnable, - params->DspEnable); + fsp_display_upd_value("EnableAzalia", 1, original->EnableAzalia, params->EnableAzalia); + fsp_display_upd_value("DspEnable", 1, original->DspEnable, params->DspEnable); fsp_display_upd_value("IoBufferOwnership", 1, original->IoBufferOwnership, params->IoBufferOwnership); fsp_display_upd_value("PortUsb20Enable[0]", 1, @@ -525,12 +465,10 @@ original->PortUsb30Enable[8], params->PortUsb30Enable[8]); fsp_display_upd_value("PortUsb30Enable[9]", 1, original->PortUsb30Enable[9], params->PortUsb30Enable[9]); - fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, - params->XdciEnable); - fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable, - params->SsicPortEnable); - fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, - params->SmbusEnable); + fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, params->XdciEnable); + fsp_display_upd_value("SsicPortEnable", 1, + original->SsicPortEnable, params->SsicPortEnable); + fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, params->SmbusEnable); fsp_display_upd_value("SerialIoDevMode[0]", 1, original->SerialIoDevMode[0], params->SerialIoDevMode[0]); fsp_display_upd_value("SerialIoDevMode[1]", 1, @@ -559,10 +497,9 @@ original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled); fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled, params->ScsSdCardEnabled); - fsp_display_upd_value("IshEnable", 1, original->IshEnable, - params->IshEnable); - fsp_display_upd_value("ShowSpiController", 1, - original->ShowSpiController, params->ShowSpiController); + fsp_display_upd_value("IshEnable", 1, original->IshEnable, params->IshEnable); + fsp_display_upd_value("ShowSpiController", 1, original->ShowSpiController, + params->ShowSpiController); fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging, params->HsioMessaging); fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled, @@ -571,45 +508,28 @@ params->EnableSata); fsp_display_upd_value("SataMode", 1, original->SataMode, params->SataMode); - fsp_display_upd_value("NumOfDevIntConfig", 1, - original->NumOfDevIntConfig, + fsp_display_upd_value("NumOfDevIntConfig", 1, original->NumOfDevIntConfig, params->NumOfDevIntConfig); - fsp_display_upd_value("PxRcConfig[PARC]", 1, - original->PxRcConfig[PCH_PARC], + fsp_display_upd_value("PxRcConfig[PARC]", 1, original->PxRcConfig[PCH_PARC], params->PxRcConfig[PCH_PARC]); - fsp_display_upd_value("PxRcConfig[PBRC]", 1, - original->PxRcConfig[PCH_PBRC], + fsp_display_upd_value("PxRcConfig[PBRC]", 1, original->PxRcConfig[PCH_PBRC], params->PxRcConfig[PCH_PBRC]); - fsp_display_upd_value("PxRcConfig[PCRC]", 1, - original->PxRcConfig[PCH_PCRC], + fsp_display_upd_value("PxRcConfig[PCRC]", 1, original->PxRcConfig[PCH_PCRC], params->PxRcConfig[PCH_PCRC]); - fsp_display_upd_value("PxRcConfig[PDRC]", 1, - original->PxRcConfig[PCH_PDRC], + fsp_display_upd_value("PxRcConfig[PDRC]", 1, original->PxRcConfig[PCH_PDRC], params->PxRcConfig[PCH_PDRC]); - fsp_display_upd_value("PxRcConfig[PERC]", 1, - original->PxRcConfig[PCH_PERC], + fsp_display_upd_value("PxRcConfig[PERC]", 1, original->PxRcConfig[PCH_PERC], params->PxRcConfig[PCH_PERC]); - fsp_display_upd_value("PxRcConfig[PFRC]", 1, - original->PxRcConfig[PCH_PFRC], + fsp_display_upd_value("PxRcConfig[PFRC]", 1, original->PxRcConfig[PCH_PFRC], params->PxRcConfig[PCH_PFRC]); - fsp_display_upd_value("PxRcConfig[PGRC]", 1, - original->PxRcConfig[PCH_PGRC], + fsp_display_upd_value("PxRcConfig[PGRC]", 1, original->PxRcConfig[PCH_PGRC], params->PxRcConfig[PCH_PGRC]); - fsp_display_upd_value("PxRcConfig[PHRC]", 1, - original->PxRcConfig[PCH_PHRC], + fsp_display_upd_value("PxRcConfig[PHRC]", 1, original->PxRcConfig[PCH_PHRC], params->PxRcConfig[PCH_PHRC]); - fsp_display_upd_value("GpioIrqRoute", 1, - original->GpioIrqRoute, - params->GpioIrqRoute); - fsp_display_upd_value("SciIrqSelect", 1, - original->SciIrqSelect, - params->SciIrqSelect); - fsp_display_upd_value("TcoIrqSelect", 1, - original->TcoIrqSelect, - params->TcoIrqSelect); - fsp_display_upd_value("TcoIrqEnable", 1, - original->TcoIrqEnable, - params->TcoIrqEnable); + fsp_display_upd_value("GpioIrqRoute", 1, original->GpioIrqRoute, params->GpioIrqRoute); + fsp_display_upd_value("SciIrqSelect", 1, original->SciIrqSelect, params->SciIrqSelect); + fsp_display_upd_value("TcoIrqSelect", 1, original->TcoIrqSelect, params->TcoIrqSelect); + fsp_display_upd_value("TcoIrqEnable", 1, original->TcoIrqEnable, params->TcoIrqEnable); fsp_display_upd_value("LockDownConfigGlobalSmi", 1, original->LockDownConfigGlobalSmi, params->LockDownConfigGlobalSmi); @@ -674,190 +594,127 @@ original->SerialIrqConfigStartFramePulse, params->SerialIrqConfigStartFramePulse); - fsp_display_upd_value("Psi1Threshold[0]", 1, - original->Psi1Threshold[0], + fsp_display_upd_value("Psi1Threshold[0]", 1, original->Psi1Threshold[0], params->Psi1Threshold[0]); - fsp_display_upd_value("Psi1Threshold[1]", 1, - original->Psi1Threshold[1], + fsp_display_upd_value("Psi1Threshold[1]", 1, original->Psi1Threshold[1], params->Psi1Threshold[1]); - fsp_display_upd_value("Psi1Threshold[2]", 1, - original->Psi1Threshold[2], + fsp_display_upd_value("Psi1Threshold[2]", 1, original->Psi1Threshold[2], params->Psi1Threshold[2]); - fsp_display_upd_value("Psi1Threshold[3]", 1, - original->Psi1Threshold[3], + fsp_display_upd_value("Psi1Threshold[3]", 1, original->Psi1Threshold[3], params->Psi1Threshold[3]); - fsp_display_upd_value("Psi1Threshold[4]", 1, - original->Psi1Threshold[4], + fsp_display_upd_value("Psi1Threshold[4]", 1, original->Psi1Threshold[4], params->Psi1Threshold[4]); - fsp_display_upd_value("Psi2Threshold[0]", 1, - original->Psi2Threshold[0], + fsp_display_upd_value("Psi2Threshold[0]", 1, original->Psi2Threshold[0], params->Psi2Threshold[0]); - fsp_display_upd_value("Psi2Threshold[1]", 1, - original->Psi2Threshold[1], + fsp_display_upd_value("Psi2Threshold[1]", 1, original->Psi2Threshold[1], params->Psi2Threshold[1]); - fsp_display_upd_value("Psi2Threshold[2]", 1, - original->Psi2Threshold[2], + fsp_display_upd_value("Psi2Threshold[2]", 1, original->Psi2Threshold[2], params->Psi2Threshold[2]); - fsp_display_upd_value("Psi2Threshold[3]", 1, - original->Psi2Threshold[3], + fsp_display_upd_value("Psi2Threshold[3]", 1, original->Psi2Threshold[3], params->Psi2Threshold[3]); - fsp_display_upd_value("Psi2Threshold[4]", 1, - original->Psi2Threshold[4], + fsp_display_upd_value("Psi2Threshold[4]", 1, original->Psi2Threshold[4], params->Psi2Threshold[4]); - fsp_display_upd_value("Psi3Threshold[0]", 1, - original->Psi3Threshold[0], + fsp_display_upd_value("Psi3Threshold[0]", 1, original->Psi3Threshold[0], params->Psi3Threshold[0]); - fsp_display_upd_value("Psi3Threshold[1]", 1, - original->Psi3Threshold[1], + fsp_display_upd_value("Psi3Threshold[1]", 1, original->Psi3Threshold[1], params->Psi3Threshold[1]); - fsp_display_upd_value("Psi3Threshold[2]", 1, - original->Psi3Threshold[2], + fsp_display_upd_value("Psi3Threshold[2]", 1, original->Psi3Threshold[2], params->Psi3Threshold[2]); - fsp_display_upd_value("Psi3Threshold[3]", 1, - original->Psi3Threshold[3], + fsp_display_upd_value("Psi3Threshold[3]", 1, original->Psi3Threshold[3], params->Psi3Threshold[3]); - fsp_display_upd_value("Psi3Threshold[4]", 1, - original->Psi3Threshold[4], + fsp_display_upd_value("Psi3Threshold[4]", 1, original->Psi3Threshold[4], params->Psi3Threshold[4]); - fsp_display_upd_value("Psi3Enable[0]", 1, - original->Psi3Enable[0], + fsp_display_upd_value("Psi3Enable[0]", 1, original->Psi3Enable[0], params->Psi3Enable[0]); - fsp_display_upd_value("Psi3Enable[1]", 1, - original->Psi3Enable[1], + fsp_display_upd_value("Psi3Enable[1]", 1, original->Psi3Enable[1], params->Psi3Enable[1]); - fsp_display_upd_value("Psi3Enable[2]", 1, - original->Psi3Enable[2], + fsp_display_upd_value("Psi3Enable[2]", 1, original->Psi3Enable[2], params->Psi3Enable[2]); - fsp_display_upd_value("Psi3Enable[3]", 1, - original->Psi3Enable[3], + fsp_display_upd_value("Psi3Enable[3]", 1, original->Psi3Enable[3], params->Psi3Enable[3]); - fsp_display_upd_value("Psi3Enable[4]", 1, - original->Psi3Enable[4], + fsp_display_upd_value("Psi3Enable[4]", 1, original->Psi3Enable[4], params->Psi3Enable[4]); - fsp_display_upd_value("Psi4Enable[0]", 1, - original->Psi4Enable[0], + fsp_display_upd_value("Psi4Enable[0]", 1, original->Psi4Enable[0], params->Psi4Enable[0]); - fsp_display_upd_value("Psi4Enable[1]", 1, - original->Psi4Enable[1], + fsp_display_upd_value("Psi4Enable[1]", 1, original->Psi4Enable[1], params->Psi4Enable[1]); - fsp_display_upd_value("Psi4Enable[2]", 1, - original->Psi4Enable[2], + fsp_display_upd_value("Psi4Enable[2]", 1, original->Psi4Enable[2], params->Psi4Enable[2]); - fsp_display_upd_value("Psi4Enable[3]", 1, - original->Psi4Enable[3], + fsp_display_upd_value("Psi4Enable[3]", 1, original->Psi4Enable[3], params->Psi4Enable[3]); - fsp_display_upd_value("Psi4Enable[4]", 1, - original->Psi4Enable[4], + fsp_display_upd_value("Psi4Enable[4]", 1, original->Psi4Enable[4], params->Psi4Enable[4]); - fsp_display_upd_value("ImonSlope[0]", 1, - original->ImonSlope[0], + fsp_display_upd_value("ImonSlope[0]", 1, original->ImonSlope[0], params->ImonSlope[0]); - fsp_display_upd_value("ImonSlope[1]", 1, - original->ImonSlope[1], + fsp_display_upd_value("ImonSlope[1]", 1, original->ImonSlope[1], params->ImonSlope[1]); - fsp_display_upd_value("ImonSlope[2]", 1, - original->ImonSlope[2], + fsp_display_upd_value("ImonSlope[2]", 1, original->ImonSlope[2], params->ImonSlope[2]); - fsp_display_upd_value("ImonSlope[3]", 1, - original->ImonSlope[3], + fsp_display_upd_value("ImonSlope[3]", 1, original->ImonSlope[3], params->ImonSlope[3]); - fsp_display_upd_value("ImonSlope[4]", 1, - original->ImonSlope[4], + fsp_display_upd_value("ImonSlope[4]", 1, original->ImonSlope[4], params->ImonSlope[4]); - fsp_display_upd_value("ImonOffse[0]t", 1, - original->ImonOffset[0], + fsp_display_upd_value("ImonOffse[0]t", 1, original->ImonOffset[0], params->ImonOffset[0]); - fsp_display_upd_value("ImonOffse[1]t", 1, - original->ImonOffset[1], + fsp_display_upd_value("ImonOffse[1]t", 1, original->ImonOffset[1], params->ImonOffset[1]); - fsp_display_upd_value("ImonOffse[2]t", 1, - original->ImonOffset[2], + fsp_display_upd_value("ImonOffse[2]t", 1, original->ImonOffset[2], params->ImonOffset[2]); - fsp_display_upd_value("ImonOffse[3]t", 1, - original->ImonOffset[3], + fsp_display_upd_value("ImonOffse[3]t", 1, original->ImonOffset[3], params->ImonOffset[3]); - fsp_display_upd_value("ImonOffse[4]t", 1, - original->ImonOffset[4], + fsp_display_upd_value("ImonOffse[4]t", 1, original->ImonOffset[4], params->ImonOffset[4]); - fsp_display_upd_value("IccMax[0]", 1, - original->IccMax[0], + fsp_display_upd_value("IccMax[0]", 1, original->IccMax[0], params->IccMax[0]); - fsp_display_upd_value("IccMax[1]", 1, - original->IccMax[1], + fsp_display_upd_value("IccMax[1]", 1, original->IccMax[1], params->IccMax[1]); - fsp_display_upd_value("IccMax[2]", 1, - original->IccMax[2], + fsp_display_upd_value("IccMax[2]", 1, original->IccMax[2], params->IccMax[2]); - fsp_display_upd_value("IccMax[3]", 1, - original->IccMax[3], + fsp_display_upd_value("IccMax[3]", 1, original->IccMax[3], params->IccMax[3]); - fsp_display_upd_value("IccMax[4]", 1, - original->IccMax[4], + fsp_display_upd_value("IccMax[4]", 1, original->IccMax[4], params->IccMax[4]); - fsp_display_upd_value("VrVoltageLimit[0]", 1, - original->VrVoltageLimit[0], + fsp_display_upd_value("VrVoltageLimit[0]", 1, original->VrVoltageLimit[0], params->VrVoltageLimit[0]); - fsp_display_upd_value("VrVoltageLimit[1]", 1, - original->VrVoltageLimit[1], + fsp_display_upd_value("VrVoltageLimit[1]", 1, original->VrVoltageLimit[1], params->VrVoltageLimit[1]); - fsp_display_upd_value("VrVoltageLimit[2]", 1, - original->VrVoltageLimit[2], + fsp_display_upd_value("VrVoltageLimit[2]", 1, original->VrVoltageLimit[2], params->VrVoltageLimit[2]); - fsp_display_upd_value("VrVoltageLimit[3]", 1, - original->VrVoltageLimit[3], + fsp_display_upd_value("VrVoltageLimit[3]", 1, original->VrVoltageLimit[3], params->VrVoltageLimit[3]); - fsp_display_upd_value("VrVoltageLimit[4]", 1, - original->VrVoltageLimit[4], + fsp_display_upd_value("VrVoltageLimit[4]", 1, original->VrVoltageLimit[4], params->VrVoltageLimit[4]); - fsp_display_upd_value("VrConfigEnable[0]", 1, - original->VrConfigEnable[0], + fsp_display_upd_value("VrConfigEnable[0]", 1, original->VrConfigEnable[0], params->VrConfigEnable[0]); - fsp_display_upd_value("VrConfigEnable[1]", 1, - original->VrConfigEnable[1], + fsp_display_upd_value("VrConfigEnable[1]", 1, original->VrConfigEnable[1], params->VrConfigEnable[1]); - fsp_display_upd_value("VrConfigEnable[2]", 1, - original->VrConfigEnable[2], + fsp_display_upd_value("VrConfigEnable[2]", 1, original->VrConfigEnable[2], params->VrConfigEnable[2]); - fsp_display_upd_value("VrConfigEnable[3]", 1, - original->VrConfigEnable[3], + fsp_display_upd_value("VrConfigEnable[3]", 1, original->VrConfigEnable[3], params->VrConfigEnable[3]); - fsp_display_upd_value("VrConfigEnable[4]", 1, - original->VrConfigEnable[4], + fsp_display_upd_value("VrConfigEnable[4]", 1, original->VrConfigEnable[4], params->VrConfigEnable[4]); - fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, - original->SerialIoI2cVoltage[0], + fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, original->SerialIoI2cVoltage[0], params->SerialIoI2cVoltage[0]); - fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, - original->SerialIoI2cVoltage[1], + fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, original->SerialIoI2cVoltage[1], params->SerialIoI2cVoltage[1]); - fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, - original->SerialIoI2cVoltage[2], + fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, original->SerialIoI2cVoltage[2], params->SerialIoI2cVoltage[2]); - fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, - original->SerialIoI2cVoltage[3], + fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, original->SerialIoI2cVoltage[3], params->SerialIoI2cVoltage[3]); - fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, - original->SerialIoI2cVoltage[4], + fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, original->SerialIoI2cVoltage[4], params->SerialIoI2cVoltage[4]); - fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, - original->SerialIoI2cVoltage[5], + fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, original->SerialIoI2cVoltage[5], params->SerialIoI2cVoltage[5]); - fsp_display_upd_value("SendVrMbxCmd", 1, - original->SendVrMbxCmd, - params->SendVrMbxCmd); - fsp_display_upd_value("AcousticNoiseMitigation", 1, - original->AcousticNoiseMitigation, + fsp_display_upd_value("SendVrMbxCmd", 1, original->SendVrMbxCmd, params->SendVrMbxCmd); + fsp_display_upd_value("AcousticNoiseMitigation", 1, original->AcousticNoiseMitigation, params->AcousticNoiseMitigation); - fsp_display_upd_value("SlowSlewRateForIa", 1, - original->SlowSlewRateForIa, + fsp_display_upd_value("SlowSlewRateForIa", 1, original->SlowSlewRateForIa, params->SlowSlewRateForIa); - fsp_display_upd_value("SlowSlewRateForGt", 1, - original->SlowSlewRateForGt, + fsp_display_upd_value("SlowSlewRateForGt", 1, original->SlowSlewRateForGt, params->SlowSlewRateForGt); - fsp_display_upd_value("SlowSlewRateForSa", 1, - original->SlowSlewRateForSa, + fsp_display_upd_value("SlowSlewRateForSa", 1, original->SlowSlewRateForSa, params->SlowSlewRateForSa); - fsp_display_upd_value("FastPkgCRampDisable", 1, - original->FastPkgCRampDisable, + fsp_display_upd_value("FastPkgCRampDisable", 1, original->FastPkgCRampDisable, params->FastPkgCRampDisable); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1313dc1..1dbe590 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -142,8 +142,7 @@ /* * The following fields come from FspUpdVpd.h. - * These are configuration values that are passed to FSP during - * MemoryInit. + * These are configuration values that are passed to FSP during MemoryInit. */ u64 PlatformMemorySize; u8 SmramMask; @@ -191,9 +190,8 @@ /* SATA related */ u8 EnableSata; enum { - /* Documentation and header files of Skylake FSP disagree on - the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses - these: */ + /* Documentation and header files of Skylake FSP disagree on the values, + * Kaby Lake FSP (KabylakeFsp0001 on github) uses these: */ KBLFSP_SATA_MODE_AHCI = 0, KBLFSP_SATA_MODE_RAID = 1, } SataMode; @@ -224,8 +222,7 @@ /* * Pcie Root Port configuration: - * each element of array corresponds to - * respective PCIe root port. + * each element of array corresponds to respective PCIe root port. */ /* PEG Max Link Width */ @@ -361,8 +358,7 @@ /* * The following fields come from fsp_vpd.h - * These are configuration values that are passed to FSP during - * SiliconInit. + * These are configuration values that are passed to FSP during SiliconInit. */ u32 LogoPtr; u32 LogoSize; @@ -446,8 +442,7 @@ */ u8 PmConfigPciClockRun; /* - * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, - * 1: Enabled + * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled */ u8 PmConfigSlpStrchSusUp; /* @@ -481,8 +476,7 @@ /* * VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; /* diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..87bf644 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -86,14 +86,11 @@ }; /* - * If the PCIe root port at function 0 is disabled, - * the PCIe root ports might be coalesced after FSP silicon init. - * The below function will swap the devfn of the first enabled device - * in devicetree and function 0 resides a pci device - * so that it won't confuse coreboot. + * If the PCIe root port at function 0 is disabled, the PCIe root ports might be coalesced + * after FSP silicon init. The below function will swap the devfn of the first enabled device + * in devicetree and function 0 resides a pci device so that it won't confuse coreboot. */ -static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, - size_t pci_groups) +static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, size_t pci_groups) { struct device *func0; unsigned int devfn, devfn0; @@ -117,18 +114,13 @@ * Then find first enabled device to replace func0 * as that port was move to func0. */ - for (i = 1; i < pcie_rp_group[group].func_count; - i++, devfn += inc) { + for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) { struct device *dev = pcidev_path_on_root(devfn); if (dev == NULL || !dev->enabled) continue; - /* - * Found the first enabled device in - * a given dev number. - */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); + /* Found the first enabled device in a given dev number. */ + printk(BIOS_INFO, "PCI func %d was swapped to func 0.\n", i); func0->path.pci.devfn = dev->path.pci.devfn; dev->path.pci.devfn = devfn0; break; @@ -160,8 +152,7 @@ pcie_update_device_tree(&pcie_table_skl_pch_h[0], ARRAY_SIZE(pcie_table_skl_pch_h)); } else { - printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" - " is not found\n", id); + printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x is not found\n", id); return; } } @@ -250,18 +241,12 @@ params->GraphicsConfigPtr = (u32) vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -269,8 +254,7 @@ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; } if (config->usb3_ports[i].tx_downscale_amp) { params->Usb3HsioTxDownscaleAmpEnable[i] = 1; @@ -287,23 +271,20 @@ sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpAdvancedErrorReporting, - config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, + sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); /* - * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for - * all the enabled PCIe root ports, invalid(0x1F) is set for - * disabled PCIe root ports. + * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for all the enabled + * PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. */ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { if (config->PcieRpClkReqSupport[i]) - params->PcieRpClkSrcNumber[i] = - config->PcieRpClkSrcNumber[i]; + params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i]; else params->PcieRpClkSrcNumber[i] = 0x1F; } @@ -344,12 +325,9 @@ params->ScsSdCardEnabled = config->ScsSdCardEnabled; if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { - params->PchScsEmmcHs400DllDataValid = - !!config->EmmcHs400DllNeed; - params->PchScsEmmcHs400RxStrobeDll1 = - config->ScsEmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = - config->ScsEmmcHs400TxDataDll; + params->PchScsEmmcHs400DllDataValid = !!config->EmmcHs400DllNeed; + params->PchScsEmmcHs400RxStrobeDll1 = config->ScsEmmcHs400RxStrobeDll1; + params->PchScsEmmcHs400TxDataDll = config->ScsEmmcHs400TxDataDll; } /* If ISH is enabled, enable ISH elements */ @@ -373,9 +351,8 @@ tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; /* - * To disable HECI, the Psf needs to be left unlocked - * by FSP till end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in FSP, + * To disable HECI, the Psf needs to be left unlocked by FSP till end of post sequence. + * Based on the devicetree setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; @@ -384,7 +361,7 @@ params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; /* - * Skip Spi Flash Lockdown from inside FSP. + * Skip SPI Flash Lockdown from inside FSP. * Making this config "0" means FSP won't set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). * So, it becomes coreboot's responsibility to set this bit @@ -413,8 +390,7 @@ params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; params->PchPmLpcClockRun = config->PmConfigPciClockRun; params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PchPmPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; /* Indicate whether platform supports Voltage Margining */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..c551df8 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -151,8 +151,7 @@ /* Set long term power limit to TDP */ limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); + tdp_pl1 = ((conf->tdp_pl1_override == 0) ? tdp : (conf->tdp_pl1_override * power_unit)); limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); /* Set PL1 Pkg Power clamp bit */ @@ -182,10 +181,8 @@ if (conf->tdp_psyspl2) { limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); limit.hi = 0; - printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", - conf->tdp_psyspl2); - limit.hi |= (conf->tdp_psyspl2 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", conf->tdp_psyspl2); + limit.hi |= (conf->tdp_psyspl2 * power_unit) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; @@ -196,20 +193,16 @@ if (conf->tdp_psyspl3) { limit = rdmsr(MSR_PL3_CONTROL); limit.lo = 0; - printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", - conf->tdp_psyspl3); - limit.lo |= (conf->tdp_psyspl3 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", conf->tdp_psyspl3); + limit.lo |= (conf->tdp_psyspl3 * power_unit) & PKG_POWER_LIMIT_MASK; /* Enable PsysPl3 */ limit.lo |= PKG_POWER_LIMIT_EN; /* set PsysPl3 time window */ limit.lo |= (conf->tdp_psyspl3_time & - PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; + PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; /* set PsysPl3 duty cycle */ limit.lo |= (conf->tdp_psyspl3_dutycycle & - PKG_POWER_LIMIT_DUTYCYCLE_MASK) << - PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; + PKG_POWER_LIMIT_DUTYCYCLE_MASK) << PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; wrmsr(MSR_PL3_CONTROL, limit); } @@ -217,10 +210,8 @@ if (conf->tdp_pl4) { limit = rdmsr(MSR_VR_CURRENT_CONFIG); limit.lo = 0; - printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", - conf->tdp_pl4); - limit.lo |= (conf->tdp_pl4 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", conf->tdp_pl4); + limit.lo |= (conf->tdp_pl4 * power_unit) & PKG_POWER_LIMIT_MASK; wrmsr(MSR_VR_CURRENT_CONFIG, limit); } @@ -382,20 +373,17 @@ /* C-state Interrupt Response Latency Control 3 - package C8 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); /* C-state Interrupt Response Latency Control 4 - package C9 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); /* C-state Interrupt Response Latency Control 5 - package C10 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } @@ -410,8 +398,7 @@ /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; /* Set PM1 timer IO port and enable*/ @@ -424,9 +411,10 @@ void soc_core_init(struct device *cpu) { /* Clear out pending MCEs */ - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ + /* + * TODO(adurbin): This should only be done on a cold boot. Also, some of these + * banks are core vs package scope. For now every CPU clears every bank. + */ mca_configure(); /* Enable the local CPU apics */ @@ -481,10 +469,7 @@ /* Set Max Ratio */ cpu_set_max_ratio(); - /* - * Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ + /* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */ smm_southbridge_enable(GBL_EN); /* Lock down the SMRAM space. */ @@ -503,9 +488,8 @@ static const struct mp_ops mp_ops = { /* - * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, - * that are set prior to ramstage. - * Real MTRRs programming are being done after resource allocation. + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, that are set + * prior to ramstage. Real MTRRs programming are being done after resource allocation. */ .pre_mp_init = soc_fsp_load, .get_cpu_count = get_cpu_count, @@ -545,8 +529,7 @@ if (msr2.lo && (current_patch_id == new_patch_id - 1)) return 0; else - return (msr1.lo & PRMRR_SUPPORTED) && - (current_patch_id == new_patch_id - 1); + return (msr1.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } void cpu_lock_sgx_memory(void) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137..2bf9c52 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -52,19 +52,13 @@ #define PME_STS_BIT (1 << 15) #ifdef __SIMPLE_DEVICE__ -static void pch_log_add_elog_event(const struct pme_status_info *info, - pci_devfn_t dev) +static void pch_log_add_elog_event(const struct pme_status_info *info, pci_devfn_t dev) #else -static void pch_log_add_elog_event(const struct pme_status_info *info, - struct device *dev) +static void pch_log_add_elog_event(const struct pme_status_info *info, struct device *dev) #endif { - /* - * If wake source is XHCI, check for detailed wake source events on - * USB2/3 ports. - */ - if ((info->dev == PCH_DEV_XHCI) && - pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + /* If wake source is XHCI, check for detailed wake source events on USB2/3 ports. */ + if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return; elog_add_event_wake(info->elog_event, 0); @@ -105,11 +99,10 @@ } /* - * If device is still not found, but the wake source is internal PME, - * try probing XHCI ports to see if any of the USB2/3 ports indicate - * that it was the wake source. This path would be taken in case of GSMI - * logging with S0ix where the pci_pm_resume_noirq runs and clears the - * PME_STS_BIT in controller register. + * If device is still not found, but the wake source is internal PME, try probing XHCI + * ports to see if any of the USB2/3 ports indicate that it was the wake source. This + * path would be taken in case of GSMI logging with S0ix where the pci_pm_resume_noirq + * runs and clears the PME_STS_BIT in controller register. */ if (!dev_found) dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); @@ -155,10 +148,7 @@ if ((val == 0xFFFFFFFF) || !(val & RP_PME_STS_BIT)) continue; - /* - * Linux kernel uses PME STS bit information. So do not clear - * this bit. - */ + /* Linux kernel uses PME STS bit information. So do not clear this bit. */ pch_log_add_elog_event(&pme_status_info[i], dev); } } @@ -234,8 +224,7 @@ } /* TCO Timeout */ - if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + if (ps->prev_sleep_state != ACPI_S3 && ps->tco2_sts & TCO_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ @@ -253,11 +242,9 @@ /* ACPI Wake Event */ if (ps->prev_sleep_state != ACPI_S0) { if (deep_sx) - elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, - ps->prev_sleep_state); + elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, ps->prev_sleep_state); else - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - ps->prev_sleep_state); + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); } } diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8afaf4d..633c347 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -79,8 +79,7 @@ config = config_of(dev); /* - * Set low maximum temp value used for dynamic thermal sensor - * shutdown consideration. + * Set low maximum temp value used for dynamic thermal sensor shutdown consideration. * * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index a4c3726..b5d5e33 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -23,12 +23,9 @@ .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, - .CodeRegionBase = - (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .MicrocodeRegionBase = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionSize = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, }, }; diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..3a211ac 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -176,17 +176,14 @@ return routes; } -uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, - int dw_reg, uint32_t reg_val) +uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { if (CONFIG(SKYLAKE_SOC_PCH_H)) return reg_val; - /* - * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 - * ~ GPP_F11. - */ + + /* For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 ~ GPP_F11. */ if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1) reg_val = reg_val & ~(PAD_CFG1_TOL_1V8); - return reg_val; + return reg_val; } diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c06893e..fae6469 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -63,11 +63,10 @@ write32(base + PCH_PP_DIVISOR, reg32); /* So far all devices seem to use the PCH PWM function. - The CPU PWM registers are all zero after reset. */ + The CPU PWM registers are all zero after reset. */ if (conf->gpu_pch_backlight_pwm_hz) { - /* Reference clock is 24MHz. We can choose either a 16 - or a 128 step increment. Use 16 if we would have less - than 100 steps otherwise. */ + /* Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. + * Use 16 if we would have less than 100 steps otherwise. */ const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; unsigned int pwm_increment, pwm_period; u32 south_chicken1; @@ -82,15 +81,12 @@ } write32(base + SOUTH_CHICKEN1, south_chicken1); - pwm_period = 24 * 1000 * 1000 / pwm_increment - / conf->gpu_pch_backlight_pwm_hz; + pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; /* Start with a 50% duty cycle. */ - write32(base + BLC_PWM_PCH_CTL2, - pwm_period << 16 | pwm_period / 2); + write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); write32(base + BLC_PWM_PCH_CTL1, - !!conf->gpu_pch_backlight_polarity << 29 | - BLM_PCH_PWM_ENABLE); + !!conf->gpu_pch_backlight_polarity << 29 | BLM_PCH_PWM_ENABLE); } } @@ -101,9 +97,8 @@ graphics_setup_panel(dev); /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver does not execute. + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. This will allow the + * kernel to use 4-lane eDP links properly if the VBIOS or GOP driver does not execute. */ ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { @@ -117,12 +112,9 @@ pci_write_config32(dev, PCI_COMMAND, reg32); /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. + * GFX PEIM module inside FSP binary is taking care of graphics initialization based on + * RUN_FSP_GOP Kconfig option and input VBT file. In case of non-FSP solution, SoC need + * to select another Kconfig to perform GFX initialization. */ if (CONFIG(RUN_FSP_GOP)) { /* nothing to do */ @@ -159,8 +151,8 @@ /* FIXME: Add platform specific mailbox initialization */ } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) +uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, + struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index c39c066..f883ee5 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -30,9 +30,9 @@ unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_mainboard_gnvs(global_nvs_t *gnvs); void southbridge_inject_dsdt(struct device *device); -unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); -unsigned long northbridge_write_acpi_tables(struct device *, - unsigned long current, struct acpi_rsdp *); +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, + struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long current, + struct acpi_rsdp *rsdp); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 0681f78..7455999 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -42,8 +42,7 @@ /* Common Timer Copy (CTC) frequency - 24MHz. */ #define CTC_FREQ 24000000 -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 13a0a7a..3bfaba5 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -18,8 +18,8 @@ #define _SOC_GPIO_H_ #include <soc/gpio_defs.h> -#include <intelblocks/gpio.h> /* intelblocks/gpio.h depends on definitions in - soc/gpio_defs.h */ +/* intelblocks/gpio.h depends on definitions in soc/gpio_defs.h */ +#include <intelblocks/gpio.h> #define CROS_GPIO_DEVICE_NAME "INT344B:00" #endif diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..e012e3a 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -35,10 +35,8 @@ #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) #define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM3_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS)) + ((NUM_GPIO_COM0_GPI_REGS) + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) + (NUM_GPIO_COM2_GPI_REGS)) /* * IOxAPIC IRQs for the GPIOs @@ -220,9 +218,9 @@ /* Register defines. */ #define GPIO_MISCCFG 0x10 -#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 #define HOSTSW_OWN_REG_0 0xd0 #define PAD_CFG_BASE 0x400 #define GPI_INT_STS_0 0x100 diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c73d766..f1220de 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -22,8 +22,8 @@ /* * Memory-mapped I/O registers. */ -#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 -#define PCH_PRESERVED_BASE_SIZE 0x02000000 +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index a25e5ac..82de495 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -43,8 +43,8 @@ int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); /* - * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0 - * on error. + * Add nau88l25 headset codec on provided SSP link. + * Return 0 on succes, < 0 on error. */ int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink); @@ -72,8 +72,8 @@ int nhlt_soc_add_rt5514(struct nhlt *nhlt, int hwlink, int num_channels); /* - * Add rt5663 headset codec on provided SSP link. Return 0 on success, < 0 - * on error. + * Add rt5663 headset codec on provided SSP link. + * Return 0 on success, < 0 on error. */ int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink); @@ -84,8 +84,8 @@ int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink); /* - * Add da7219 headset codec on provided SSP link. Return 0 on success, < 0 - * on error. + * Add da7219 headset codec on provided SSP link. + * Return 0 on success, < 0 on error. */ int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 615edac..a220d8c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -145,8 +145,7 @@ * - on microcontroller writes (io 0x62/0x66) * - on TCO events */ -#define ENABLE_SMI_PARAMS \ - (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) +#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) /* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ #define ETR 0xac diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 88ce9e3..96faace 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -30,9 +30,8 @@ msr_t smrr_base; msr_t smrr_mask; /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE + * The smm_save_state_in_msrs field indicates if SMM save state locations live in MSRs. + * This indicates to the CPUs how to adjust the SMMBASE and IEDBASE */ int smm_save_state_in_msrs; }; diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index aebbbdf..2fa6f9f 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -27,15 +27,10 @@ struct vr_config { - /* - * The below settings will take effect when this is set to 1 - * for that domain. - */ + /* The below settings will take effect when this is set to 1 for that domain. */ int vr_config_enable; - /* Power State X current cutoff in 1/4 Amp increments - * Range is 0-128A - */ + /* Power State X current cutoff in 1/4 Amp increments Range is 0-128A */ int psi1threshold; int psi2threshold; int psi3threshold; @@ -45,8 +40,8 @@ int psi4enable; /* - * Imon slope correction. Specified in 1/100 increment - * values. Range is 0-200. 125 = 1.25 + * Imon slope correction. Specified in 1/100 increment values. + * Range is 0-200. 125 = 1.25 */ int imon_slope; @@ -72,8 +67,7 @@ #if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced */ enum vr_domain { VR_SYSTEM_AGENT, @@ -85,8 +79,7 @@ }; #else /* VrConfig Settings for 4 domains - * 0 = System Agent, 1 = IA Core, - * 2 = GT unsliced, 3 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = GT unsliced, 3 = GT sliced */ enum vr_domain { VR_SYSTEM_AGENT, @@ -97,6 +90,5 @@ }; #endif -void fill_vr_domain_config(void *params, - int domain, const struct vr_config *cfg); +void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); #endif diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index ddaffda..8ce0f78 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -24,198 +24,143 @@ #include <string.h> static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { - /* - * cAVS(Audio, Voice, Speech), INTA is default, programmed in - * PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), - /* - * SMBus Controller, no default value, programmed in - * PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* cAVS(Audio, Voice, Speech), INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + + /* SMBus Controller, no default value, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), - /* - * SerialIo: UART #0, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[7] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), - /* - * SerialIo: UART #1, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[8] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), - /* - * SerialIo: SPI #0, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[10] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), - /* - * SerialIo: SPI #1, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[11] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + + /* SerialIo: UART #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[7] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART0), int_A, + LPSS_UART0_IRQ), + + /* SerialIo: UART #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[8] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART1), int_B, + LPSS_UART1_IRQ), + + /* SerialIo: SPI #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[10] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI0), int_C, + LPSS_SPI0_IRQ), + + /* SerialIo: SPI #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[11] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI1), int_D, + LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), - /* PCI Express Port, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), - /* - * PCI Express Port 1, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), - /* - * PCI Express Port 2, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), - /* - * PCI Express Port 3, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), - /* - * PCI Express Port 4, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), - /* - * PCI Express Port 5, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), - /* - * PCI Express Port 6, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), - /* - * PCI Express Port 7, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), - /* - * PCI Express Port 8, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + + /* PCI Express Port, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + + /* PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + + /* PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + + /* PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + + /* PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + + /* PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + + /* PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + + /* PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + + /* PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* * SerialIo UART Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[9] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), /* * SerialIo UART Controller #5, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[6] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), /* * SerialIo UART Controller #4, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[5] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), - /* - * SATA Controller, INTA is default, - * programmed in PciCfgSpace + 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, - PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + + /* SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + /* * SerialIo I2C Controller #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[1] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), /* * SerialIo I2C Controller #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[2] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), /* * SerialIo I2C Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[3] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), /* * SerialIo I2C Controller #3, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[4] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), - /* - * USB 3.0 xHCI Controller, no default value, - * programmed in PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + + /* USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + /* Camera IO Host Controller */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, - PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) }; void soc_irq_settings(FSP_SIL_UPD *params) @@ -229,9 +174,8 @@ /* Get Device Int Count */ intdeventry = ARRAY_SIZE(devintconfig); /* update irq table */ - memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) - (params->DevIntConfigPtr), devintconfig, intdeventry * - sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); + memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)(params->DevIntConfigPtr), + devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); params->NumOfDevIntConfig = intdeventry; /* PxRC to IRQ programming */ diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584..b838c5c 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -93,38 +93,22 @@ /* HFSTS2[27:24] Power Management Event */ static const char *const me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_CM0_CM3] = - "CM0->CM3", - [ME_HFS2_PMEVENT_CM3_CM0] = - "CM3->CM0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_CMX_CMOFF] = - "Cx/Mx->Cx/Moff", - [ME_HFS2_PMEVENT_CM0_CM0PG] = - "CM0->CM0PG", - [ME_HFS2_PMEVENT_CM3_CM3PG] = - "CM3->CM3PG", - [ME_HFS2_PMEVENT_CM0PG_CM0] = - "CM0PG->CM0" + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", + [ME_HFS2_PMEVENT_CM0_CM3] = "CM0->CM3", + [ME_HFS2_PMEVENT_CM3_CM0] = "CM3->CM0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_CMX_CMOFF] = "Cx/Mx->Cx/Moff", + [ME_HFS2_PMEVENT_CM0_CM0PG] = "CM0->CM0PG", + [ME_HFS2_PMEVENT_CM3_CM3PG] = "CM3->CM3PG", + [ME_HFS2_PMEVENT_CM0PG_CM0] = "CM0PG->CM0" }; @@ -136,70 +120,41 @@ /* Progress Code 1 states */ static const char *const me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_CG_ENABLE] = - "Enabling CG for cset", - [ME_HFS2_STATE_BUP_PM_HND_EN] = - "Enabling PM handshaking", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_PMC_PATCHING] = - "PMC Patching process", - [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = - "Get VSCC params", - [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = - "Set VSCC params", + [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event", + [ME_HFS2_STATE_BUP_CG_ENABLE] = "Enabling CG for cset", + [ME_HFS2_STATE_BUP_PM_HND_EN] = "Enabling PM handshaking", + [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process", + [ME_HFS2_STATE_BUP_PMC_PATCHING] = "PMC Patching process", + [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = "Get VSCC params", + [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = "Set VSCC params", [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_EFSS_INIT] = - "Initialize EFFS", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_STRAP_DIS] = - "EFFS says ME disabled", + "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_EFSS_INIT] = "Initialize EFFS", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_STRAP_DIS] = "EFFS says ME disabled", [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", + "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error", [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", + "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load", }; static void print_me_version(void *unused) @@ -258,8 +213,7 @@ */ heci_reset(); - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, - HECI_MKHI_ADD)) + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, HECI_MKHI_ADD)) goto failed; if (!heci_receive(&resp, &resp_size)) @@ -293,18 +247,14 @@ hfs3.data = me_read_config32(PCI_ME_HFSTS3); hfs6.data = me_read_config32(PCI_ME_HFSTS6); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", - hfs.data); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", - hfs2.data); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", - hfs3.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", hfs.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", hfs2.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", hfs3.data); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 4 : 0x%08X\n", me_read_config32(PCI_ME_HFSTS4)); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 5 : 0x%08X\n", me_read_config32(PCI_ME_HFSTS5)); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n", - hfs6.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n", hfs6.data); /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs.fields.fpt_bad ? "BAD" : "OK"); @@ -344,12 +294,10 @@ printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (hfs2.fields.progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ - if (hfs2.fields.current_state - < ARRAY_SIZE(me_progress_rom_values) + if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_rom_values) && me_progress_rom_values[hfs2.fields.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_rom_values[ - hfs2.fields.current_state]); + me_progress_rom_values[hfs2.fields.current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state); break; @@ -359,12 +307,10 @@ break; case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2.fields.current_state - < ARRAY_SIZE(me_progress_bup_values) + if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_bup_values) && me_progress_bup_values[hfs2.fields.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[ - hfs2.fields.current_state]); + me_progress_bup_values[hfs2.fields.current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state); break; @@ -417,8 +363,7 @@ printk(BIOS_DEBUG, "Corporate\n"); break; default: - printk(BIOS_DEBUG, "Unknown (0x%x)\n", - hfs3.fields.fw_sku); + printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3.fields.fw_sku); } } diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 4c3c58a..acd5e92 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -40,8 +40,7 @@ static bool is_ptt_enable(void) { - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) + if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == PTT_PRESENT) return true; return false; @@ -80,8 +79,7 @@ } /* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) +static size_t get_prmrr_size(uintptr_t dram_base, const struct soc_intel_skylake_config *config) { uintptr_t prmrr_base = dram_base; size_t prmrr_size; @@ -95,12 +93,10 @@ return 0; /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. + * PRMRR Sizes that are > 1MB and < 32MB are not supported and will fail out. */ if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); + die("PRMRR Sizes that are > 1MB and < 32MB are not supported!\n"); prmrr_base -= prmrr_size; if (prmrr_size >= 32*MiB) diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c index dd91435..7dd82fa 100644 --- a/src/soc/intel/skylake/nhlt/nau88l25.c +++ b/src/soc/intel/skylake/nhlt/nau88l25.c @@ -15,8 +15,7 @@ #include <soc/nhlt.h> -/* The same DSP firmware settings are used for both the capture and - * render endpoints. */ +/* The same DSP firmware settings are used for both the capture and render endpoints. */ static const struct nhlt_format_config nau88l25_formats[] = { /* 48 KHz 24-bits per sample. */ { diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c index 9c48c7b..5be881c 100644 --- a/src/soc/intel/skylake/nhlt/rt5514.c +++ b/src/soc/intel/skylake/nhlt/rt5514.c @@ -53,8 +53,7 @@ { switch (num_channels) { case 4: - return nhlt_add_ssp_endpoints(nhlt, hwlink, - rt5514_4ch_descriptors, + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5514_4ch_descriptors, ARRAY_SIZE(rt5514_4ch_descriptors)); default: return -1; diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c index c5a3f53..a308265 100644 --- a/src/soc/intel/skylake/nhlt/rt5663.c +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -16,8 +16,7 @@ #include <soc/nhlt.h> /* - * The same DSP firmware settings are used for both the capture and - * render endpoints. + * The same DSP firmware settings are used for both the capture and render endpoints. */ static const struct nhlt_format_config rt5663_formats[] = { /* 48 KHz 24-bits per sample. */ diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c index c1e9118..f118b38 100644 --- a/src/soc/intel/skylake/p2sb.c +++ b/src/soc/intel/skylake/p2sb.c @@ -31,14 +31,13 @@ * Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband * access for MIPI controller. */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | - (1 << 16) | (1 << 10) | (1 << 1); + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | (1 << 16) | + (1 << 10) | (1 << 1); ep_mask[P2SB_EP_MASK_5_REG] = mask; /* - * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband - * access for XHCI controller. + * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband access for XHCI controller. */ mask = (1 << 6) | (1 << 5); diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ffe0605..65075ea 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -48,8 +48,7 @@ } /* - * Set which power state system will be after reapplying - * the power (from G3 State) + * Set which power state system will be after reapplying the power (from G3 State) */ void pmc_soc_set_afterg3_en(const bool on) { @@ -84,10 +83,8 @@ static const struct reg_script pch_pmc_misc_init_script[] = { /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ - REG_PCI_RMW16(GEN_PMCON_B, - ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), - S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | - DIS_SLP_X_STRCH_SUS_UP), + REG_PCI_RMW16(GEN_PMCON_B, ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), + S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP), /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), REG_SCRIPT_END @@ -107,8 +104,7 @@ uint32_t reg; uint8_t *pmcbase = pmc_mmio_regs(); - printk(BIOS_DEBUG, "%sabling Deep S%c\n", - enable ? "En" : "Dis", sx + '0'); + printk(BIOS_DEBUG, "%sabling Deep S%c\n", enable ? "En" : "Dis", sx + '0'); reg = read32(pmcbase + offset); if (enable) reg |= mask; @@ -168,12 +164,10 @@ static void pm1_enable_pwrbtn_smi(void *unused) { /* - * Enable power button SMI only before jumping to payload. This ensures - * that: + * Enable power button SMI only before jumping to payload. This ensures that: * 1. Power button SMI is enabled only after coreboot is done. - * 2. On resume path, power button SMI is not enabled and thus avoids - * any shutdowns because of power button presses due to power button - * press in resume path. + * 2. On resume path, power button SMI is not enabled and thus avoids any shutdowns + * because of power button presses due to power button press in resume path. */ pmc_update_pm1_enable(PWRBTN_EN); } @@ -181,10 +175,9 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); /* - * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in - * deep_sx_config. If WAKE# pin is not enabled, then PCI Express Wake Disable - * bit needs to be set in PM1_EN to avoid unnecessary wakes caused by WAKE# - * pin. + * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in deep_sx_config. + * If WAKE# pin is not enabled, then PCI Express Wake Disable bit needs to be set + * in PM1_EN to avoid unnecessary wakes caused by WAKE# pin. */ static void pm1_handle_wake_pin(void *unused) { diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 90f1b03..ee3c74d 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -212,22 +212,18 @@ } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { /* - * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. + * Check for any power failure to determine if this a wake from S5 because + * the PCH does not set the WAK_STS bit when waking from a true G3 state. */ - if (!(ps->pm1_sts & WAK_STS) && - (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) + if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) prev_sleep_state = ACPI_S5; /* - * If waking from S3 determine if deep S3 is enabled. If not, - * need to check both deep sleep well and normal suspend well. - * Otherwise just check deep sleep well. + * If waking from S3 determine if deep S3 is enabled. If not, need to check both + * deep sleep well and normal suspend well. Otherwise just check deep sleep well. */ if (prev_sleep_state == ACPI_S3) { /* PWR_FLR represents deep sleep power well loss. */ @@ -250,8 +246,7 @@ ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); @@ -260,8 +255,7 @@ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); - printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b); printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index ff1a959..a87ce47 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -24,14 +24,12 @@ static void do_force_global_reset(void) { /* - * BIOS should ensure it does a global reset - * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] + * BIOS should ensure it does a global reset to reset both host and + * Intel ME by setting PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] */ pmc_global_reset_enable(true); - /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port - * to global reset platform */ + /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port to global reset platform */ do_full_reset(); } @@ -39,7 +37,7 @@ { if (send_global_reset() != 0) { /* If ME unable to reset platform then - * force global reset using PMC CF9GR register*/ + * force global reset using PMC CF9GR register */ do_force_global_reset(); } } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2d0de2f..e1e3ad0 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -51,8 +51,7 @@ } /* UPD parameters to be initialized before MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) { const struct soc_intel_skylake_config *config; @@ -61,11 +60,10 @@ config = config_of_path(PCH_DEVFN_LPC); /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake does not - * have access to the bios_reserved range so it always assumes 8MB is - * used and so the kernel will avoid the last 8MB of the stolen window. - * With the default stolen size of 32MB(-8MB) there is not enough space - * for FBC to work with a high resolution panel. + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have access to + * the bios_reserved range so it always assumes 8MB is used and so the kernel will + * avoid the last 8MB of the stolen window. With the default stolen size of 32MB(-8MB), + * there is not enough space for FBC to work with a high resolution panel. */ upd->IgdDvmt50PreAlloc = 2; @@ -90,34 +88,25 @@ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); + memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param); memory_cfg->MrcFastBoot = 0x00; memory_cfg->SaGv = 0x02; } -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) { /* Display the parameters for MemoryInit */ printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); - fsp_display_upd_value("PlatformMemorySize", 8, - old->PlatformMemorySize, new->PlatformMemorySize); - fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, - new->MemorySpdPtr00); - fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, - new->MemorySpdPtr01); - fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, - new->MemorySpdPtr10); - fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, - new->MemorySpdPtr11); + fsp_display_upd_value("PlatformMemorySize", 8, old->PlatformMemorySize, + new->PlatformMemorySize); + fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, new->MemorySpdPtr00); + fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, new->MemorySpdPtr01); + fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, new->MemorySpdPtr10); + fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, new->MemorySpdPtr11); fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen, new->MemorySpdDataLen); fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0], @@ -208,46 +197,32 @@ new->RcompResistor[1]); fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2], new->RcompResistor[2]); - fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], - new->RcompTarget[0]); - fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], - new->RcompTarget[1]); - fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], - new->RcompTarget[2]); - fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], - new->RcompTarget[3]); - fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], - new->RcompTarget[4]); - fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, - new->CaVrefConfig); + fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], new->RcompTarget[0]); + fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], new->RcompTarget[1]); + fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], new->RcompTarget[2]); + fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], new->RcompTarget[3]); + fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], new->RcompTarget[4]); + fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, new->CaVrefConfig); fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask); - fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, - new->MrcFastBoot); + fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, new->MrcFastBoot); fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); - fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, - new->EnableTraceHub); + fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, new->EnableTraceHub); fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, new->IgdDvmt50PreAlloc); - fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, - new->InternalGfx); - fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, - new->ApertureSize); + fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, new->InternalGfx); + fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, new->ApertureSize); fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); - fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, - new->FspCarBase); - fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, - new->FspCarSize); + fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, new->FspCarBase); + fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, new->FspCarSize); } /* SOC initialization after RAM is enabled. */ void soc_after_ram_init(struct romstage_params *params) { - /* Set the DISB as soon as possible after DRAM - * init and MRC cache is saved. - */ + /* Set the DISB as soon as possible after DRAM init and MRC cache is saved. */ pmc_set_disb(); } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index ecd1428..c517d1f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -60,22 +60,16 @@ struct dimm_info *dest_dimm; struct memory_info *mem_info; const MEMORY_INFO_DATA_HOB *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = - FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; /* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = - fsp_find_extension_hob_by_guid(smbios_memory_info_guid, - &hob_size); + memory_info_hob = fsp_find_extension_hob_by_guid(smbios_memory_info_guid, &hob_size); if (memory_info_hob == NULL || hob_size == 0) { printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; } - /* - * Allocate CBMEM area for DIMM information used to populate SMBIOS - * table 17 - */ + /* Allocate CBMEM area for DIMM information used to populate SMBIOS table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); if (mem_info == NULL) { printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); @@ -165,8 +159,7 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } -static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, - FSP_M_TEST_CONFIG *m_t_cfg, +static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, FSP_M_TEST_CONFIG *m_t_cfg, const struct soc_intel_skylake_config *config) { const struct device *dev; @@ -177,8 +170,7 @@ * device pci 01.0 on end # enable PEG0 root port * device pci 01.1 off end # do not configure PEG1 * - * If PEG port is not defined in the device tree, it will be disabled - * in FSP + * If PEG port is not defined in the device tree, it will be disabled in FSP */ dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ if (!dev || !dev->enabled) @@ -239,7 +231,7 @@ m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) - mask |= (1<<i); + mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; @@ -269,12 +261,11 @@ } else { m_cfg->InternalGfx = 1; /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake - * does not have access to the bios_reserved range so it always - * assumes 8MB is used and so the kernel will avoid the last - * 8MB of the stolen window. With the default stolen size of - * 32MB(-8MB) there is not enough space for FBC to work with - * a high resolution panel + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have + * access to the bios_reserved range so it always assumes 8MB is used and so + * the kernel will avoid the last 8MB of the stolen window. With the default + * stolen size of 32MB(-8MB) there is not enough space for FBC to work with + * a high resolution panel. */ m_cfg->IgdDvmt50PreAlloc = 2; } @@ -324,14 +315,10 @@ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); + memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param); memory_cfg->MrcFastBoot = 0x00; memory_cfg->SaGv = 0x02; } diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea24..48884ec 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -33,8 +33,7 @@ if (config->ignore_vtd) return; - const bool vtd_capable = - !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); if (!vtd_capable) return; @@ -58,11 +57,9 @@ }; /* Set Fixed MMIO address into PCI configuration space */ - sa_set_pci_bar(soc_fixed_pci_resources, - ARRAY_SIZE(soc_fixed_pci_resources)); + sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); /* Set Fixed MMIO address into MCH base address */ - sa_set_mch_bar(soc_fixed_mch_resources, - ARRAY_SIZE(soc_fixed_mch_resources)); + sa_set_mch_bar(soc_fixed_mch_resources, ARRAY_SIZE(soc_fixed_mch_resources)); systemagent_vtd_init(); diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..b4f16e9 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -27,19 +27,15 @@ void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS + * BWE is RW, so the SMI was caused by a write to BWE, not by a write to the BIOS * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. + * This is the place where we notice someone is trying to tinker with the BIOS. + * We are trying to be nice and just ignore it. A more resolute answer would be + * to power down the box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); fast_spi_enable_wp(); @@ -48,8 +44,7 @@ /* SMI handlers that should be serviced in SCI mode too. */ uint32_t smihandler_soc_get_sci_mask(void) { - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | + uint32_t sci_mask = SMI_HANDLER_SCI_EN(APM_STS_BIT) | SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); return sci_mask; diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..f92d3f4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -46,23 +46,20 @@ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, +static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; /* - * The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. + * The relocated handler runs with all CPUs concurrently. Therefore stagger + * the entry points adjusting SMBASE downwards by save state size * CPU num. */ smbase = staggered_smbase; iedbase = relo_params->ied_base; - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", smbase, iedbase); /* * All threads need to set IEDBASE and SMBASE to the relocated @@ -93,8 +90,7 @@ } else { em64t101_smm_state_save_area_t *save_state; - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -120,12 +116,10 @@ } /* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. + * The relocation work is actually performed in SMM context, but the code resides in the + * ramstage module. This occurs by trampolining from the default SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; @@ -133,18 +127,15 @@ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* - * Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. + * Determine if the processor supports saving state in MSRs. If so, enable it before + * the non-BSPs run so that SMM relocation can occur in parallel in the non-BSP CPUs. */ if (cpu == 0) { /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. + * If smm_save_state_in_msrs is 1 then that means this is the 2nd time through + * the relocation handler for the BSP. Parallel SMM handler relocation is + * taking place. However, it is desired to access other CPUs save state in the + * real SMM handler. Therefore, disable the SMM save state in MSRs feature. */ if (relo_params->smm_save_state_in_msrs) { msr_t smm_feature_control; @@ -154,10 +145,9 @@ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); } else if (bsp_setup_msr_save_state(relo_params)) /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. + * Just return from relocation handler if MSR save state is enabled. + * In that case the BSP will come back into the relocation handler + * to setup the new SMBASE as well disabling SMM save state in MSRs. */ return; } @@ -210,8 +200,7 @@ memset(ied_base + (1 << 20), 0, (32 << 10)); } -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); @@ -243,10 +232,9 @@ void smm_relocate(void) { /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation shall take place. + * Run the relocation handler a second time on the BSP to do * the final move. + * For APs, a relocation handler always needs to be run. */ if (smm_reloc_params.smm_save_state_in_msrs) smm_initiate_relocation_parallel(); @@ -258,9 +246,8 @@ { struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. + * LOCK the SMM memory window and enable normal SMM. After running this + * function, only a full reset can make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 410265f..825078b 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -30,23 +30,21 @@ bool soc_is_vtd_capable(void) { struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - return root_dev && - !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); + + return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); } /* * SoC implementation * - * Add all known fixed memory ranges for Host Controller/Memory - * controller. + * Add all known fixed memory ranges for Host Controller/Memory controller. */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, @@ -60,11 +58,9 @@ if (!config->ignore_vtd && soc_is_vtd_capable()) { if (igd_dev && igd_dev->enabled) - sa_add_fixed_mmio_resources(dev, index, - &soc_gfxvt_mmio_descriptor, 1); + sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); - sa_add_fixed_mmio_resources(dev, index, - &soc_vtvc0_mmio_descriptor, 1); + sa_add_fixed_mmio_resources(dev, index, &soc_vtvc0_mmio_descriptor, 1); } } diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 089dd5d..7febe24 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -295,8 +295,7 @@ } #endif -void fill_vr_domain_config(void *params, - int domain, const struct vr_config *chip_cfg) +void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params; const struct vr_config *cfg; -- To view, visit https://review.coreboot.org/c/coreboot/+/35172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Gerrit-Change-Number: 35172 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: test
by HAOUAS Elyes (Code Review) May 3, 2020

May 3, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41014 ) Change subject: test ...................................................................... test Change-Id: I838089cba69e683daa9e08b4afca57a8bde9e954 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/41014/1 diff --git a/Makefile.inc b/Makefile.inc index e315732..63e57aa 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -264,13 +264,13 @@ # Ignore _HID & _ADR coexisting in Intel Lynxpoint and Broadwell ASL code. # See cb:38803 & cb:38802 # "Multiple types (Device object requires either a _HID or _ADR, but not both)" -MULTIPLE_TYPES_WARNING = 3073 +#MULTIPLE_TYPES_WARNING = 3073 -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) -else +#ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) +#IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) +#else IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -endif +#endif define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml -- To view, visit https://review.coreboot.org/c/coreboot/+/41014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I838089cba69e683daa9e08b4afca57a8bde9e954 Gerrit-Change-Number: 41014 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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