coreboot-gerrit May 2020

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Change in coreboot[master]: mb/google/dedede: Read DRAM part number from CBI
by Marco Chen (Code Review) 04 May '20

04 May '20

Hello Marco Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40836 to review the following change. Change subject: mb/google/dedede: Read DRAM part number from CBI ...................................................................... mb/google/dedede: Read DRAM part number from CBI The index of MEM_STRAPS will be migrated from per DRAM part number to per DRAM characteristic therefore one index mapped to a single SPD binary can represent to multiple DRAM part numbers as long as their characteristic is the same for DRAM controller to support. In this case, the real DRAM part number would be provisioned in the CBI instead of SPD in the factory flow. As a result, we need to extract DRAM part number from CBI. BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. check DRAM part number is correct in SMBIOS for memory device Change-Id: I40780a35e04efb279591e9db179cb86b5e907c0d Signed-off-by: Marco Chen <marcochen(a)google.com> --- M src/mainboard/google/dedede/romstage.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40836/1 diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 2efaaf1..a5ded5f 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,9 +6,13 @@ */ #include <baseboard/variants.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <memory_info.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include <string.h> #include <variant/gpio.h> void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -22,3 +26,30 @@ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } + +bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + static enum { + PART_NUM_NOT_READ, + PART_NUM_AVAILABLE, + PART_NUM_NOT_IN_CBI, + } part_num_state = PART_NUM_NOT_READ; + + if (part_num_state == PART_NUM_NOT_READ) { + if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "No DRAM part number in CBI!\n"); + part_num_state = PART_NUM_NOT_IN_CBI; + } else { + part_num_state = PART_NUM_AVAILABLE; + } + } + + if (part_num_state == PART_NUM_NOT_IN_CBI) + return false; + + *part_num = &part_num_store[0]; + *len = strlen(part_num_store) + 1; + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40780a35e04efb279591e9db179cb86b5e907c0d Gerrit-Change-Number: 40836 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/**/dsdt.asl: Drop unused BRIGHTNESS_{UP,DOWN}
by Angel Pons (Code Review) 04 May '20

04 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40865 ) Change subject: mb/**/dsdt.asl: Drop unused BRIGHTNESS_{UP,DOWN} ...................................................................... mb/**/dsdt.asl: Drop unused BRIGHTNESS_{UP,DOWN} It is only used with the Lenovo-specific H8 EC code. Change-Id: If3b209a9ab82a07ce7b4450d8a0b62a1ca86a95c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/snb_ivb_laptops/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl 8 files changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/40865/1 diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index db0ae47..1a85131 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \DSPC.BRTU -#define BRIGHTNESS_DOWN \DSPC.BRTD - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index b173dbe..a72ace1 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 1b52040..64d7373 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 9d4c890..8f318b4 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ - -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 27329e4..8f318b4 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 27329e4..8f318b4 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 27329e4..8f318b4 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 7cf6e08..d85d4b9 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -13,9 +13,6 @@ * GNU General Public License for more details. */ -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", -- To view, visit https://review.coreboot.org/c/coreboot/+/40865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3b209a9ab82a07ce7b4450d8a0b62a1ca86a95c Gerrit-Change-Number: 40865 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: treewide: Drop ACPI_VIDEO_DEVICE macro
by Angel Pons (Code Review) 04 May '20

04 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40864 ) Change subject: treewide: Drop ACPI_VIDEO_DEVICE macro ...................................................................... treewide: Drop ACPI_VIDEO_DEVICE macro It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t60/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/lenovo/x60/dsdt.asl M util/autoport/bd82x6x.go 22 files changed, 3 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/40864/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 45fa0a8..366fd09 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -141,13 +141,12 @@ BRIGHTNESS_DOWN() } -#ifdef ACPI_VIDEO_DEVICE /* Next display GPE */ Method(_Q16, 0, NotSerialized) { - Notify (ACPI_VIDEO_DEVICE, 0x82) + Notify (\_SB.PCI0.GFX0, 0x82) } -#endif + /* AC status change: present */ Method(_Q26, 0, NotSerialized) { diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index 0ab2c2f..d97e746 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 22 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index c626350..3db858f 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -117,7 +117,7 @@ /* Video output switch hotkey */ Method (_Q16, 0, NotSerialized) { - Notify (ACPI_VIDEO_DEVICE, 0x82) + Notify (\_SB.PCI0.GFX0, 0x82) ^HKEY.MHKQ (0x1007) } diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index 2b9357e..b26d1ac 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 23 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 001e91e..9df34cf 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index c2624d4..286615f 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index a03b252..384900a 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index a03b252..384900a 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 583f9f3..5f06afc 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index a03b252..384900a 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 94e7043..5ace124 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -15,7 +15,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define THINKPAD_EC_GPE 17 diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index a03b252..384900a 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index a03b252..384900a 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 51ff336..f2f9231 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \BRTU #define BRIGHTNESS_DOWN \BRTD -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include <arch/acpi.h> DefinitionBlock( diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 1c237fe..b82ef8b 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 22 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index ce85612..d1a9538 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT 1 diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index abe1c27..6cdfd69 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include <arch/acpi.h> DefinitionBlock( diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index c2624d4..286615f 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index a03b252..384900a 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index a03b252..384900a 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 78a51d3..4528fa1 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -4,7 +4,6 @@ #define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include <arch/acpi.h> DefinitionBlock( diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 87e7584..9f37aee 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -192,10 +192,6 @@ DSDTDefine{ Key: "BRIGHTNESS_DOWN", Value: "\\_SB.PCI0.GFX0.DECB", - }, - DSDTDefine{ - Key: "ACPI_VIDEO_DEVICE", - Value: "\\_SB.PCI0.GFX0", }) /* SPI init */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Gerrit-Change-Number: 40864 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/**/dsdt.asl: Drop unused ACPI_VIDEO_DEVICE
by Angel Pons (Code Review) 04 May '20

04 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40863 ) Change subject: mb/**/dsdt.asl: Drop unused ACPI_VIDEO_DEVICE ...................................................................... mb/**/dsdt.asl: Drop unused ACPI_VIDEO_DEVICE It is only used with the Lenovo-specific H8 EC code. Change-Id: I596d4d19277555894ab728e32a44e34a5a21e21d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/gigabyte/ga-h61m-series/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/snb_ivb_laptops/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl 11 files changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40863/1 diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index f14272d..db0ae47 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -3,7 +3,6 @@ #define BRIGHTNESS_UP \DSPC.BRTU #define BRIGHTNESS_DOWN \DSPC.BRTD -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include <arch/acpi.h> DefinitionBlock( diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 01656ad..b173dbe 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index ff5c708..1b52040 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index 7da32d3..40bb732 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 0c02456..591473a 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 247114e..9d4c890 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -4,7 +4,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index cea8efe..890956e 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 - #include <arch/acpi.h> DefinitionBlock( diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 150bdcf..27329e4 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 150bdcf..27329e4 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 150bdcf..27329e4 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -3,7 +3,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 8b23ee7..7cf6e08 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -15,7 +15,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", -- To view, visit https://review.coreboot.org/c/coreboot/+/40863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I596d4d19277555894ab728e32a44e34a5a21e21d Gerrit-Change-Number: 40863 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: asus/p2b: Align IDE settings, enable UDMA for all variants
by Keith Hui (Code Review) 04 May '20

04 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40961 ) Change subject: asus/p2b: Align IDE settings, enable UDMA for all variants ...................................................................... asus/p2b: Align IDE settings, enable UDMA for all variants Enable UDMA on all IDE interfaces for all variants. There's no reason not to. Change-Id: I12c9e0f66c437d8add5c4096fd2a5e747d082799 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/devicetree.cb M src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb M src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb 3 files changed, 4 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40961/1 diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 9dcd1da..9f7f63e 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -46,10 +46,10 @@ register "ide1_enable" = "1" register "ide_legacy_enable" = "1" # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" register "thrm_polarity" = "1" register "lid_polarity" = "1" end diff --git a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb index 7424144..ce36ce6 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb @@ -17,14 +17,6 @@ end end end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" end end end diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb index 6eabe58..b261a35 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb @@ -18,14 +18,6 @@ end end device pci 6.0 on end # Onboard SCSI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/40961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12c9e0f66c437d8add5c4096fd2a5e747d082799 Gerrit-Change-Number: 40961 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: nb/intel/i440bx: Ready raminit for S3 resume path
by Keith Hui (Code Review) 04 May '20

04 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40960 ) Change subject: nb/intel/i440bx: Ready raminit for S3 resume path ...................................................................... nb/intel/i440bx: Ready raminit for S3 resume path Change-Id: I77e95850af82a5684ba10841260db021f5de1e8b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h M src/northbridge/intel/i440bx/romstage.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40960/1 diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 18997c5..d1e0f40 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1004,7 +1004,7 @@ void __weak enable_spd(void) { } void __weak disable_spd(void) { } -void sdram_initialize(void) +void sdram_initialize(int s3resume) { timestamp_add_now(TS_BEFORE_INITRAM); enable_spd(); diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 534bc44..e9099de 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -9,7 +9,7 @@ void enable_spd(void); void disable_spd(void); -void sdram_initialize(void); +void sdram_initialize(int s3resume); void mainboard_enable_serial(void); /* Debug */ diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index 69cfa7f..199cf5c 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -10,6 +10,6 @@ { i82371eb_early_init(); - sdram_initialize(); + sdram_initialize(0); cbmem_initialize_empty(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77e95850af82a5684ba10841260db021f5de1e8b Gerrit-Change-Number: 40960 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/i440bx: Use SPDX for remaining files
by Keith Hui (Code Review) 04 May '20

04 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40959 ) Change subject: nb/intel/i440bx: Use SPDX for remaining files ...................................................................... nb/intel/i440bx: Use SPDX for remaining files Change-Id: I0d28f1fc835fc05b4fc3ab891e9e6e340848aa49 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/Makefile.inc M src/northbridge/intel/i440bx/i440bx.h M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h M src/northbridge/intel/i440bx/romstage.c 5 files changed, 9 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/40959/1 diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 708a41f..6270811 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -1,17 +1,5 @@ -## +## SPDX-License-Identifier: GPL-2.0-or-later ## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 3a2b3f4..1b58003 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef NORTHBRIDGE_INTEL_I440BX_I440BX_H #define NORTHBRIDGE_INTEL_I440BX_I440BX_H diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index ee1e759..18997c5 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include <spd.h> #include <delay.h> diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index dcc8007..534bc44 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef RAMINIT_H #define RAMINIT_H diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index bdcfdc9..69cfa7f 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include <arch/romstage.h> #include <cbmem.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/40959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d28f1fc835fc05b4fc3ab891e9e6e340848aa49 Gerrit-Change-Number: 40959 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/i440bx: Drop northbridge.h
by Keith Hui (Code Review) 04 May '20

04 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40958 ) Change subject: nb/intel/i440bx: Drop northbridge.h ...................................................................... nb/intel/i440bx: Drop northbridge.h It declares a function that was either never or no longer implemented. Change-Id: I714d39374519bff1afb94870d0e84f57db619a1f Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/northbridge.c D src/northbridge/intel/i440bx/northbridge.h 2 files changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/40958/1 diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index da0107c..d0c93fd 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -8,7 +8,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/cpu.h> -#include "northbridge.h" #include "i440bx.h" static void northbridge_init(struct device *dev) diff --git a/src/northbridge/intel/i440bx/northbridge.h b/src/northbridge/intel/i440bx/northbridge.h deleted file mode 100644 index f42211e..0000000 --- a/src/northbridge/intel/i440bx/northbridge.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_440BX_H -#define NORTHBRIDGE_INTEL_440BX_H - -extern unsigned int i440bx_scan_root_bus(struct device *root, unsigned int max); - -#endif /* NORTHBRIDGE_INTEL_440BX_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I714d39374519bff1afb94870d0e84f57db619a1f Gerrit-Change-Number: 40958 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i440bx: Resolve a SMP-raminit TODO
by Keith Hui (Code Review) 04 May '20

04 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40957 ) Change subject: nb/intel/i440bx: Resolve a SMP-raminit TODO ...................................................................... nb/intel/i440bx: Resolve a SMP-raminit TODO Change-Id: I0087294bccee079368c93ba8986873a5e65593b0 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/40957/1 diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index dddcc21..ee1e759 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -123,8 +123,11 @@ * [01:00] Reserved */ NBXCFG + 0, 0x0c, - // TODO: Bit 15 should be 0 for multiprocessor boards +#if CONFIG(SMP) + NBXCFG + 1, 0x00, +#else NBXCFG + 1, 0x80, +#endif NBXCFG + 2, 0x00, NBXCFG + 3, 0xff, -- To view, visit https://review.coreboot.org/c/coreboot/+/40957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0087294bccee079368c93ba8986873a5e65593b0 Gerrit-Change-Number: 40957 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82371eb: Move wakeup code to romstage
by Keith Hui (Code Review) 04 May '20

04 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40965 ) Change subject: sb/intel/i82371eb: Move wakeup code to romstage ...................................................................... sb/intel/i82371eb: Move wakeup code to romstage This code is needed in romstage, not ramstage. Change-Id: Ic38c3c50fb135fba582864a242348ec29cec2991 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/40965/1 diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 1a1a0a1..327c424 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -24,8 +24,8 @@ ramstage-y += smbus.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c romstage-y += early_smbus.c -- To view, visit https://review.coreboot.org/c/coreboot/+/40965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic38c3c50fb135fba582864a242348ec29cec2991 Gerrit-Change-Number: 40965 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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