coreboot-gerrit May 2020

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Change in coreboot[master]: soc/intel/jasperlake: Allow SD card power enable polarity configuration
by Ronak Kanabar (Code Review) 04 May '20

04 May '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41027 ) Change subject: soc/intel/jasperlake: Allow SD card power enable polarity configuration ...................................................................... Patch Set 7: (5 comments) https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@7 PS5, Line 7: Allow SdCardPowerEnableActiveHigh to be filled from devicetree > Allow SD card power enable polarity configuration? Done https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@9 PS5, Line 9: SdCardPowerEnable ActiveHigh > SdCardPowerEnableActiveHigh Done https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@9 PS5, Line 9: SdCardPowerEnable ActiveHigh is a UPD which controls polarity of SD card power enable > Can we limit line <72 characters? Done https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@11 PS5, Line 11: requirement > requirement. Done https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@16 PS5, Line 16: Signe > New line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Gerrit-Change-Number: 41027 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 14:58:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Allow SD card power enable polarity configuration
by Ronak Kanabar (Code Review) 04 May '20

04 May '20

Hello build bot (Jenkins), Patrick Georgi, Maulik V Vaghela, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41027 to look at the new patch set (#7). Change subject: soc/intel/jasperlake: Allow SD card power enable polarity configuration ...................................................................... soc/intel/jasperlake: Allow SD card power enable polarity configuration SdCardPowerEnable ActiveHigh is a UPD which controls polarity of SD card power enable pin. Setting it 1 will set polarity of this pin as Active high. This patch will allow to control it from devicetree so that it can be set as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified Upd value from fsp log Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: Id777a262651689952a217875e6606f67855fc2f4 --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41027/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/41027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Gerrit-Change-Number: 41027 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Allow SataEnable to be filled from devicetree
by Aamir Bohra (Code Review) 04 May '20

04 May '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41029 ) Change subject: soc/intel/jasperlake: Allow SataEnable to be filled from devicetree ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/c/coreboot/+/41029/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41029/2//COMMIT_MSG@9 PS2, Line 9: sata SATA https://review.coreboot.org/c/coreboot/+/41029/2//COMMIT_MSG@9 PS2, Line 9: sata SATA controller https://review.coreboot.org/c/coreboot/+/41029/2//COMMIT_MSG@11 PS2, Line 11: t t. https://review.coreboot.org/c/coreboot/+/41029/2//COMMIT_MSG@16 PS2, Line 16: Ch New line. -- To view, visit https://review.coreboot.org/c/coreboot/+/41029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Gerrit-Change-Number: 41029 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 14:58:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Add DisableHeciRetry to config
by Christian Walter (Code Review) 04 May '20

04 May '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40756 ) Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config ...................................................................... soc/intel/cannonlake: Add DisableHeciRetry to config Add DisableHeciRetry to the chip config and parse it in romstage. Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/40756/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 578473b..981c381 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -195,6 +195,7 @@ /* Heci related */ uint8_t Heci3Enabled; + uint8_t DisableHeciRetry; /* Gfx related */ uint8_t IgdDvmt50PreAlloc; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 010d152c..c99f5a5 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -128,6 +128,8 @@ config->sata_port[i].TxGen3DeEmph; } } + if (config->DisableHeciRetry) + tconfig->DisableHeciRetry = config->DisableHeciRetry; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/40756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Gerrit-Change-Number: 40756 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Allow SD card power enable polarity configuration
by Ronak Kanabar (Code Review) 04 May '20

04 May '20

Hello build bot (Jenkins), Patrick Georgi, Maulik V Vaghela, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41027 to look at the new patch set (#6). Change subject: soc/intel/jasperlake: Allow SD card power enable polarity configuration ...................................................................... soc/intel/jasperlake: Allow SD card power enable polarity configuration SdCardPowerEnable ActiveHigh is a UPD which controls polarity of SD card power enable pin. Setting it 1 will set polarity of this pin as Active high. This patch will allow to control it from devicetree so that it can be set as per each board's requirement BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified Upd value from fsp log Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: Id777a262651689952a217875e6606f67855fc2f4 --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41027/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/41027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Gerrit-Change-Number: 41027 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Allow SdCardPowerEnableActiveHigh to be filled ...
by Aamir Bohra (Code Review) 04 May '20

04 May '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41027 ) Change subject: soc/intel/jasperlake: Allow SdCardPowerEnableActiveHigh to be filled from devicetree ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@9 PS5, Line 9: SdCardPowerEnable ActiveHigh SdCardPowerEnableActiveHigh https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@11 PS5, Line 11: requirement requirement. -- To view, visit https://review.coreboot.org/c/coreboot/+/41027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Gerrit-Change-Number: 41027 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 14:56:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Allow SdCardPowerEnableActiveHigh to be filled ...
by Aamir Bohra (Code Review) 04 May '20

04 May '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41027 ) Change subject: soc/intel/jasperlake: Allow SdCardPowerEnableActiveHigh to be filled from devicetree ...................................................................... Patch Set 5: (3 comments) https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@7 PS5, Line 7: Allow SdCardPowerEnableActiveHigh to be filled from devicetree Allow SD card power enable polarity configuration? https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@9 PS5, Line 9: SdCardPowerEnable ActiveHigh is a UPD which controls polarity of SD card power enable Can we limit line <72 characters? https://review.coreboot.org/c/coreboot/+/41027/5//COMMIT_MSG@16 PS5, Line 16: Signe New line. -- To view, visit https://review.coreboot.org/c/coreboot/+/41027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Gerrit-Change-Number: 41027 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 14:54:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sconfig: Refuse devicetree with leaf "chip"s
by Paul Menzel (Code Review) 04 May '20

04 May '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/3189 ) Change subject: sconfig: Refuse devicetree with leaf "chip"s ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/3189/1/util/sconfig/sconfig.y File util/sconfig/sconfig.y: https://review.coreboot.org/c/coreboot/+/3189/1/util/sconfig/sconfig.y@37 PS1, Line 37: chipchildren: chipchildren device | device | chipchildren chip | chipchildren registers ; > the | is a separator, and we don't _want_ to allow the empty substitution anymore. […] Thanks a lot for the explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/3189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia35b518bd4acd631e78bdf63c4424c0fa6a81229 Gerrit-Change-Number: 3189 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 04 May 2020 13:48:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/p2b{,-ls}: Get rid of power button device
by Paul Menzel (Code Review) 04 May '20

04 May '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40007 ) Change subject: mb/asus/p2b{,-ls}: Get rid of power button device ...................................................................... mb/asus/p2b{,-ls}: Get rid of power button device Currently, two power buttons are exposed in ACPI, and detected by the operating system. [ 0.000000] Linux version 4.4.14-smp (root@hive) (gcc version 5.3.0 (GCC) ) #2 SMP Fri Jun 24 14:44:24 CDT 2016 […] [ 0.000000] DMI: ASUS P2B-LS/P2B-LS, BIOS 4.11-839-g11c5b3b180 01/10/2020 […] [ 23.887594] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input3 [ 23.887837] ACPI: Power Button [PWRB] [ 23.888158] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input4 [ 23.888383] ACPI: Power Button [PWRF] Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot, CB:27272) [1] to Intel 440BX boards [1]: > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. > > Chrome EC mainboards implemented the generic hardware power button in > a broken manner i.e. power button object with HID PNP0C0C is added to > ACPI however none of the boards set POWER_BUTTON flag in FADT. This > results in Linux kernel adding both fixed hardware power button as > well as generic hardware power button to the list of devices present > on the system. Though this is mostly harmless, it is logically > incorrect and can confuse any userspace utilities scanning the ACPI > devices. > > This change gets rid of the generic hardware power button from all > google mainboards and relies completely on the fixed hardware power > button. [1]: https://review.coreboot.org/27272 TEST=Verify, Linux detects only the fixed hardware power button: ACPI: Power Button [PWRF] that means, the message below is absent from the Linux log. ACPI: Power Button [PWRB] Change-Id: I0f5b7aaf32366360de3cce58cd742651a2bb46ba Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/p2b-ls/dsdt.asl M src/mainboard/asus/p2b/dsdt.asl 2 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/40007/1 diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index c79b786..c0ac141 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -107,15 +107,6 @@ /* Root of the bus hierarchy */ Scope (\_SB) { - Device (PWRB) - { - /* Power Button Device */ - Name (_HID, EisaId ("PNP0C0C")) - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } #include <southbridge/intel/i82371eb/acpi/intx.asl> PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index b52b4569..02b44f4 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -102,15 +102,6 @@ /* Root of the bus hierarchy */ Scope (\_SB) { - Device (PWRB) - { - /* Power Button Device */ - Name (_HID, EisaId ("PNP0C0C")) - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } #include <southbridge/intel/i82371eb/acpi/intx.asl> PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/40007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5b7aaf32366360de3cce58cd742651a2bb46ba Gerrit-Change-Number: 40007 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/external/GRUB2: prevent rebuild without actual changes
by Paul Menzel (Code Review) 04 May '20

04 May '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40955 ) Change subject: payloads/external/GRUB2: prevent rebuild without actual changes ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/40955/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40955/1//COMMIT_MSG@13 PS1, Line 13: 1. Changed list of included modules (CONFIG_GRUB2_EXTRA_MODULES) Please add a blank line above. https://review.coreboot.org/c/coreboot/+/40955/1/payloads/external/GRUB2/Ma… File payloads/external/GRUB2/Makefile: https://review.coreboot.org/c/coreboot/+/40955/1/payloads/external/GRUB2/Ma… PS1, Line 40: grub2: $(CONFIG_DEP) checkout grub2/build/config.h Excuse my ignorance, but why is moving `CONFIG_DEP` fixes the issue? Squashing the targets `config` and `grub2` is just for cosmetics? -- To view, visit https://review.coreboot.org/c/coreboot/+/40955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf5a316d0c9761426ec2ee306d78cd56d4bf19b5 Gerrit-Change-Number: 40955 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 12:51:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2020