coreboot-gerrit May 2020

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Change in coreboot[master]: mb/ocp/sonorapass: Add Sonora Pass
by Maxim Polyakov (Code Review) 01 May '20

01 May '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40469 ) Change subject: mb/ocp/sonorapass: Add Sonora Pass ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/40469/5/src/mainboard/ocp/sonorapa… File src/mainboard/ocp/sonorapass/Kconfig: https://review.coreboot.org/c/coreboot/+/40469/5/src/mainboard/ocp/sonorapa… PS5, Line 1: ## : ## This file is part of the coreboot project. : ## : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; either version 2 of the License, or : ## (at your option) any later version. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ## > # SPDX-License-Identifier: GPL-2.0-only […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Gerrit-Change-Number: 40469 Gerrit-PatchSet: 6 Gerrit-Owner: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 12:58:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/sonorapass: Add Sonora Pass
by Maxim Polyakov (Code Review) 01 May '20

01 May '20

Maxim Polyakov has uploaded a new patch set (#6) to the change originally created by Ryback Hung. ( https://review.coreboot.org/c/coreboot/+/40469 ) Change subject: mb/ocp/sonorapass: Add Sonora Pass ...................................................................... mb/ocp/sonorapass: Add Sonora Pass Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe --- A src/mainboard/ocp/sonorapass/Kconfig A src/mainboard/ocp/sonorapass/Kconfig.name A src/mainboard/ocp/sonorapass/Makefile.inc A src/mainboard/ocp/sonorapass/acpi/platform.asl A src/mainboard/ocp/sonorapass/board.fmd A src/mainboard/ocp/sonorapass/board_info.txt A src/mainboard/ocp/sonorapass/bootblock.c A src/mainboard/ocp/sonorapass/devicetree.cb A src/mainboard/ocp/sonorapass/dsdt.asl 9 files changed, 259 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40469/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Gerrit-Change-Number: 40469 Gerrit-PatchSet: 6 Gerrit-Owner: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/octopus/variants/garg: update Garfour SKU ID
by Tony Huang (Code Review) 01 May '20

01 May '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40586 ) Change subject: mb/google/octopus/variants/garg: update Garfour SKU ID ...................................................................... mb/google/octopus/variants/garg: update Garfour SKU ID SKUID: 49 - Garfour EVT (touch, TypeA DB) 50 - Garfour EVT (non-touch, HDMI DB) BUG=b:152861752 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I656a2bb2404efded6da6697664748b6c8d2ca4e0 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/garg/gpio.c M src/mainboard/google/octopus/variants/garg/include/variant/sku.h M src/mainboard/google/octopus/variants/garg/variant.c 3 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/40586/1 diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 0fc0487..d05becb 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -66,6 +66,7 @@ switch (sku_id) { case SKU_9_HDMI: case SKU_19_HDMI_TS: + case SKU_50_HDMI_GARFOUR: *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; case SKU_17_LTE: diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index bfe7615..178ea7e 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -13,6 +13,8 @@ SKU_20_2A2C_TS = 20, SKU_37_2A2C_360 = 37, SKU_38_2A2C_360_TS_NO_STYLUES = 38, + SKU_49_TS_GARFOUR = 49, /*touch, TypeA DB*/ + SKU_50_HDMI_GARFOUR = 50, /*non-touch, HDMI DB*/ }; #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 29796b7..357070d 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -47,6 +47,7 @@ switch (sku_id) { case SKU_9_HDMI: case SKU_19_HDMI_TS: + case SKU_50_HDMI_GARFOUR: return "vbt_garg_hdmi.bin"; default: return "vbt.bin"; -- To view, visit https://review.coreboot.org/c/coreboot/+/40586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I656a2bb2404efded6da6697664748b6c8d2ca4e0 Gerrit-Change-Number: 40586 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/aspeed/common: Add early configure functions
by 9elements QA (Code Review) 01 May '20

01 May '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40483 ) Change subject: superio/aspeed/common: Add early configure functions ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2872 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2871 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2870 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2869 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/40483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59c29a042b2c7bf196b8a5bd5218704d8075855 Gerrit-Change-Number: 40483 Gerrit-PatchSet: 8 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 May 2020 12:29:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/kconfig: Remove miniconfig script
by Patrick Georgi (Code Review) 01 May '20

01 May '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37150 ) Change subject: util/kconfig: Remove miniconfig script ...................................................................... util/kconfig: Remove miniconfig script It replicates the functionality of savedefconfig because back when the script was added, savedefconfig didn't work for us. It now does, is the official way of doing things, is recommended in our documentation and is also a fair bit faster. Change-Id: Ia8e0377537ff7cd638c564037ea6a77b01a87243 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- D util/kconfig/miniconfig 1 file changed, 0 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/37150/1 diff --git a/util/kconfig/miniconfig b/util/kconfig/miniconfig deleted file mode 100755 index 29a4035..0000000 --- a/util/kconfig/miniconfig +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/env bash -# -# miniconfig - utility to minimize your coreboot config files -# -# Copyright 2015 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -CONFIG=$1 -NEWCONFIG=$2 - -CONF=build/util/kconfig/conf -KCONFIG=src/Kconfig -DOTCONFIG=.config -PREVCONFIG=.config.prev -TMPCONFIG=.config.mini - -recreate_config() -{ - $CONF --olddefconfig $KCONFIG &> /dev/null -} - -if [ "$CONFIG" == "" ]; then - printf "usage: util/miniconfig/miniconfig [path to config file] <path to new config file>\n" - exit 0 -fi - -if [ ! -r "$CONFIG" ]; then - printf "Can't read $CONFIG.\n" - exit 1 -fi - -if [ "$CONFIG" == .config ]; then - printf "Can't use .config, it's overwritten. Make a backup.\n" - exit 1 -fi - -if [ ! -x "$CONF" ]; then - printf "conf utility at $CONF not available.\n" - exit 1 -fi - -# Start out by creating a default config file for a mainboard -VENDOR=$( grep ^CONFIG_VENDOR "$CONFIG" ) -BOARD=$( grep ^CONFIG_BOARD "$CONFIG" | grep -v ROMSIZE | grep -v SPECIFIC_OPTIONS ) - -printf "$VENDOR\n$BOARD\n" > "$TMPCONFIG" -cp "$TMPCONFIG" "$DOTCONFIG" -recreate_config - -LINES=$( cat "$CONFIG" | wc -l ) -CUR=1 - -# Now go through each line of the existing, large config file, add it to our -# new minimal config file, and see if it makes a difference when running "make -# olddefconfig". If it does, keep the line, otherwise discard it. - -cat "$CONFIG" | while read L; do - printf "\rProcessing $CONFIG - $CUR / $LINES (%d%%)" $(( $CUR * 100 / $LINES)) - mv "$DOTCONFIG" "$PREVCONFIG" - cp "$TMPCONFIG" "$DOTCONFIG" - echo "$L" >> "$DOTCONFIG" - recreate_config - - if ! diff -q "$DOTCONFIG" "$PREVCONFIG" > /dev/null; then - echo "$L" >> "$TMPCONFIG" - fi - CUR=$(( $CUR + 1 )) -done - -echo - -if [ "$NEWCONFIG" != "" ]; then - printf "Writing new, minimized config to $NEWCONFIG\n" - mv "$TMPCONFIG" "$NEWCONFIG" -else - printf "Overwriting $CONFIG with new, minimized config.\n" - mv "$TMPCONFIG" "$CONFIG" -fi -- To view, visit https://review.coreboot.org/c/coreboot/+/37150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e0377537ff7cd638c564037ea6a77b01a87243 Gerrit-Change-Number: 37150 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSE
by Furquan Shaikh (Code Review) 01 May '20

01 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40700 ) Change subject: soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSE ...................................................................... soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSE This change updates Makefile.inc to use a helper function set-bit to set a bit for the soft fuses. It gets rid of the different checks that were done to set soft fuses to magic values in different places. This is still not the best way to handle the fuses and instead this logic should be embedded within the amdfwtool by making it aware of specific platforms. But until that happens, we want to avoid having to add PSP_SOFTFUSE setting in various places with different values. BUG=b:154880818 Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40700/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 446198e..012ab8b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -108,9 +108,8 @@ # type = 0x9 PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin - -# type = 0xb - See #55758 (NDA) for bit definitions. -PSP_SOFTFUSE="0x0000000010000001" +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 ifeq ($(CONFIG_USE_PSPSCUREOS),y) # types = 0x2 @@ -134,7 +133,8 @@ # BIOS type = 0x6a PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin else -PSP_SOFTFUSE="0x0000000030000001" +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 endif # type = 0x28 @@ -199,6 +199,14 @@ PSP_UCODE_FILE2=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin PSP_UCODE_FILE3=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +# type = 0xb - See #55758 (NDA) for bit definitions. +PSP_SOFTFUSE_BITS += 28 + +# Helper function to return a value with given bit set +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + # # Build the arguments to amdfwtool (order is unimportant). Missing file names # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -- To view, visit https://review.coreboot.org/c/coreboot/+/40700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b Gerrit-Change-Number: 40700 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/romstage_spd_smbus.c: Fix missing DIMM issue
by Edward O'Callaghan (Code Review) 01 May '20

01 May '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40820 ) Change subject: mb/google/hatch/romstage_spd_smbus.c: Fix missing DIMM issue ...................................................................... mb/google/hatch/romstage_spd_smbus.c: Fix missing DIMM issue Since https://review.coreboot.org/c/coreboot/+/40558/13 got merged Puff will not be able to boot up and stop as below log: ``` ... SPD: banks 16, ranks 2, rows 16, columns 10, density 8192 Mb SPD: device width 8 bits, bus width 64 bits SPD: module size is 16384 MB (per channel) ASSERTION ERROR: file 'src/soc/intel/cannonlake/cnl_memcfg_init.c', line 47 ``` BUG=b:155220125 BRANCH=none TEST=none Change-Id: I5f47c849344951d53fa8c67e779b7c46d632d124 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/romstage_spd_smbus.c 1 file changed, 15 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40820/1 diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 4aa37fa..bac5d58 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -18,15 +18,24 @@ /* Access memory info through SMBUS. */ get_spd_smbus(&blk); - memcfg.spd[0].read_type = READ_SPD_MEMPTR; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; + + if (blk.spd_array[0] == NULL) { + memcfg.spd[0].read_type = NOT_EXISTING; + } else { + memcfg.spd[0].read_type = READ_SPD_MEMPTR; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; + } memcfg.spd[1].read_type = NOT_EXISTING; - memcfg.spd[2].read_type = READ_SPD_MEMPTR; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; + if (blk.spd_array[1] == NULL) { + memcfg.spd[2].read_type = NOT_EXISTING; + } else { + memcfg.spd[2].read_type = READ_SPD_MEMPTR; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; + } memcfg.spd[3].read_type = NOT_EXISTING; dump_spd_info(&blk); -- To view, visit https://review.coreboot.org/c/coreboot/+/40820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f47c849344951d53fa8c67e779b7c46d632d124 Gerrit-Change-Number: 40820 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/cpu/x86/mtrr/earlymtrr: Add clear_all_var_mtrr
by Raul Rangel (Code Review) 01 May '20

01 May '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40764 ) Change subject: src/cpu/x86/mtrr/earlymtrr: Add clear_all_var_mtrr ...................................................................... src/cpu/x86/mtrr/earlymtrr: Add clear_all_var_mtrr Picasso does not define the state of variable MTRRs on boot. Add a helper function to clear all MTRRs. BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I21b887ce12849a95ddd8f1698028fb6bbfb4a7f6 --- M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/40764/1 diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 4d14a8d..e400359 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -42,3 +42,17 @@ maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); } + +void clear_all_var_mtrr(void) +{ + msr_t mtrr = {0, 0}; + int vcnt; + int i; + + vcnt = get_var_mtrr_count(); + + for (i = 0; i < vcnt; i++) { + wrmsr(MTRR_PHYS_MASK(i), mtrr); + wrmsr(MTRR_PHYS_BASE(i), mtrr); + } +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 07db3cb..50148ff 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -107,6 +107,7 @@ void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, unsigned int type); int get_free_var_mtrr(void); +void clear_all_var_mtrr(void); asmlinkage void display_mtrrs(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/40764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b887ce12849a95ddd8f1698028fb6bbfb4a7f6 Gerrit-Change-Number: 40764 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mb/google/volteer: workaround for GPIO PM on s0ix entry/exit
by Venkata Krishna Nimmagadda (Code Review) 01 May '20

01 May '20

Venkata Krishna Nimmagadda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40261 ) Change subject: src/mb/google/volteer: workaround for GPIO PM on s0ix entry/exit ...................................................................... src/mb/google/volteer: workaround for GPIO PM on s0ix entry/exit Setting the default values for GPIO community power management, causing issues in detecting tpm interrupts. So to avoid that gpio pm had to be disabled in devicetree. But for s0ix it is needed. This patch implements a workaround in asl code to enable gpio pm on s0ix entry and disable it on s0ix exit. This patch adds three methods platform specific methods 1. MS0X to enable power management features for GPIO communities on entry and on exit, it disables them. 2. MPTS to enable power management features for GPIO communities when preparing to sleep 3. MWAK to disable power management features for GPIO communities on waking up BUG=b:148892882 BRANCH=none TEST="Booted with this change on volteer proto1 and checked for GPIO community config with debugger" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda(a)intel.com> Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3 --- M src/mainboard/google/volteer/dsdt.asl A src/mainboard/google/volteer/mainboard.asl 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40261/1 diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 640f7cd..ac4b0b9 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -32,11 +32,16 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } + /* Mainboard hooks */ + #include "mainboard.asl" } // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> + /* Low power idle table */ + #include <soc/intel/tigerlake/acpi/lpit.asl> + // Chrome OS Embedded Controller Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl new file mode 100644 index 0000000..69f5a23 --- /dev/null +++ b/src/mainboard/google/volteer/mainboard.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <intelblocks/gpio.h> + +Method (LOCL, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + LOCL (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.LPID._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + } Else { + /* S0ix Exit */ + LOCL (0) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3 Gerrit-Change-Number: 40261 Gerrit-PatchSet: 1 Gerrit-Owner: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/sata: Add missing .ops_pci member
by Furquan Shaikh (Code Review) 01 May '20

01 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40777 ) Change subject: soc/amd/common/block/sata: Add missing .ops_pci member ...................................................................... soc/amd/common/block/sata: Add missing .ops_pci member This change sets .ops_pci for sata device_operations to default pci_dev_ops_pci. BUG=b:153858769 Change-Id: I695ac8961c92a3061beca890f5d47413b251e22b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/common/block/sata/sata.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/40777/1 diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 4db00b1..1959d3d 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -19,6 +19,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = soc_enable_sata_features, + .ops_pci = &pci_dev_ops_pci, .acpi_name = sata_acpi_name, .acpi_fill_ssdt = acpi_device_write_pci_dev, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/40777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I695ac8961c92a3061beca890f5d47413b251e22b Gerrit-Change-Number: 40777 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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