coreboot-gerrit May 2020

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Change in coreboot[master]: soc/amd/picasso/bootblock: Remove duplicate sb_reset_i2c_slaves
by Raul Rangel (Code Review) 01 May '20

01 May '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40867 ) Change subject: soc/amd/picasso/bootblock: Remove duplicate sb_reset_i2c_slaves ...................................................................... soc/amd/picasso/bootblock: Remove duplicate sb_reset_i2c_slaves sb_reset_i2c_slaves is called in fch_pre_init. BUG=b:153675916 TEST=Builds on trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I157e473984257d633ceb3ef9df45c71a31c5c00b --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/40867/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index de0cb6e..24b8f94 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -17,7 +17,6 @@ void bootblock_soc_early_init(void) { - sb_reset_i2c_slaves(); fch_pre_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157e473984257d633ceb3ef9df45c71a31c5c00b Gerrit-Change-Number: 40867 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/bootblock/bootblock: Remove duplicate i2c init
by Raul Rangel (Code Review) 01 May '20

01 May '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40866 ) Change subject: soc/amd/picasso/bootblock/bootblock: Remove duplicate i2c init ...................................................................... soc/amd/picasso/bootblock/bootblock: Remove duplicate i2c init fch_early_init already calls i2c_soc_early_init(). BUG=b:153675916 TEST=Boot trembyle and only see 1 i2c initialization message Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I689616fb617904df1781be3abe9d1dc580608173 --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/40866/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 8ae4db3..de0cb6e 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -27,5 +27,4 @@ printk(BIOS_DEBUG, "Family_Model: %08x\n", val); fch_early_init(); - i2c_soc_early_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I689616fb617904df1781be3abe9d1dc580608173 Gerrit-Change-Number: 40866 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Allow mainboard to provide pci ddi descriptors
by Raul Rangel (Code Review) 01 May '20

01 May '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40875 to review the following change. Change subject: soc/amd/picasso: Allow mainboard to provide pci ddi descriptors ...................................................................... soc/amd/picasso: Allow mainboard to provide pci ddi descriptors Mainboards must provide their DDI descriptors. BUG=b:153502861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/fsp_params.c A src/soc/amd/picasso/include/soc/platform_descriptors.h 3 files changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/40875/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d7cf9c0..55338a2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c +ramstage-y += fsp_params.c all-y += reset.c diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c new file mode 100644 index 0000000..0dbda09 --- /dev/null +++ b/src/soc/amd/picasso/fsp_params.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/pci.h> +#include <soc/pci_devs.h> +#include <soc/platform_descriptors.h> +#include <fsp/api.h> +#include "chip.h" + +static void fill_pcie_descriptors(FSP_S_CONFIG *scfg, + const picasso_fsp_pcie_descriptor *descs, size_t num) +{ + size_t i; + picasso_fsp_pcie_descriptor *fsp_pcie; + + /* FIXME: this violates C rules. */ + fsp_pcie = (picasso_fsp_pcie_descriptor *)(scfg->dxio_descriptor0); + + for (i = 0; i < num; i++) { + fsp_pcie[i] = descs[i]; + } +} + +static void fill_ddi_descriptors(FSP_S_CONFIG *scfg, + const picasso_fsp_ddi_descriptor *descs, size_t num) +{ + size_t i; + picasso_fsp_ddi_descriptor *fsp_ddi; + + /* FIXME: this violates C rules. */ + fsp_ddi = (picasso_fsp_ddi_descriptor *)&(scfg->ddi_descriptor0); + + for (i = 0; i < num; i++) { + fsp_ddi[i] = descs[i]; + } +} +static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) +{ + const picasso_fsp_pcie_descriptor *fsp_pcie; + const picasso_fsp_ddi_descriptor *fsp_ddi; + size_t num_pcie; + size_t num_ddi; + + mainboard_get_pcie_ddi_descriptors(&fsp_pcie, &num_pcie, + &fsp_ddi, &num_ddi); + fill_pcie_descriptors(scfg, fsp_pcie, num_pcie); + fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + FSP_S_CONFIG *scfg = &supd->FspsConfig; + + fsp_fill_pcie_ddi_descriptors(scfg); +} diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h new file mode 100644 index 0000000..bc67550 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__ +#define __PICASSO_PLATFORM_DESCRIPTORS_H__ + +#include <types.h> +#include <platform_descriptors.h> +#include <FspsUpd.h> + +/* Mainboard callback to obtain PCIe and DDI descriptors. */ +void mainboard_get_pcie_ddi_descriptors( + const picasso_fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); + +#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Gerrit-Change-Number: 40875 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Fix incorrect diag message in clear_pending_events()
by Victor Ding (Code Review) 01 May '20

01 May '20

Victor Ding has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40900 ) Change subject: Fix incorrect diag message in clear_pending_events() ...................................................................... Fix incorrect diag message in clear_pending_events() The expected error code should be EC_RES_UNAVAILABLE(9), not EC_RES_INVALID_COMMAND(1). Change-Id: I609490ceef675267760d34b5e9775211da93347c Signed-off-by: Victor Ding <victording(a)google.com> --- M src/ec/google/chromeec/smihandler.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40900/1 diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index febb457..5e192a5 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -41,7 +41,7 @@ while (google_chromeec_get_event() != 0) ; - printk(BIOS_DEBUG,"Clearing pending EC events. Error code 1 is expected.\n"); + printk(BIOS_DEBUG, "Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.\n"); while (google_chromeec_get_mkbp_event(&mkbp_event) == 0) ; } -- To view, visit https://review.coreboot.org/c/coreboot/+/40900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I609490ceef675267760d34b5e9775211da93347c Gerrit-Change-Number: 40900 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/deltaur: Add BT reset gpio
by EricR Lai (Code Review) 01 May '20

01 May '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40831 ) Change subject: mb/google/deltaur: Add BT reset gpio ...................................................................... mb/google/deltaur: Add BT reset gpio Harrison Peak (HrP) 9560 module need a reset pin for BT power sequence. BUG=b:155248677 TEST=Boot into OS and check BT is functional. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2 --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/gpio.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40831/1 diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 498266e..2aee78f 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -229,6 +229,7 @@ chip drivers/usb/acpi register "desc" = ""M.2 2230 (BT)"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device usb 2.9 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index a96e702..62b6559e 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -32,7 +32,7 @@ /* A12 : GPP_A12 ==> M2280_PCIE_SATA# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */ - PAD_CFG_GPO(GPP_A13, 0, DEEP), + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* A14 : GPP_A14 ==> USB_OC1# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : GPP_A15 ==> USB_OC2# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2 Gerrit-Change-Number: 40831 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better ...
by Subrata Banik (Code Review) 01 May '20

01 May '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40904 ) Change subject: soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding ...................................................................... soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding BIT 1 -> DEBUG_INTERFACE_ISA_SERIAL BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/40904/1 diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3983d03..4bdbb11 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -198,9 +198,9 @@ /* Debug interface selection */ enum { DEBUG_INTERFACE_RAM = (1 << 0), - DEBUG_INTERFACE_UART = (1 << 1), + DEBUG_INTERFACE_ISA_SERIAL = (1 << 1), DEBUG_INTERFACE_USB3 = (1 << 3), - DEBUG_INTERFACE_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), DEBUG_INTERFACE_TRACEHUB = (1 << 5), } debug_interface_flag; diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index a841809..89dd89a 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -60,7 +60,7 @@ /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + DEBUG_INTERFACE_ISA_SERIAL : DEBUG_INTERFACE_LPSS_SERIAL_IO; /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a3319d4..fa53371 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -195,9 +195,9 @@ /* Debug interface selection */ enum { DEBUG_INTERFACE_RAM = (1 << 0), - DEBUG_INTERFACE_UART = (1 << 1), + DEBUG_INTERFACE_ISA_SERIAL = (1 << 1), DEBUG_INTERFACE_USB3 = (1 << 3), - DEBUG_INTERFACE_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), DEBUG_INTERFACE_TRACEHUB = (1 << 5), } debug_interface_flag; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index b4521e2..ead20ff 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -71,7 +71,7 @@ /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + DEBUG_INTERFACE_ISA_SERIAL : DEBUG_INTERFACE_LPSS_SERIAL_IO; /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); -- To view, visit https://review.coreboot.org/c/coreboot/+/40904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f Gerrit-Change-Number: 40904 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/deltaur: Update USB/WWAN config
by Ivy Jian (Code Review) 01 May '20

01 May '20

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40818 ) Change subject: mb/google/deltaur: Update USB/WWAN config ...................................................................... mb/google/deltaur: Update USB/WWAN config Update USB3 ports configuration as schematics design. BUG=b:155026295 TEST=Boot into OS and check WWAN device detected by lsusb. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb 1 file changed, 8 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/40818/1 diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 498266e..7d59916 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -48,6 +48,8 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN # PCIe root port 6 (WLAN), clock 1 register "PcieRpEnable[5]" = "1" @@ -232,33 +234,21 @@ device usb 2.9 on end end chip drivers/usb/acpi - register "desc" = ""Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.0 on end end chip drivers/usb/acpi - register "desc" = ""Type-C Port 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.1 on end end chip drivers/usb/acpi - register "desc" = ""Type-A Port 1 (Right)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Type-A Port 2 (Left)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.3 on end - end - chip drivers/usb/acpi register "desc" = ""WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end + device usb 3.3 on end end end end @@ -297,7 +287,7 @@ device pci 1c.0 on end # PCIe Root Port #1 (USB) device pci 1c.1 on end # PCIe Root Port #2 (USB) device pci 1c.2 off end # PCIe Root Port #3 () - device pci 1c.3 on end # PCIe Root Port #4 (WWAN) + device pci 1c.3 off end # PCIe Root Port #4 (WWAN) device pci 1c.4 on end # PCIe Root Port #5 (LTE) device pci 1c.5 on end # PCIe Root Port #6 (WiFi) device pci 1c.6 on end # PCIe Root Port #7 (Card reader) -- To view, visit https://review.coreboot.org/c/coreboot/+/40818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf Gerrit-Change-Number: 40818 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/acpi: Add define for generic container HID
by Duncan Laurie (Code Review) 01 May '20

01 May '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40881 ) Change subject: arch/x86/acpi: Add define for generic container HID ...................................................................... arch/x86/acpi: Add define for generic container HID The generic container HID is defined in ACPI specification as PNP0A05. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I3632e77533a47f22b92259b469b03e63f51687e0 --- M src/arch/x86/include/arch/acpi.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40881/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 86b3932..5314d78 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -118,6 +118,7 @@ #define ACPI_HID_COM "PNP0501" #define ACPI_HID_LPT "PNP0400" #define ACPI_HID_PNP "PNP0C02" +#define ACPI_HID_CONTAINER "PNP0A05" /* Generic ACPI header, provided by (almost) all tables */ typedef struct acpi_table_header { -- To view, visit https://review.coreboot.org/c/coreboot/+/40881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3632e77533a47f22b92259b469b03e63f51687e0 Gerrit-Change-Number: 40881 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/acpi_device: Allow empty child references
by Duncan Laurie (Code Review) 01 May '20

01 May '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40880 ) Change subject: arch/x86/acpi_device: Allow empty child references ...................................................................... arch/x86/acpi_device: Allow empty child references Currently if a child table is created and added to a property list without adding any properties to that child it will generate an empty package. For example: struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); struct acpi_dp *prop = acpi_dp_new_table("PROP"); acpi_dp_add_child(dsd, "dsd-prop", prop); acpi_dp_write(dsd); Results in an empty PROP package: Name (_DSD, Package (2) { ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") Package (1) { Package (2) { "dsd-prop", "PROP" } } } Name (PROP, Package (0) { } Empty packages don't seem to be explicitly forbidden, but they don't serve a purpose with device properties. Instead, if packages without any properties or children are skipped then this empty package is not written and the added child property can refer to another property that is already defined. This allows creating property references to existing tables, which can save duplication and namespace collision issues with nested properties. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff --- M src/arch/x86/acpi_device.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/40880/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index b4016ef..f3ee1e7 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -665,7 +665,7 @@ char *dp_count, *prop_count = NULL; int child_count = 0; - if (!table || table->type != ACPI_DP_TYPE_TABLE) + if (!table || table->type != ACPI_DP_TYPE_TABLE || !table->next) return; /* Name (name) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff Gerrit-Change-Number: 40880 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Benjamin Doron (Code Review) 01 May '20

01 May '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40625 to look at the new patch set (#7). Change subject: [WIP] skl: PEG for Optimus ...................................................................... [WIP] skl: PEG for Optimus Creates PEG ACPI device for Optimus. Optimus is not working (dGPU does not appear in the OS; perhaps an issue with optimus_mb.asl - implementation of dGPU power functions). Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/soc/intel/skylake/acpi/peg.asl M src/soc/intel/skylake/acpi/systemagent.asl 2 files changed, 158 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40625/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2020