coreboot-gerrit May 2020

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Change in coreboot[master]: sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40791 ) Change subject: sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register ...................................................................... sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register Change-Id: I212ef304a03d068232f50a71c318e2b468336339 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/ibexpeak/usb_ehci.c 4 files changed, 22 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40791/1 diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index eb75b12..3a66b2c 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -262,8 +262,8 @@ pci_write_config32(dev, 0xd0, reg32); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + reg16 = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, reg16 | PCI_COMMAND_MASTER); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 5f6be1d..e298fba 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -358,6 +358,7 @@ { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -380,10 +381,10 @@ mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16w); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -475,7 +476,7 @@ { struct resource *res; struct mei_csr host; - u32 reg32; + u16 reg16; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -486,9 +487,9 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 29c3a76..7e5a025 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -66,24 +66,24 @@ void pch_enable(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_SERR; + pci_write_config16(dev, PCI_COMMAND, reg16); } } diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 40ba758..0307fc7 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -13,6 +13,7 @@ static void usb_ehci_init(struct device *dev) { u32 reg32; + u16 reg16; struct resource *res; u8 access_cntl; @@ -30,10 +31,10 @@ pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xfc, 0x301b1728); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + //reg16 |= PCI_COMMAND_SERR; + pci_write_config16(dev, PCI_COMMAND, reg16); access_cntl = pci_read_config8(dev, 0x80); -- To view, visit https://review.coreboot.org/c/coreboot/+/40791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212ef304a03d068232f50a71c318e2b468336339 Gerrit-Change-Number: 40791 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/intelmetool: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40790 ) Change subject: util/intelmetool: Fix 16-bit read/write PCI_COMMAND register ...................................................................... util/intelmetool: Fix 16-bit read/write PCI_COMMAND register Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/intelmetool/me.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/40790/1 diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index ee2b46a..e9aa510 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -574,7 +574,7 @@ uint32_t intel_mei_setup(struct pci_dev *dev) { struct mei_csr host; - uint32_t reg32; + uint16_t reg16; uint32_t pagerounded; mei_base_address = dev->base_addr[0] & ~0xf; @@ -588,9 +588,9 @@ } /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_long(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_long(dev, PCI_COMMAND, reg32); + reg16 = pci_read_word(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_word(dev, PCI_COMMAND, reg16); /* Clean up status for next message */ read_host_csr(&host); -- To view, visit https://review.coreboot.org/c/coreboot/+/40790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717 Gerrit-Change-Number: 40790 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40789 ) Change subject: soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/psp.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/40789/1 diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index 88bd61d..5a4cd4d 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -12,7 +12,8 @@ void soc_enable_psp_early(void) { - u32 base, limit, cmd; + u32 base, limit; + u16 cmd; /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; @@ -25,9 +26,9 @@ pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND); cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); }; void *soc_get_mbox_address(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/40789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f Gerrit-Change-Number: 40789 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree
by Meera Ravindranath (Code Review) 01 May '20

01 May '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40758 ) Change subject: mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree ...................................................................... mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree This CL selects the PcieRpClkReqDetect for the required root ports which is needed to allow proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/40758/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 7dc45ae..9a06f4b 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -67,8 +67,17 @@ register "PcieRpEnable[1]" = "1" register "PcieRpEnable[4]" = "1" + # Enable ClkReqDetect 1 for WLAN + # Enable ClkReqDetect 4 for NVMe + register "PcieRpClkReqDetect[1]" = "1" + register "PcieRpClkReqDetect[4]" = "1" + register "PcieClkSrcUsage[0]" = "0x04" register "PcieClkSrcUsage[1]" = "0x01" + register "PcieClkSrcUsage[2]" = "0xFF" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcClkReq[0]" = "0x00" register "PcieClkSrcClkReq[1]" = "0x01" -- To view, visit https://review.coreboot.org/c/coreboot/+/40758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Gerrit-Change-Number: 40758 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Include <smbios.h> when appropriate
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39816 ) Change subject: src: Include <smbios.h> when appropriate ...................................................................... src: Include <smbios.h> when appropriate Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/device.h M src/soc/intel/braswell/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/skylake/chip.h 4 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/39816/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 333ac5d..bbe861e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -5,6 +5,7 @@ #include <device/resource.h> #include <device/path.h> #include <device/pci_type.h> +#include <smbios.h> #include <types.h> struct device; @@ -29,7 +30,6 @@ struct bus; -struct smbios_type11; struct acpi_rsdp; struct device_operations { diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 026e491..767ecde 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -24,7 +24,6 @@ #include <fsp/util.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> -#include <smbios.h> #define SVID_CONFIG1 1 #define SVID_CONFIG3 3 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 7794fd4..5f58f08 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,7 +20,6 @@ #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> -#include <smbios.h> #include <stdint.h> #include <soc/gpio.h> #include <soc/pch.h> diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 178ab03..880c1d6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -31,7 +31,6 @@ #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> -#include <smbios.h> #define MAX_PEG_PORTS 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/39816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf Gerrit-Change-Number: 39816 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/include/device/device.h: Use already defined 'smbios_type11'
by HAOUAS Elyes (Code Review) 01 May '20

01 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40310 ) Change subject: src/include/device/device.h: Use already defined 'smbios_type11' ...................................................................... src/include/device/device.h: Use already defined 'smbios_type11' include <smbios.h> to use already defined 'smbios_type11'. Change-Id: Id412a504da2fd75648636febd150356569e07935 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/device.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/40310/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 4e9c594..d25cbd0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -5,6 +5,7 @@ #include <device/resource.h> #include <device/path.h> #include <device/pci_type.h> +#include <smbios.h> #include <types.h> struct device; @@ -29,7 +30,6 @@ struct bus; -struct smbios_type11; struct acpi_rsdp; struct device_operations { -- To view, visit https://review.coreboot.org/c/coreboot/+/40310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id412a504da2fd75648636febd150356569e07935 Gerrit-Change-Number: 40310 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Remove pad termination for RAM_STRAP_4
by Karthik Ramasubramanian (Code Review) 01 May '20

01 May '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40531 ) Change subject: mb/google/dedede: Remove pad termination for RAM_STRAP_4 ...................................................................... mb/google/dedede: Remove pad termination for RAM_STRAP_4 The stuffed resistor straps are weaker compared to the internal pull-up. This can cause the GPIO to read '1' always. Remove the internal pull-up. BUG=b:154301008 TEST=Build and boot the mainboard. Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40531/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index a4ce97d..58f5ca3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -348,7 +348,7 @@ /* S0 : RAM_STRAP_4 */ - PAD_CFG_GPI(GPP_S0, UP_5K, DEEP), + PAD_CFG_GPI(GPP_S0, NONE, DEEP), /* S1 : RSVD_STRAP */ PAD_NC(GPP_S1, NONE), /* S2 : DMIC1_CLK */ @@ -418,7 +418,7 @@ PAD_CFG_GPO(GPP_H19, 0, DEEP), /* S0 : RAM_STRAP_4 */ - PAD_CFG_GPI(GPP_S0, UP_5K, DEEP), + PAD_CFG_GPI(GPP_S0, NONE, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/40531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Gerrit-Change-Number: 40531 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Helios: Update DPTF settings for smooth fan speed control
by Sumeet R Pawnikar (Code Review) 01 May '20

01 May '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40530 ) Change subject: Helios: Update DPTF settings for smooth fan speed control ...................................................................... Helios: Update DPTF settings for smooth fan speed control Update DPTF settings for smooth fan speed control. BRANCH=firmware-hatch-12672.B BUG=b:154074920 TEST=Built and test on Helios system Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/40530/1 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index cf2d999..39d50c3 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -13,9 +13,12 @@ #define DPTF_TSR1_SENSOR_NAME "5V Regulator" #define DPTF_TSR1_PASSIVE 0 #define DPTF_TSR1_CRITICAL 70 -#define DPTF_TSR1_ACTIVE_AC0 42 -#define DPTF_TSR1_ACTIVE_AC1 41 -#define DPTF_TSR1_ACTIVE_AC2 39 +#define DPTF_TSR1_ACTIVE_AC0 43 +#define DPTF_TSR1_ACTIVE_AC1 42 +#define DPTF_TSR1_ACTIVE_AC2 41 +#define DPTF_TSR1_ACTIVE_AC3 40 +#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC5 38 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Ambient" @@ -73,7 +76,7 @@ 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 60, 50, 40, 30, 0, 0, 0, 0 }, Package () { -- To view, visit https://review.coreboot.org/c/coreboot/+/40530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87 Gerrit-Change-Number: 40530 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable camera support for waddledoo
by Patrick Georgi (Code Review) 01 May '20

01 May '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40476 ) Change subject: mb/google/dedede: Enable camera support for waddledoo ...................................................................... mb/google/dedede: Enable camera support for waddledoo BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/variants/baseboard/gpio.c A src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl 5 files changed, 22 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 3743908..85dbc38e 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -80,4 +80,10 @@ default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE +config VARIANT_HAS_CAMERA_ACPI + bool + default n + help + Select this option to enable camera ACPI support on the variant. + endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index cf9298c..25ad61f 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -11,6 +11,7 @@ select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 98ef6e4..f7bb6b9 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -34,6 +34,11 @@ } } +#if CONFIG(VARIANT_HAS_CAMERA_ACPI) + /* Camera */ + #include <variant/acpi/camera.asl> +#endif + /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index a4ce97d..b09d6c1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -170,13 +170,13 @@ /* D11 : GPP_D11/GSPI2_MOSI/UART0A_CTSB */ PAD_NC(GPP_D11, NONE), /* D12 : WCAM_RST_L */ - PAD_NC(GPP_D12, NONE), + PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* D13 : EN_PP2800_CAMERA */ - PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* D14 : EN_PP1200_CAMERA */ - PAD_NC(GPP_D14, NONE), + PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* D15 : UCAM_RST_L */ - PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* D16 : HP_INT_ODL */ PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), /* D17 : EN_SPK */ @@ -195,11 +195,11 @@ PAD_NC(GPP_D23, NONE), /* E0 : CLK_24M_UCAM */ - PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), /* E1 : EMR_RESET_L */ PAD_NC(GPP_E1, NONE), /* E2 : CLK_24M_WCAM */ - PAD_NC(GPP_E2, NONE), + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* E3 : GPP_E3/SATA_0_DEVSLP */ PAD_NC(GPP_E3, NONE), /* E4 : IMGCLKOUT_2 */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl new file mode 100644 index 0000000..304c0fe --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <baseboard/acpi/camera.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/40476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Gerrit-Change-Number: 40476 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/intel/dedede: Add camera support for WDoo
by Varshit B Pandya (Code Review) 01 May '20

01 May '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39360 ) Change subject: mb/intel/dedede: Add camera support for WDoo ...................................................................... mb/intel/dedede: Add camera support for WDoo Add support as per the schmatics Add 2 Ports and 2 Endpoints Add support for OTVI8856 and OTVI5676 Add ON and OFF logic as Power Rails are same for both sensor Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/variants/baseboard/gpio.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl A src/mainboard/google/dedede/variants/baseboard/include/waddledoo/camera.asl 9 files changed, 601 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/39360/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 068650b..880fe6a 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -62,6 +62,12 @@ string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_DEDEDE +# Select this option to enable camera ACPI support on the variant. +config VARIANT_HAS_CAMERA_ACPI + bool + default n if !BOARD_GOOGLE_WADDLEDOO + default y if BOARD_GOOGLE_WADDLEDOO + config TPM_TIS_ACPI_INTERRUPT int default 4 # GPE0_DW0_4 (GPP_B4) diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 45a1486..3281cad 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -35,6 +35,11 @@ } } + #if CONFIG(VARIANT_HAS_CAMERA_ACPI) + /* Camera */ + #include <variants/acpi/camera.asl> + #endif + /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 0831649..13b6c0c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -95,6 +95,14 @@ /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + /* D12 : WCAM_RST_L */ + PAD_CFG_GPO(GPP_D12, 0, PLTRST), + /* D13 : EN_PP2800_CAMERA */ + PAD_CFG_GPO(GPP_D13, 0, PLTRST), + /* D14 : EN_PP1200_CAMERA */ + PAD_CFG_GPO(GPP_D14, 0, PLTRST), + /* D15 : UCAM_RST_L */ + PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* D16 : HP_INT_ODL*/ PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), /* D17 : EN_SPK */ @@ -102,6 +110,11 @@ /* D18 : I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* E0 : CLK_24M_UCAM */ + PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF2), + /* E2 : CLK_24M_WCAM */ + PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), + /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -149,9 +162,9 @@ /* H5 : AP_I2C_TS_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* H6 : AP_I2C_CAM_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* H7 : AP_I2C_CAM_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* H8 : AP_I2C_AUDIO_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* H9 : AP_I2C_AUDIO_SCL */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl new file mode 100644 index 0000000..aa0d0d5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -0,0 +1,179 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +scope (\_SB.PCI0.I2C3) +{ + Name (STA0, Zero) + //Method to turn of Power Rails + Method (POFF, 0) + { + //Disable PP1200 lane + CTXS(GPP_D13) + //Disable PP2800 lane + CTXS(GPP_D14) + } + Method (PON, 0) + { + //Enable PP1200 lane + STXS(GPP_D13) + //Enable PP2800 lane + STXS(GPP_D14) + } + PowerResource (FCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) // _ON_: Power On + { + //DeAssert Reset + STXS(GPP_D15) + //Enable CLK0 + MCCT(0,1,1) // Clock 0, enable, 19.2MHz + Store(1,STA0) + //Check if another sensor is ON + IF((STA0 + STA1 > 0)) + { + //Do nothing since the other sensor is ON + } + ELSE + { + PON() + } + } + Method (_OFF, 0, Serialized) // _OFF_: Power Off + { + //Assert Reset + CTXS(GPP_D15) + Store(0,STA0) + IF((STA0 + STA1 > 0)) + { + //Do nothing since the other sensor is ON + } + ELSE + { + POFF() + } + } + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA0) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI9734") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 9734 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + FCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + FCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl new file mode 100644 index 0000000..22670b4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA1, Zero) + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) // _ON_: Power On + { + //DeAssert Reset + STXS(GPP_D12) + //Enable CLK1 + MCCT(1,1,1) // Clock 0, enable, 19.2MHz + Store(1,STA1) + //Check if another sensor is ON + IF((STA0 + STA1 > 0)) + { + //Do nothing since the other sensor is ON + } + ELSE + { + PON() + } + } + Method (_OFF, 0, Serialized) // _OFF_: Power Off + { + //Assert Reset + CTXS(GPP_D12) + Store(0,STA1) + IF((STA0 + STA1 > 0)) + { + //Do nothing since the other sensor is ON + } + ELSE + { + POFF() + } + } + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA1) + } + } + Device(CAM1) + { + Name (_HID, "OVTI8856") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x02) + { + 0x15752A00, + 0xABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl new file mode 100644 index 0000000..542a274 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..b30615e --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x01) + { + One, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..da85e26 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/waddledoo/camera.asl b/src/mainboard/google/dedede/variants/baseboard/include/waddledoo/camera.asl new file mode 100644 index 0000000..66a20ec --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/waddledoo/camera.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/camera.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/39360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1 Gerrit-Change-Number: 39360 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2020