Change in coreboot[master]: soc/intel/jasperlake: Add support to generate ACPI GPIO operations

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40536 )

Change subject: soc/intel/jasperlake: Add support to generate ACPI GPIO operations
......................................................................

soc/intel/jasperlake: Add support to generate ACPI GPIO operations

Add support to generate ACPI operations to get/set/clear RX/TX GPIOs.

BUG=b:152936541
TEST=Build and boot the mainboard. Ensure that there are no errors in
the coreboot logs regarding unsupported ACPI GPIO operations.

Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/jasperlake/acpi.c
1 file changed, 37 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40536/1

diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index 29a4619..d8b695b 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -330,3 +330,40 @@
 {
    return MP_IRQ_POLARITY_HIGH;
 }
+
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
+{
+	/* op (gpio_num) */
+	acpigen_emit_namestring(op);
+	acpigen_write_integer(gpio_num);
+	return 0;
+}
+
+static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
+{
+	/* Store (op (gpio_num), Local0) */
+	acpigen_write_store();
+	acpigen_soc_gpio_op(op, gpio_num);
+	acpigen_emit_byte(LOCAL0_OP);
+	return 0;
+}
+
+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.PCI0.GRXS", gpio_num);
+}
+
+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.PCI0.GTXS", gpio_num);
+}
+
+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.PCI0.STXS", gpio_num);
+}
+
+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.PCI0.CTXS", gpio_num);
+}

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40536 )

Change subject: soc/intel/jasperlake: Add support to generate ACPI GPIO operations
......................................................................

Patch Set 1: Code-Review+2

FYI there's supposed to be a follow-up patch from someone else to clean up all of these copy-pasted acpigen_soc_gpio* functions.

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40536 )

Change subject: soc/intel/jasperlake: Add support to generate ACPI GPIO operations
......................................................................

soc/intel/jasperlake: Add support to generate ACPI GPIO operations

Add support to generate ACPI operations to get/set/clear RX/TX GPIOs.

BUG=b:152936541
TEST=Build and boot the mainboard. Ensure that there are no errors in
the coreboot logs regarding unsupported ACPI GPIO operations.

Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/jasperlake/acpi.c
1 file changed, 37 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index 4acd8a6..b390968 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -330,3 +330,40 @@
 {
    return MP_IRQ_POLARITY_HIGH;
 }
+
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
+{
+	/* op (gpio_num) */
+	acpigen_emit_namestring(op);
+	acpigen_write_integer(gpio_num);
+	return 0;
+}
+
+static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
+{
+	/* Store (op (gpio_num), Local0) */
+	acpigen_write_store();
+	acpigen_soc_gpio_op(op, gpio_num);
+	acpigen_emit_byte(LOCAL0_OP);
+	return 0;
+}
+
+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.PCI0.GRXS", gpio_num);
+}
+
+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.PCI0.GTXS", gpio_num);
+}
+
+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.PCI0.STXS", gpio_num);
+}
+
+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.PCI0.CTXS", gpio_num);
+}