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Change in coreboot[master]: mb/intel/ehlcrb: Remove ChromeOS EC related headers
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48119 ) Change subject: mb/intel/ehlcrb: Remove ChromeOS EC related headers ...................................................................... mb/intel/ehlcrb: Remove ChromeOS EC related headers Since EHL does not support ChromeOS, this patch removes ChromeOS EC related headers (ec.h & gpio.h) and #includes. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I9c0c3722065c041769081f3d564646ce6a565a9b --- M src/mainboard/intel/elkhartlake_crb/bootblock.c M src/mainboard/intel/elkhartlake_crb/dsdt.asl M src/mainboard/intel/elkhartlake_crb/mainboard.c D src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h D src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c 7 files changed, 0 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48119/1 diff --git a/src/mainboard/intel/elkhartlake_crb/bootblock.c b/src/mainboard/intel/elkhartlake_crb/bootblock.c index a8f7e41..c39a8ff 100644 --- a/src/mainboard/intel/elkhartlake_crb/bootblock.c +++ b/src/mainboard/intel/elkhartlake_crb/bootblock.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <bootblock_common.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/elkhartlake_crb/dsdt.asl b/src/mainboard/intel/elkhartlake_crb/dsdt.asl index dcbf380..9dd33a8 100644 --- a/src/mainboard/intel/elkhartlake_crb/dsdt.asl +++ b/src/mainboard/intel/elkhartlake_crb/dsdt.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <baseboard/ec.h> -#include <baseboard/gpio.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c index efba386..a8a1cc2 100644 --- a/src/mainboard/intel/elkhartlake_crb/mainboard.c +++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> #include <intelblocks/pcr.h> diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h deleted file mode 100644 index f05cb77..0000000 --- a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_EC_H__ -#define __BASEBOARD_EC_H__ - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* - * EC can wake from S3 with lid or power button or key press or - * mode change event. - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h deleted file mode 100644 index de0adf6..0000000 --- a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c index fe2aff7..003a6a5 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c index cca208e..8446e6c 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <baseboard/gpio.h> #include <console/console.h> #include <gpio.h> #include <soc/meminit.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c0c3722065c041769081f3d564646ce6a565a9b Gerrit-Change-Number: 48119 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/intel/ehlcrb: Remove ChromeOS EC support EHL smihandler
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48118 ) Change subject: mb/intel/ehlcrb: Remove ChromeOS EC support EHL smihandler ...................................................................... mb/intel/ehlcrb: Remove ChromeOS EC support EHL smihandler Since there is no ChromeOS support for EHL, removing ChromeOS EC codes from smihandler.c. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Id474c3b04a82c03dda6514cc4565b58fb790b9c1 --- M src/mainboard/intel/elkhartlake_crb/Makefile.inc D src/mainboard/intel/elkhartlake_crb/smihandler.c 2 files changed, 0 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/48118/1 diff --git a/src/mainboard/intel/elkhartlake_crb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/Makefile.inc index cf9e1c9..69a9368 100644 --- a/src/mainboard/intel/elkhartlake_crb/Makefile.inc +++ b/src/mainboard/intel/elkhartlake_crb/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += mainboard.c ramstage-y += board_id.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/elkhartlake_crb/smihandler.c b/src/mainboard/intel/elkhartlake_crb/smihandler.c deleted file mode 100644 index be0066a..0000000 --- a/src/mainboard/intel/elkhartlake_crb/smihandler.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <cpu/x86/smm.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/smm.h> -#include <elog.h> -#include <intelblocks/smihandler.h> -#include <baseboard/ec.h> - -void mainboard_smi_espi_handler(void) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_process_events(); -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, - MAINBOARD_EC_S5_WAKE_EVENTS); -} - -int mainboard_smi_apmc(u8 apmc) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); - - return 0; -} - -void elog_gsmi_cb_mainboard_log_wake_source(void) -{ - if (CONFIG(EC_GOOGLE_CHROMEEC)) - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id474c3b04a82c03dda6514cc4565b58fb790b9c1 Gerrit-Change-Number: 48118 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/intel/ehlcrb: Remove ChromeOS support from mainboard
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48117 ) Change subject: mb/intel/ehlcrb: Remove ChromeOS support from mainboard ...................................................................... mb/intel/ehlcrb: Remove ChromeOS support from mainboard Since ChromeOS is not officially supported for EHL, removing ChromeOS related codes. Here are the change details: - Remove ChromeOS related kconfigs, including SOC_INTEL_CSE_LITE_SKU which has dependency on ChromeOS flag - Remove chromeos.c file & chromeos.c codes from makefile.c - Remove ChromeOS dsdt related codes from dsdt.asl & mainboard.c - Remove ChromeOS GPIO related codes from variants.h & gpio.c Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816 --- M src/mainboard/intel/elkhartlake_crb/Kconfig M src/mainboard/intel/elkhartlake_crb/Makefile.inc D src/mainboard/intel/elkhartlake_crb/chromeos.c M src/mainboard/intel/elkhartlake_crb/dsdt.asl M src/mainboard/intel/elkhartlake_crb/mainboard.c M src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c 7 files changed, 0 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/48117/1 diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig index 14c2b93..07dc311 100644 --- a/src/mainboard/intel/elkhartlake_crb/Kconfig +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig @@ -16,11 +16,9 @@ select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_ELKHARTLAKE select SOC_INTEL_COMMON_BLOCK_DTT - select SOC_INTEL_CSE_LITE_SKU config MAINBOARD_DIR string @@ -46,16 +44,6 @@ int default 512 -config CHROMEOS - bool - default y - select GBB_FLAG_FORCE_DEV_SWITCH_ON - select GBB_FLAG_FORCE_DEV_BOOT_USB - select GBB_FLAG_FORCE_DEV_BOOT_LEGACY - select GBB_FLAG_FORCE_MANUAL_RECOVERY - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select HAS_RECOVERY_MRC_CACHE - config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/intel/elkhartlake_crb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/Makefile.inc index 2ac1b07..cf9e1c9 100644 --- a/src/mainboard/intel/elkhartlake_crb/Makefile.inc +++ b/src/mainboard/intel/elkhartlake_crb/Makefile.inc @@ -3,15 +3,10 @@ subdirs-y += spd bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.c b/src/mainboard/intel/elkhartlake_crb/chromeos.c deleted file mode 100644 index c59fac8..0000000 --- a/src/mainboard/intel/elkhartlake_crb/chromeos.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <boot/coreboot_tables.h> -#include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ - -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/elkhartlake_crb/dsdt.asl b/src/mainboard/intel/elkhartlake_crb/dsdt.asl index 2faa511..dcbf380 100644 --- a/src/mainboard/intel/elkhartlake_crb/dsdt.asl +++ b/src/mainboard/intel/elkhartlake_crb/dsdt.asl @@ -29,21 +29,5 @@ } } -#if CONFIG(CHROMEOS) - /* Chrome OS specific */ - #include <vendorcode/google/chromeos/acpi/chromeos.asl> -#endif - -#if CONFIG(EC_GOOGLE_CHROMEEC) - /* Chrome OS Embedded Controller */ - Scope (\_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include <ec/google/chromeec/acpi/superio.asl> - /* ACPI code for EC functions */ - #include <ec/google/chromeec/acpi/ec.asl> - } -#endif - #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c index 315d47d..efba386 100644 --- a/src/mainboard/intel/elkhartlake_crb/mainboard.c +++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c @@ -7,7 +7,6 @@ #include <soc/gpio.h> #include <soc/pcr_ids.h> #include <smbios.h> -#include <vendorcode/google/chromeos/chromeos.h> #define SERIAL_IO_PCR_GPPRVRW4 0x60C @@ -23,11 +22,6 @@ pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - const char *smbios_system_sku(void) { static const char *sku_str = "sku2147483647"; /* sku{0-1} */ @@ -36,5 +30,4 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h index 7db40a9..46bf375 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h @@ -6,13 +6,11 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next 3 sets of functions return the gpio table and fill in the number * of entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); /* This function returns SPD related FSP-M mainboard configs */ const struct mb_cfg *variant_memcfg_config(uint8_t board_id); diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c index f01202b..fe2aff7 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -25,13 +25,3 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816 Gerrit-Change-Number: 48117 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/intel/ehlcrb: Add missing 'include <console/console.h>'
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48116 ) Change subject: mb/intel/ehlcrb: Add missing 'include <console/console.h>' ...................................................................... mb/intel/ehlcrb: Add missing 'include <console/console.h>' "Die()" needs <console/console.h>, as per this patch: https://review.coreboot.org/c/coreboot/+/45540 Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I0f9fae4a1e43477ca8e78ebbebd8c0729f8b7668 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48116/1 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c index e764fdc..cca208e 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <console/console.h> #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f9fae4a1e43477ca8e78ebbebd8c0729f8b7668 Gerrit-Change-Number: 48116 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/intel/ehlcrb: Add initial mainboard code
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47707 ) Change subject: mb/intel/ehlcrb: Add initial mainboard code ...................................................................... mb/intel/ehlcrb: Add initial mainboard code This is a initial mainboard code cloned entirely from jasperlake_rvp aimed to serve as base for further mainboard check-ins. This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/37868 List of changes on top off initial jasperlake_rvp clone: 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jslrvp" with "ehlcrb" 4. Remove unwanted SPD file, add empty SPD as placeholder 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config 7. Empty GPIO configurations, to be filled as per board 8. Empty memory.c configurations, to be filled as per board 9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB 10. Replace jslrvp variant with ehlcrb variant Changes to follow on top of this: 1. Add correct memory parameters, add SPDs 2. Clean up devicetree as per tigerlake SOC 3. Add GPIO support 4. Update ehl fmd file to replace 32MB chromeos.fmd Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I2cbe9f12468318680b148739edec5222582e42a0 --- A src/mainboard/intel/elkhartlake_crb/Kconfig A src/mainboard/intel/elkhartlake_crb/Kconfig.name A src/mainboard/intel/elkhartlake_crb/Makefile.inc A src/mainboard/intel/elkhartlake_crb/board_id.c A src/mainboard/intel/elkhartlake_crb/board_id.h A src/mainboard/intel/elkhartlake_crb/board_info.txt A src/mainboard/intel/elkhartlake_crb/bootblock.c A src/mainboard/intel/elkhartlake_crb/chromeos.c A src/mainboard/intel/elkhartlake_crb/chromeos.fmd A src/mainboard/intel/elkhartlake_crb/dsdt.asl A src/mainboard/intel/elkhartlake_crb/mainboard.c A src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c A src/mainboard/intel/elkhartlake_crb/smihandler.c A src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc A src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex A src/mainboard/intel/elkhartlake_crb/spd/spd.h A src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c 23 files changed, 1,091 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47707/1 diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig new file mode 100644 index 0000000..6456df7 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig @@ -0,0 +1,75 @@ +if BOARD_INTEL_ELKHARTLAKE_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DPTF_USE_EISA_HID + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_ACPI + select HAVE_SPD_IN_CBFS + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ELKHARTLAKE + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_CSE_LITE_SKU + +config MAINBOARD_DIR + string + default "intel/elkhartlake_crb" + +config VARIANT_DIR + string + default "ehlcrb" if BOARD_INTEL_ELKHARTLAKE_CRB + +config MAINBOARD_PART_NUMBER + string + default "ehlcrb" + +config MAINBOARD_FAMILY + string + default "Intel_ehlcrb" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2 + +config UART_FOR_CONSOLE + int + default 2 if INTEL_LPSS_UART_FOR_CONSOLE + default 0 + +config TPM_TIS_ACPI_INTERRUPT + int + default 45 # GPE0_DW1_13 (GPP_H13) +endif diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig.name b/src/mainboard/intel/elkhartlake_crb/Kconfig.name new file mode 100644 index 0000000..3a20b88 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_ELKHARTLAKE_CRB + bool "Elkhartlake LPDDR4x CRB" diff --git a/src/mainboard/intel/elkhartlake_crb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/Makefile.inc new file mode 100644 index 0000000..2ac1b07 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/Makefile.inc @@ -0,0 +1,24 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += mainboard.c +ramstage-y += board_id.c + +smm-y += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/elkhartlake_crb/board_id.c b/src/mainboard/intel/elkhartlake_crb/board_id.c new file mode 100644 index 0000000..90609ff --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/board_id.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <ec/google/chromeec/ec.h> +#include <stdint.h> + +#include "board_id.h" + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* + * Get Board ID via EC I/O port write/read + * Board id is 5 bit, so mask other bits while returning board id. + */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + id = get_board_id_via_ext_ec(); + } else { + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + + return (id & 0x1f); +} diff --git a/src/mainboard/intel/elkhartlake_crb/board_id.h b/src/mainboard/intel/elkhartlake_crb/board_id.h new file mode 100644 index 0000000..85c7c85 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/board_id.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/elkhartlake_crb/board_info.txt b/src/mainboard/intel/elkhartlake_crb/board_info.txt new file mode 100644 index 0000000..f2c19c0 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Elkhartlake crb +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/elkhartlake_crb/bootblock.c b/src/mainboard/intel/elkhartlake_crb/bootblock.c new file mode 100644 index 0000000..a8f7e41 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.c b/src/mainboard/intel/elkhartlake_crb/chromeos.c new file mode 100644 index 0000000..c59fac8 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/chromeos.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.fmd b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd new file mode 100644 index 0000000..05f4592 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd @@ -0,0 +1,43 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x600000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x57F000 + } + SI_BIOS@0x600000 0xA00000 { + RW_SECTION_A@0x0 0x2d0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bffc0 + RW_FWID_A@0x2cffc0 0x40 + } + RW_SECTION_B@0x2d0000 0x2d0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bffc0 + RW_FWID_B@0x2cffc0 0x40 + } + RW_MISC@0x5a0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0x5d0000 0x30000 + WP_RO@0x600000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/intel/elkhartlake_crb/dsdt.asl b/src/mainboard/intel/elkhartlake_crb/dsdt.asl new file mode 100644 index 0000000..2faa511 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/dsdt.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/elkhartlake/acpi/southbridge.asl> + } + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c new file mode 100644 index 0000000..315d47d --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <intelblocks/pcr.h> +#include <soc/gpio.h> +#include <soc/pcr_ids.h> +#include <smbios.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define SERIAL_IO_PCR_GPPRVRW4 0x60C + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + if (CONFIG(DRIVERS_INTEL_MIPI_CAMERA)) + pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +const char *smbios_system_sku(void) +{ + static const char *sku_str = "sku2147483647"; /* sku{0-1} */ + return sku_str; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c new file mode 100644 index 0000000..1354edf --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include "board_id.h" + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* ToDo : Fill FSP-M spd related memory params */ +} diff --git a/src/mainboard/intel/elkhartlake_crb/smihandler.c b/src/mainboard/intel/elkhartlake_crb/smihandler.c new file mode 100644 index 0000000..be0066a --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/smihandler.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> +#include <elog.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); +} diff --git a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc new file mode 100644 index 0000000..1af6515 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = empty # 0b000 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex b/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/spd.h b/src/mainboard/intel/elkhartlake_crb/spd/spd.h new file mode 100644 index 0000000..f667e74 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/spd.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <stdint.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); +void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..f05cb77 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..de0adf6 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..b7603ccd --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num); +const struct mb_cfg *variant_memcfg_config(uint8_t board_id); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc new file mode 100644 index 0000000..641e814 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb new file mode 100644 index 0000000..4611685 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -0,0 +1,474 @@ +chip soc/intel/elkhartlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_H" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # Display related UPDs + # Select eDP for port A (1 = eDP, 2 = MIPI) + register "DdiPortAConfig" = "1" + + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # USB2 Type A port1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN + register "usb2_ports[6]" = "USB2_PORT_MID(OC2)" # USB2 Type A port3 + register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # USB3 WWAN + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + + # PCIe port 1 for M.2 E-key WLAN + # Enable Root Port 4(x4) for NVMe + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[4]" = "1" + + # Enable ClkReqDetect 1 for WLAN + # Enable ClkReqDetect 4 for NVMe + register "PcieRpClkReqDetect[1]" = "1" + register "PcieRpClkReqDetect[4]" = "1" + + register "PcieClkSrcUsage[0]" = "0x04" + register "PcieClkSrcUsage[1]" = "0x01" + register "PcieClkSrcUsage[2]" = "0xFF" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" + + register "PcieClkSrcClkReq[0]" = "0x00" + register "PcieClkSrcClkReq[1]" = "0x01" + register "PcieClkSrcClkReq[2]" = "0x02" + register "PcieClkSrcClkReq[3]" = "0x03" + register "PcieClkSrcClkReq[4]" = "0x04" + register "PcieClkSrcClkReq[5]" = "0x05" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Enable DPTF + register "dptf_enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + # Enable S0ix + register "s0ix_enable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "VGPIO_39" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # SA Thermal device + + device pci 05.0 on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Lower"" + register "type" = "UPC_TYPE_A" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 4"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Upper"" + register "type" = "UPC_TYPE_A" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Lower"" + register "type" = "UPC_TYPE_A" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Upper"" + register "type" = "UPC_TYPE_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""WLAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused1"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused2"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused3"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi + device pci 14.5 on end # SDCard + device pci 15.0 on + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # I2C #0 Audio + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 off end # SATA + device pci 19.0 on # I2C #4 Cam 0 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI2740"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 2740 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset + register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 10 on end + end + end + device pci 19.1 on # I2C #5 Cam 1 and VCM + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + device i2c 0C on end + end + end + + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 - WLAN + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 - NVMe + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)" + device spi 0 on end + end + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c new file mode 100644 index 0000000..f01202b --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ToDo: Fill gpio configurations */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* ToDo: Fill early gpio configurations */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c new file mode 100644 index 0000000..e764fdc --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +/* ToDo : Fill EHL related memory configs */ + +const struct mb_cfg *variant_memcfg_config(uint8_t board_id) +{ + /* ToDo : Fill EHL related memory configs */ + + die("unsupported board id : 0x%x\n", board_id); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cbe9f12468318680b148739edec5222582e42a0 Gerrit-Change-Number: 47707 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: soc/intel/elkhartlake: Fix EHL mainboard build fail errors
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47804 ) Change subject: soc/intel/elkhartlake: Fix EHL mainboard build fail errors ...................................................................... soc/intel/elkhartlake: Fix EHL mainboard build fail errors When EHL initial mainboard patch is uploaded, there are some build errors caused by EHL soc codes. Here are the fixes: 1. include gpio_op.asl to resolve undefined variables in scs.asl 2. remove unused variables in fsp_params.c 3. rearrage sequences of #includes to fix build dependency of soc/gpio_defs.h in intelblocks/gpio.h 4. add the __weak to mainboard_memory_init_params function Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 --- M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/include/soc/gpio.h M src/soc/intel/elkhartlake/romstage/fsp_params.c 4 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47804/1 diff --git a/src/soc/intel/elkhartlake/acpi/gpio.asl b/src/soc/intel/elkhartlake/acpi/gpio.asl index ac0d1df..27cb503 100644 --- a/src/soc/intel/elkhartlake/acpi/gpio.asl +++ b/src/soc/intel/elkhartlake/acpi/gpio.asl @@ -3,6 +3,7 @@ #include <intelblocks/gpio.h> #include <soc/gpio_defs.h> #include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> #include <soc/irq.h> #include <soc/pcr_ids.h> diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 3d740fb..83a3699 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -44,17 +44,13 @@ static void parse_devicetree(FSP_S_CONFIG *params) { - const struct soc_intel_elkhartlake_config *config = config_of_soc(); /* TODO: Update with UPD override as FSP matures */ } /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - unsigned int i; - struct device *dev; FSP_S_CONFIG *params = &supd->FspsConfig; - struct soc_intel_elkhartlake_config *config = config_of_soc(); /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); diff --git a/src/soc/intel/elkhartlake/include/soc/gpio.h b/src/soc/intel/elkhartlake/include/soc/gpio.h index 6cca742..367df82 100644 --- a/src/soc/intel/elkhartlake/include/soc/gpio.h +++ b/src/soc/intel/elkhartlake/include/soc/gpio.h @@ -3,8 +3,8 @@ #ifndef _SOC_ELKHARTLAKE_GPIO_H_ #define _SOC_ELKHARTLAKE_GPIO_H_ -#include <intelblocks/gpio.h> #include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> #define CROS_GPIO_NAME "INT34C8" #define CROS_GPIO_COMM0_NAME "INT34C8:00" diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 3961dfc..0fa8451 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -25,7 +25,7 @@ mainboard_memory_init_params(mupd); } -void mainboard_memory_init_params(FSPM_UPD *mupd) +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) { /* TODO: Update later together with UPD updates */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/47804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 Gerrit-Change-Number: 47804 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR
by Patrick Rudolph (Code Review) 10 Dec '20

10 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48178 ) Change subject: cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR ...................................................................... cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/exit32.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48178/1 diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 6722cfd..d35eb13 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -24,8 +24,9 @@ drop_longmode: /* Ensure cache is clean. */ +#if defined(__RAMSTAGE__) wbinvd - +#endif /* Set 32-bit code segment and ss */ mov $CODE_SEG, %rcx /* SetCodeSelector32 will drop us to protected mode on return */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91 Gerrit-Change-Number: 48178 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: arch/x86/smbios.c: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 10 Dec '20

10 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48454 ) Change subject: arch/x86/smbios.c: Fix compilation on x86_64 ...................................................................... arch/x86/smbios.c: Fix compilation on x86_64 Change-Id: I07780f9a6fa577d7b6bb63884071a7e1ce1bdbfa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48454/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index aabeb10..aaf989d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -414,7 +414,7 @@ #if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES) u32 version_offset = (u32)smbios_string_table_len(t->eos); /* SMBIOS offsets start at 1 rather than 0 */ - chromeos_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1); + chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1); #endif t->bios_version = smbios_add_string(t->eos, get_bios_version()); uint32_t rom_size = CONFIG_ROM_SIZE; -- To view, visit https://review.coreboot.org/c/coreboot/+/48454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07780f9a6fa577d7b6bb63884071a7e1ce1bdbfa Gerrit-Change-Number: 48454 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: drivers/crb/tpm: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 10 Dec '20

10 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48453 ) Change subject: drivers/crb/tpm: Fix compilation on x86_64 ...................................................................... drivers/crb/tpm: Fix compilation on x86_64 Change-Id: I19cce90f44b54e4eb6dd8517793ae887f0bd1e22 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/crb/tpm.c M src/drivers/crb/tpm.h 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/48453/1 diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index 476b62b..fcefe96 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -43,10 +43,11 @@ control_area.cancel = read32(CRB_REG(cur_loc, CRB_REG_CANCEL)); control_area.interrupt_control = read64(CRB_REG(cur_loc, CRB_REG_INT_CTRL)); control_area.command_size = read32(CRB_REG(cur_loc, CRB_REG_CMD_SIZE)); - control_area.command_bfr = (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR)); + control_area.command_bfr = + (void *)(uintptr_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR)); control_area.response_size = read32(CRB_REG(cur_loc, CRB_REG_RESP_SIZE)); control_area.response_bfr = - (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR)); + (void *)(uintptr_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR)); } /* Wait for Reg to be expected Value */ diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h index 0d68384..c43beb6 100644 --- a/src/drivers/crb/tpm.h +++ b/src/drivers/crb/tpm.h @@ -6,7 +6,7 @@ #define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS #define CRB_REG(LOCTY, REG) \ - (void *)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG) + (void *)(uintptr_t)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG) /* hardware registers */ #define CRB_REG_LOC_STATE 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/48453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cce90f44b54e4eb6dd8517793ae887f0bd1e22 Gerrit-Change-Number: 48453 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Furquan Shaikh (Code Review) 10 Dec '20

10 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > > > You really should check the history of drivers/wifi/generic, commit d436750 for example... > > > > Well, the history is one thing. The current code is what > > matters however. How about you read that? > > I did ;) Actually I meant that one change, the wording is just misleading One major difference in the way UART driver is being handled in this CL and how CNVi device is handled is: For CNVi: - PCI operations are still performed as part of the PCI driver for the CNVi controller - ACPI operations are performed as part of the chip driver written for the dummy device under CNVi controller For UART: - This change performs PCI and ACPI operations on the parent of the dummy device. This does not work for the platforms that do not add the dummy device in devicetree/overridetree. There are other drivers in coreboot that handle this in a similar way. Example: ISH. PCI operations are handled by PCI driver (either default PCI ops or by the special PCI driver provided in soc/intel) and ACPI operations are handled by chip driver implemented as part of src/drivers. One way to handle the UART situation in a similar way would be to provide only the PCI operations in PCI driver provided by soc/intel/common/block/uart and implement a chip driver in drivers/intel_lpss_uart or something similar that generates the required ACPI tables. > > > Well, if we rework the driver/chip modeling like you proposed, we indeed can get rid of any fake devices. Also I'm not sure if we want to mix "drivers" and "chips" then, because it's not always certain which model needs to be used. Or would we keep chips for real devices then and only use "driver" when the port is the device? > > Where would we place driver options then? I would be curious to understand how the new model would work too. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 06:53:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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