Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48178 )
Change subject: cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR
......................................................................
cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR
Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/x86/64bit/exit32.inc
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48178/1
diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc
index 6722cfd..d35eb13 100644
--- a/src/cpu/x86/64bit/exit32.inc
+++ b/src/cpu/x86/64bit/exit32.inc
@@ -24,8 +24,9 @@
drop_longmode:
/* Ensure cache is clean. */
+#if defined(__RAMSTAGE__)
wbinvd
-
+#endif
/* Set 32-bit code segment and ss */
mov $CODE_SEG, %rcx
/* SetCodeSelector32 will drop us to protected mode on return */
--
To view, visit https://review.coreboot.org/c/coreboot/+/48178
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91
Gerrit-Change-Number: 48178
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 )
Change subject: soc/intel/common/block/uart: rework to use dummy device
......................................................................
Patch Set 3:
> > > You really should check the history of drivers/wifi/generic, commit d436750 for example...
> >
> > Well, the history is one thing. The current code is what
> > matters however. How about you read that?
>
> I did ;) Actually I meant that one change, the wording is just misleading
One major difference in the way UART driver is being handled in this CL and how CNVi device is handled is:
For CNVi:
- PCI operations are still performed as part of the PCI driver for the CNVi controller
- ACPI operations are performed as part of the chip driver written for the dummy device under CNVi controller
For UART:
- This change performs PCI and ACPI operations on the parent of the dummy device. This does not work for the platforms that do not add the dummy device in devicetree/overridetree.
There are other drivers in coreboot that handle this in a similar way. Example: ISH. PCI operations are handled by PCI driver (either default PCI ops or by the special PCI driver provided in soc/intel) and ACPI operations are handled by chip driver implemented as part of src/drivers.
One way to handle the UART situation in a similar way would be to provide only the PCI operations in PCI driver provided by soc/intel/common/block/uart and implement a chip driver in drivers/intel_lpss_uart or something similar that generates the required ACPI tables.
>
>
> Well, if we rework the driver/chip modeling like you proposed, we indeed can get rid of any fake devices. Also I'm not sure if we want to mix "drivers" and "chips" then, because it's not always certain which model needs to be used. Or would we keep chips for real devices then and only use "driver" when the port is the device?
>
> Where would we place driver options then?
I would be curious to understand how the new model would work too.
--
To view, visit https://review.coreboot.org/c/coreboot/+/48385
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7
Gerrit-Change-Number: 48385
Gerrit-PatchSet: 3
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 10 Dec 2020 06:53:44 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 )
Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT
......................................................................
Patch Set 70:
(3 comments)
https://review.coreboot.org/c/coreboot/+/27369/70/Documentation/soc/intel/u…
File Documentation/soc/intel/ucode_update/microcode_update_model.md:
PS70:
I haven't got a chance to go through the doc and the changes again. I need to think through the flows and also the impact on hardware changes. Since this is not targeted for TGL, I would appreciate if we can hold on pushing this in for some time (Probably end of this month is earliest I can get to this).
https://review.coreboot.org/c/coreboot/+/27369/70/src/soc/intel/common/base…
File src/soc/intel/common/basecode/fw_update/ucode_update.c:
https://review.coreboot.org/c/coreboot/+/27369/70/src/soc/intel/common/base…
PS70, Line 131: 0x32
This needs to be added to vboot library first.
https://review.coreboot.org/c/coreboot/+/27369/70/src/soc/intel/common/base…
PS70, Line 264: BS_PRE_DEVICE
Why is this stage chosen for ucode update? CSE update is moving to romstage. I think this should be performed as early as possible (at least along with CSE update in romstage).
--
To view, visit https://review.coreboot.org/c/coreboot/+/27369
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655
Gerrit-Change-Number: 27369
Gerrit-PatchSet: 70
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>
Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com>
Gerrit-CC: Nico Huber <nico.h(a)gmx.de>
Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com>
Gerrit-Comment-Date: Thu, 10 Dec 2020 06:38:47 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment