coreboot-gerrit December 2020

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Change in coreboot[master]: soc/amd/picasso/reset: remove leftover PCI includes
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48486 ) Change subject: soc/amd/picasso/reset: remove leftover PCI includes ...................................................................... soc/amd/picasso/reset: remove leftover PCI includes On Stoneyridge some PCI registers were accessed, but on Picasso this is no longer the case. Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/reset.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48486/1 diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 7a0074c..dea166a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -3,9 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <reset.h> -#include <soc/pci_devs.h> #include <soc/reset.h> -#include <device/pci_ops.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Gerrit-Change-Number: 48486 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Drop use of SPD cache for puff-based variants
by Matt DeVillier (Code Review) 10 Dec '20

10 Dec '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47899 ) Change subject: mb/google/hatch: Drop use of SPD cache for puff-based variants ...................................................................... mb/google/hatch: Drop use of SPD cache for puff-based variants Commit 74109923 [mb/google/puff: add a region to cache SPD data] implemented a mechanism to cache SODIMM SPD data in a FMAP region, but it's actually slower than simply letting FSP (vs coreboot) read the SPD data via smbus, so drop it. This has the side effect of removing the requirement for a RW_SPD_CACHE FMAP region, without which these boards would not boot at all - allowing the default FMAP to be used for non-ChromeOS builds. Test: build/boot WYVERN variant, check boot times via cbmem: w/SPD caching: ~722 ms w/FSP reading: ~627 ms Change-Id: I4e4db9ba9fdb0fa9fafb2645819b111d381b5756 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/romstage_spd_smbus.c 1 file changed, 5 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47899/1 diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index e697379..1db9c54 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,72 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> -#include <spd_bin.h> -#include <spd_cache.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; variant_memory_params(&memcfg); - /* Read spd block to get memory config */ - struct spd_block blk = { - .addr_map = { 0x50, 0x52, }, - }; - - uint8_t *spd_cache; - size_t spd_cache_sz; - bool need_update_cache = false; - bool dimm_changed = true; - - /* load spd cache from RW_SPD_CACHE */ - if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) { - if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) { - printk(BIOS_WARNING, "Invalid SPD cache\n"); - } else { - dimm_changed = check_if_dimm_changed(spd_cache, &blk); - if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) { - /* Set mrc_cache as invalid */ - printk(BIOS_INFO, "Set mrc_cache as invalid\n"); - memupd->FspmArchUpd.NvsBufferPtr = NULL; - } - } - need_update_cache = true; - } - - if (!dimm_changed) { - spd_fill_from_cache(spd_cache, &blk); - } else { - /* Access memory info through SMBUS. */ - get_spd_smbus(&blk); - - if (need_update_cache && update_spd_cache(&blk) == CB_ERR) - printk(BIOS_WARNING, "update SPD cache failed\n"); - } - - if (blk.spd_array[0] == NULL) { - memcfg.spd[0].read_type = NOT_EXISTING; - } else { - memcfg.spd[0].read_type = READ_SPD_MEMPTR; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; - } - + /* DDR4 SODIMMs located at CH0D0, CH1D0 */ + memcfg.spd[0].read_type = READ_SMBUS; + memcfg.spd[0].spd_spec.spd_smbus_address = 0xa0; memcfg.spd[1].read_type = NOT_EXISTING; - - if (blk.spd_array[1] == NULL) { - memcfg.spd[2].read_type = NOT_EXISTING; - } else { - memcfg.spd[2].read_type = READ_SPD_MEMPTR; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; - } - + memcfg.spd[2].read_type = READ_SMBUS; + memcfg.spd[2].spd_spec.spd_smbus_address = 0xa4; memcfg.spd[3].read_type = NOT_EXISTING; - dump_spd_info(&blk); /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ memcfg.vref_ca_config = 2; -- To view, visit https://review.coreboot.org/c/coreboot/+/47899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e4db9ba9fdb0fa9fafb2645819b111d381b5756 Gerrit-Change-Number: 47899 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Nico Huber (Code Review) 10 Dec '20

10 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: I only now realized that you stripped the most important part when quoting me: > > > > What > > > > about all the mainboards that use this driver by properly > > > > matching the PCI IDs? Maybe you misunderstood. This driver is not only used via a `chip` entry in the devicetree. It is foremost used as a usual PCI driver. $ git grep 'device pci 1[89e].* on.*UART' src/mainboard/ This says there are at least 120 cases in the tree that potentially use it and might break due to this change. The driver would even be used if the device is not mentioned in the dt at all, it's PCI. > > > > I can't say if this is working, or even if it can work. > > > > > > I wonder how this one is different from drivers/wifi/generic, which uses the same dummy model? > > > > Except it doesn't? It does not use a generic device below > > a PCI device. And it checks the device path so it doesn't > > attach PCI ops to a non-PCI device in the first place. > > What is this then? > > device pci 14.3 on > chip drivers/wifi/generic > register "wake" = "GPE0_PME_B0" > device generic 0 on end > end > end # CNVi wifi Sorry, my bad. I didn't realize it's used with two different topologies. The difference is that the driver is prepared for that and attaches the CNVi ops only in case of the generic device. And only then the parent is queried. Here, OTOH, you always use the parent, no matter the topology. > > You really should check the history of drivers/wifi/generic, commit d436750 for example... Well, the history is one thing. The current code is what matters however. How about you read that? -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 00:09:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 3: > > > > > Patch Set 3: Code-Review-2 > > > > > > I can't say if this is working, or even if it can work. > > > > I wonder how this one is different from drivers/wifi/generic, which uses the same dummy model? > > Except it doesn't? It does not use a generic device below > a PCI device. And it checks the device path so it doesn't > attach PCI ops to a non-PCI device in the first place. What is this then? device pci 14.3 on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end end # CNVi wifi You really should check the history of drivers/wifi/generic, commit d436750 for example... > > > > > > Another idea to solve one of the issues this chip driver > > > currently handles: Allow to specify the PCI IDs in the > > > devicetree if the device is `hidden`. > > > > Huh, that is already possible (devid) > > I meant a proper solution, not a "register" hack. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Dec 2020 23:38:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Nico Huber (Code Review) 10 Dec '20

10 Dec '20

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Change in coreboot[master]: Makefile.inc: Fix $(@) shows empty issue
by Xi Chen (Code Review) 10 Dec '20

10 Dec '20

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48201 ) Change subject: Makefile.inc: Fix $(@) shows empty issue ...................................................................... Makefile.inc: Fix $(@) shows empty issue When passing $(@) to printf, $(@) is replaced by empty string, need to add extra '$'. For example: cbfs-files-processor-struct= \ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ # ** @(@) is empty string instead of $(2) ** printf " CC+STRIP $(@) \n"; \ # ** $$(@) == $(2) ** printf " CC+STRIP $$(@) \n"; \ ......) Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: Id6a66e25d7dfe8fe6410e517593ed22a438d2f82 --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48201/1 diff --git a/Makefile.inc b/Makefile.inc index 9273961..38af658 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -336,7 +336,7 @@ # arg2: binary file cbfs-files-processor-struct= \ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ - printf " CC+STRIP $(@)\n"; \ + printf " CC+STRIP $$(<) --> $$(@) \n"; \ $(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \ $(OBJCOPY_ramstage) -O binary $(2).tmp $(2); \ rm -f $(2).tmp) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/48201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6a66e25d7dfe8fe6410e517593ed22a438d2f82 Gerrit-Change-Number: 48201 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > Patch Set 3: Code-Review-2 > > I can't say if this is working, or even if it can work. I wonder how this one is different from drivers/wifi/generic, which uses the same dummy model? > about all the mainboards that use this driver by properly > matching the PCI IDs? > > TBH, I don't like to see any more hacks with fake chips or > devices. The old model of attaching drivers via PCI IDs > served us well for a long time. Now Intel makes more and > more PCI devices that actually aren't PCI devices. I think > it's time we adapt and find a new model to attach drivers. > > As we have chipset devicetrees now, it makes things easy > to match device drivers by name. Just like we do it for > chip drivers. So my idea would be to do something like > this: > > device pci 19.2 hidden > driver soc/intel/common/block/uart > end > > And then name the `struct pci_driver` > `soc_intel_common_block_uart_driver` accordingly. > > Just from the top of my head. Alternative suggestions > are most welcome :) If we're going to do that, we should do this tree-wide, else we have again multiple different models. > Another idea to solve one of the issues this chip driver > currently handles: Allow to specify the PCI IDs in the > devicetree if the device is `hidden`. Huh, that is already possible (devid) -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Dec 2020 23:16:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Nico Huber (Code Review) 10 Dec '20

10 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: Code-Review-2 I can't say if this is working, or even if it can work. What about all the mainboards that use this driver by properly matching the PCI IDs? TBH, I don't like to see any more hacks with fake chips or devices. The old model of attaching drivers via PCI IDs served us well for a long time. Now Intel makes more and more PCI devices that actually aren't PCI devices. I think it's time we adapt and find a new model to attach drivers. As we have chipset devicetrees now, it makes things easy to match device drivers by name. Just like we do it for chip drivers. So my idea would be to do something like this: device pci 19.2 hidden driver soc/intel/common/block/uart end And then name the `struct pci_driver` `soc_intel_common_block_uart_driver` accordingly. Just from the top of my head. Alternative suggestions are most welcome :) Another idea to solve one of the issues this chip driver currently handles: Allow to specify the PCI IDs in the devicetree if the device is `hidden`. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Dec 2020 23:01:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/chili/base: Fix state of PCI devices
by Felix Singer (Code Review) 09 Dec '20

09 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48388 ) Change subject: mb/siemens/chili/base: Fix state of PCI devices ...................................................................... mb/siemens/chili/base: Fix state of PCI devices The PCI devices P2SB and PMC are hidden by the FSP and thus setting them to `on` is not correct. Therefore, set their state to hidden. Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/siemens/chili/variants/base/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48388/1 diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 6bdec65..9493801 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -120,8 +120,8 @@ device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI -- To view, visit https://review.coreboot.org/c/coreboot/+/48388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7 Gerrit-Change-Number: 48388 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Tim Wawrzynczak (Code Review) 09 Dec '20

09 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48194 ) Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Dec 2020 22:27:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020