coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

1 participants
3165 discussions

Change in coreboot[master]: mb/supermicro/x11ssm-f: enable LTR for all root ports
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48367 ) Change subject: mb/supermicro/x11ssm-f: enable LTR for all root ports ...................................................................... mb/supermicro/x11ssm-f: enable LTR for all root ports Follow vendor and enable LTR on all root ports to optimize for devices' latency requirements and also optimize power management while preventing failure due to wrongly guessing idle states, which happens without LTR. Tested successfully. No errors show up in dmesg. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index d7f1873..a03ecc5 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -52,22 +52,27 @@ end device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) register "PcieRpEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1d.0 on # PCH PCIe Port 9 register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" device pci 00.0 on end # GbE 1 end device pci 1d.1 on # PCH PCIe Port 10 register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" device pci 00.1 on end # GbE 2 end device pci 1d.2 on # PCH PCIe Port 11 register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end -- To view, visit https://review.coreboot.org/c/coreboot/+/48367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c Gerrit-Change-Number: 48367 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48366 ) Change subject: mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME ...................................................................... mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME All X11 boards currently supported have Intel SPS without support for S3/S5. Thus, drop it from Kconfig. Note: not all X11 boards are server boards. When a X11 desktop or workstation board should be added, this can be selected by the boards, where S3/S5 work. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/supermicro/x11-lga1151-series/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index c4df4848..bbd54b0 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -1,7 +1,6 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES def_bool n select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT -- To view, visit https://review.coreboot.org/c/coreboot/+/48366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 Gerrit-Change-Number: 48366 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: (re)configure unconnected pads
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48099 ) Change subject: mb/supermicro/x11ssm-f: (re)configure unconnected pads ...................................................................... mb/supermicro/x11ssm-f: (re)configure unconnected pads Correct unconnected pads that are configured different currently by copying vendor configuration while porting the board. Add internal pull resistors to all unconnected pads, that do not have an external pull resistor, to prevent floating. The pads have been determined by dissecting a dead board. This commit only changes pads, that are not connected at all and don't have any via, so we can be absolutely sure there is no other connection. Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c 1 file changed, 81 insertions(+), 81 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c index 0b658ac..9294a0f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c @@ -19,41 +19,41 @@ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), PAD_NC(GPP_A12, NONE), - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_NC(GPP_A13, UP_20K), + PAD_NC(GPP_A14, UP_20K), + PAD_NC(GPP_A15, UP_20K), PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A17, UP_20K), PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), /* GPP_A19 - RESERVED */ - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_NC(GPP_A23, NONE), + PAD_NC(GPP_A20, UP_20K), + PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A22, UP_20K), + PAD_NC(GPP_A23, UP_20K), /* GPIO Group GPP_B */ PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), PAD_NC(GPP_B2, NONE), - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_NC(GPP_B9, NONE), - PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B3, UP_20K), + PAD_NC(GPP_B4, UP_20K), + PAD_NC(GPP_B5, UP_20K), + PAD_NC(GPP_B6, UP_20K), + PAD_NC(GPP_B7, UP_20K), + PAD_NC(GPP_B8, UP_20K), + PAD_NC(GPP_B9, UP_20K), + PAD_NC(GPP_B10, UP_20K), PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR + JBR1 ("Top-Block Swap") */ - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B15, UP_20K), + PAD_NC(GPP_B16, UP_20K), + PAD_NC(GPP_B17, UP_20K), PAD_NC(GPP_B18, NONE), - PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B19, UP_20K), PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */ - PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B21, UP_20K), PAD_NC(GPP_B22, NONE), PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), @@ -70,9 +70,9 @@ PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), PAD_NC(GPP_C11, NONE), - PAD_NC(GPP_C12, NONE), - PAD_NC(GPP_C13, NONE), - PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C13, UP_20K), + PAD_NC(GPP_C14, UP_20K), PAD_NC(GPP_C15, NONE), PAD_NC(GPP_C16, NONE), PAD_NC(GPP_C17, NONE), @@ -87,37 +87,37 @@ PAD_NC(GPP_D0, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), /* Power LEDs onboard + JF1 */ PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* BMC NMI# */ - PAD_NC(GPP_D3, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), - PAD_NC(GPP_D5, NONE), - PAD_NC(GPP_D6, NONE), - PAD_NC(GPP_D7, NONE), - PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D3, DN_20K), + PAD_NC(GPP_D4, UP_20K), + PAD_NC(GPP_D5, UP_20K), + PAD_NC(GPP_D6, UP_20K), + PAD_NC(GPP_D7, UP_20K), + PAD_NC(GPP_D8, UP_20K), PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D12, NONE), - PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D10, UP_20K), + PAD_NC(GPP_D11, UP_20K), + PAD_NC(GPP_D12, UP_20K), + PAD_NC(GPP_D13, UP_20K), PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D17, UP_20K), PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), /* PERST# CPU PCIe Slots */ PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), /* PERST# PCH PCIe Slots */ - PAD_NC(GPP_D20, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), + PAD_NC(GPP_D20, UP_20K), + PAD_NC(GPP_D21, UP_20K), PAD_CFG_GPI(GPP_D22, NONE, RSMRST), /* BMC enable/disable jumper JPB1 */ - PAD_NC(GPP_D23, NONE), + PAD_NC(GPP_D23, UP_20K), /* GPIO Group GPP_E */ - PAD_NC(GPP_E0, NONE), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E0, UP_20K), + PAD_NC(GPP_E1, UP_20K), + PAD_NC(GPP_E2, UP_20K), PAD_NC(GPP_E3, NONE), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E4, UP_20K), + PAD_NC(GPP_E5, UP_20K), PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, INVERT), /* NMI# (BMC WDT + JF1) */ - PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E7, UP_20K), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -125,29 +125,29 @@ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* GPIO Group GPP_F */ - PAD_NC(GPP_F0, NONE), - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), - PAD_NC(GPP_F3, NONE), - PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F0, UP_20K), + PAD_NC(GPP_F1, UP_20K), + PAD_NC(GPP_F2, UP_20K), + PAD_NC(GPP_F3, UP_20K), + PAD_NC(GPP_F4, UP_20K), PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), - PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_NC(GPP_F6, UP_20K), + PAD_NC(GPP_F7, UP_20K), + PAD_NC(GPP_F8, UP_20K), + PAD_NC(GPP_F9, UP_20K), PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F14, UP_20K), PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), PAD_NC(GPP_F17, NONE), PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F19, NONE), - PAD_NC(GPP_F20, NONE), - PAD_NC(GPP_F21, NONE), - PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F21, UP_20K), + PAD_NC(GPP_F22, UP_20K), PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), /* GPIO Group GPP_G */ @@ -155,14 +155,14 @@ PAD_NC(GPP_G1, NONE), /* JPCIE6-B32 (DGPU_PWR_OK) */ PAD_NC(GPP_G2, NONE), /* JPCIE6-B30 (DGPU_SEL#) */ PAD_NC(GPP_G3, NONE), /* JPCIE6-B82 (DGPU_PRSNT#) */ - PAD_NC(GPP_G4, NONE), - PAD_NC(GPP_G5, NONE), - PAD_NC(GPP_G6, NONE), - PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G4, UP_20K), + PAD_NC(GPP_G5, UP_20K), + PAD_NC(GPP_G6, UP_20K), + PAD_NC(GPP_G7, UP_20K), PAD_NC(GPP_G8, NONE), - PAD_NC(GPP_G9, NONE), - PAD_NC(GPP_G10, NONE), - PAD_NC(GPP_G11, NONE), + PAD_NC(GPP_G9, UP_20K), + PAD_NC(GPP_G10, UP_20K), + PAD_NC(GPP_G11, UP_20K), PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* SKU_ID[0] */ PAD_CFG_GPI(GPP_G13, NONE, PLTRST), /* SKU_ID[1] */ PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* SKU_ID[2] */ @@ -172,15 +172,15 @@ PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* BMC NMI# */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* BMC SMI# */ PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* JPI2C1 PWRFAIL# */ - PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G21, UP_20K), PAD_NC(GPP_G22, NONE), PAD_NC(GPP_G23, NONE), /* GPIO Group GPP_H */ PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), + PAD_NC(GPP_H2, UP_20K), + PAD_NC(GPP_H3, UP_20K), PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), @@ -189,17 +189,17 @@ PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), - PAD_NC(GPP_H12, NONE), - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_NC(GPP_H12, UP_20K), + PAD_NC(GPP_H13, NONE), PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), PAD_NC(GPP_H15, NONE), - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), PAD_NC(GPP_H18, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), + PAD_NC(GPP_H19, UP_20K), + PAD_NC(GPP_H20, UP_20K), + PAD_NC(GPP_H21, UP_20K), + PAD_NC(GPP_H22, UP_20K), PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), /* GPIO Group GPP_I */ @@ -223,10 +223,10 @@ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), PAD_CFG_NF(GPD5, NONE, PWROK, NF1), PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_NC(GPD7, NONE), + PAD_NC(GPD7, UP_20K), PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_NC(GPD9, NONE), - PAD_NC(GPD10, NONE), + PAD_NC(GPD9, UP_20K), + PAD_NC(GPD10, UP_20K), PAD_NC(GPD11, NONE), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Gerrit-Change-Number: 48099 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: (re)configure and document various pads
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48098 ) Change subject: mb/supermicro/x11ssm-f: (re)configure and document various pads ...................................................................... mb/supermicro/x11ssm-f: (re)configure and document various pads (Re)configure various pads found by dissecting a dead board and vendor firmware, as well as the BMC firmware: - GPP_B14: input connected to jumper JBR1 - could be used to implement "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up - GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify the BMC about a thermal throttling event. Not implemented in vendor firmware. - GPP_C23: input connected to the CPU's CATERR# output; external pull-up Not actively used by vendor firmware. - GPP_D1: output connected to on-board and front panel power LEDs - GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will be used later in CB:48096 and CB:48097; external pull-up - GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not useful, since the IGD is not connected to any ports on this board. External pulls ensure correct function of a dGPU even without driving the gpios. Not used by vendor firmware. - GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls - GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not used by vendor firmware. Also add comments for documentation. While at it, mark ME-owned pads as reserved. Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c 1 file changed, 24 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Christian Walter: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c index 335171e..0b658ac 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c @@ -46,26 +46,26 @@ PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR + JBR1 ("Top-Block Swap") */ PAD_NC(GPP_B15, NONE), PAD_NC(GPP_B16, NONE), PAD_NC(GPP_B17, NONE), PAD_NC(GPP_B18, NONE), PAD_NC(GPP_B19, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */ PAD_NC(GPP_B21, NONE), PAD_NC(GPP_B22, NONE), PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), /* GPIO Group GPP_C */ - // PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - // PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ PAD_NC(GPP_C2, NONE), - // PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - // PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), - // PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), - // PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), @@ -78,14 +78,14 @@ PAD_NC(GPP_C17, NONE), PAD_NC(GPP_C18, NONE), PAD_NC(GPP_C19, NONE), - PAD_NC(GPP_C20, NONE), + PAD_CFG_GPO(GPP_C20, 1, PLTRST), /* BMC alert CPU_THROTTLED# */ PAD_NC(GPP_C21, NONE), PAD_CFG_GPI_SMI_LOW(GPP_C22, UP_20K, DEEP, EDGE_SINGLE), /* BMC SMI# */ - PAD_NC(GPP_C23, NONE), + PAD_CFG_GPI(GPP_C23, NONE, PLTRST), /* CPU CATERR# */ /* GPIO Group GPP_D */ PAD_NC(GPP_D0, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), /* Power LEDs onboard + JF1 */ PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* BMC NMI# */ PAD_NC(GPP_D3, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), @@ -102,11 +102,11 @@ PAD_NC(GPP_D15, NONE), PAD_NC(GPP_D16, NONE), PAD_NC(GPP_D17, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), /* PERST# CPU PCIe Slots */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), /* PERST# PCH PCIe Slots */ PAD_NC(GPP_D20, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), - PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), + PAD_CFG_GPI(GPP_D22, NONE, RSMRST), /* BMC enable/disable jumper JPB1 */ PAD_NC(GPP_D23, NONE), /* GPIO Group GPP_E */ @@ -151,10 +151,10 @@ PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), /* GPIO Group GPP_G */ - PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), + PAD_NC(GPP_G0, NONE), /* JPCIE6-A19 (DGPU_PWR_EN#) */ + PAD_NC(GPP_G1, NONE), /* JPCIE6-B32 (DGPU_PWR_OK) */ + PAD_NC(GPP_G2, NONE), /* JPCIE6-B30 (DGPU_SEL#) */ + PAD_NC(GPP_G3, NONE), /* JPCIE6-B82 (DGPU_PRSNT#) */ PAD_NC(GPP_G4, NONE), PAD_NC(GPP_G5, NONE), PAD_NC(GPP_G6, NONE), @@ -163,15 +163,15 @@ PAD_NC(GPP_G9, NONE), PAD_NC(GPP_G10, NONE), PAD_NC(GPP_G11, NONE), - PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), + PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* SKU_ID[0] */ + PAD_CFG_GPI(GPP_G13, NONE, PLTRST), /* SKU_ID[1] */ + PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* SKU_ID[2] */ + PAD_CFG_GPI(GPP_G15, NONE, PLTRST), /* SKU_ID[3] */ + PAD_CFG_GPI(GPP_G16, NONE, PLTRST), /* SKU_ID[4] */ PAD_NC(GPP_G17, NONE), PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* BMC NMI# */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* BMC SMI# */ - PAD_NC(GPP_G20, NONE), + PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* JPI2C1 PWRFAIL# */ PAD_NC(GPP_G21, NONE), PAD_NC(GPP_G22, NONE), PAD_NC(GPP_G23, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/48098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93 Gerrit-Change-Number: 48098 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48100 ) Change subject: mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/48100/14/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c: https://review.coreboot.org/c/coreboot/+/48100/14/src/mainboard/supermicro/… PS14, Line 46: DN_20K > just checking pulldown is intentional, most NCs here are pullup This one is the only expection in this patch. Actually, it is connected through a diode to HDA_SDO. Since HDA_SDO gets read before GPP_B11 is configured, this is useless. Since it's connected, I've chosen a pull-down here. D8-2 GPION6 (BMC) >----->|---* | R462 GPP_B11 >---------->|---*----[===]------*---------[===]--->* HDA_SDO D8-1 R440 | R459 *---[===]---* | --- GND -- To view, visit https://review.coreboot.org/c/coreboot/+/48100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06b942e3182469f87e41914c893e5b485ccca420 Gerrit-Change-Number: 48100 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 10 Dec 2020 02:18:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: (re)configure unconnected pads
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48099 ) Change subject: mb/supermicro/x11ssm-f: (re)configure unconnected pads ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/48099/14/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c: https://review.coreboot.org/c/coreboot/+/48099/14/src/mainboard/supermicro/… PS14, Line 90: DN_20K > i assume this pulldown vs. […] Yes, this one is the only exception, because there is an optional/unpopulated external pull-down -- To view, visit https://review.coreboot.org/c/coreboot/+/48099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Gerrit-Change-Number: 48099 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 10 Dec 2020 02:06:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48487 ) Change subject: soc/amd/picasso/reset: use port and bit defines from cf9_reset.h ...................................................................... soc/amd/picasso/reset: use port and bit defines from cf9_reset.h The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/reset.c 3 files changed, 3 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/48487/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index a49768f..b33feb4 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,7 +83,6 @@ #define BIOSRAM_DATA 0xcd5 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) -#define SYS_RESET 0xcf9 /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 6fdc5ab..b485399 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -171,11 +171,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* IO 0xcf9 - Reset control port*/ -#define FULL_RST BIT(3) -#define RST_CMD BIT(2) -#define SYS_RST BIT(1) - /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */ diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index dea166a..e16223a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -2,6 +2,7 @@ #include <arch/io.h> #include <console/console.h> +#include <cf9_reset.h> #include <reset.h> #include <soc/reset.h> #include <soc/southbridge.h> @@ -27,7 +28,7 @@ /* De-assert and then assert all PwrGood signals on CF9 reset. */ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); } void do_warm_reset(void) @@ -35,7 +36,7 @@ set_warm_reset_flag(); /* Assert reset signals only. */ - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); } void do_board_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/48487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Gerrit-Change-Number: 48487 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/picasso/reset: remove leftover PCI includes
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48486 ) Change subject: soc/amd/picasso/reset: remove leftover PCI includes ...................................................................... soc/amd/picasso/reset: remove leftover PCI includes On Stoneyridge some PCI registers were accessed, but on Picasso this is no longer the case. Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/reset.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48486/1 diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 7a0074c..dea166a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -3,9 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <reset.h> -#include <soc/pci_devs.h> #include <soc/reset.h> -#include <device/pci_ops.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Gerrit-Change-Number: 48486 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/hatch: Drop use of SPD cache for puff-based variants
by Matt DeVillier (Code Review) 10 Dec '20

10 Dec '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47899 ) Change subject: mb/google/hatch: Drop use of SPD cache for puff-based variants ...................................................................... mb/google/hatch: Drop use of SPD cache for puff-based variants Commit 74109923 [mb/google/puff: add a region to cache SPD data] implemented a mechanism to cache SODIMM SPD data in a FMAP region, but it's actually slower than simply letting FSP (vs coreboot) read the SPD data via smbus, so drop it. This has the side effect of removing the requirement for a RW_SPD_CACHE FMAP region, without which these boards would not boot at all - allowing the default FMAP to be used for non-ChromeOS builds. Test: build/boot WYVERN variant, check boot times via cbmem: w/SPD caching: ~722 ms w/FSP reading: ~627 ms Change-Id: I4e4db9ba9fdb0fa9fafb2645819b111d381b5756 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/romstage_spd_smbus.c 1 file changed, 5 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47899/1 diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index e697379..1db9c54 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,72 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> -#include <spd_bin.h> -#include <spd_cache.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; variant_memory_params(&memcfg); - /* Read spd block to get memory config */ - struct spd_block blk = { - .addr_map = { 0x50, 0x52, }, - }; - - uint8_t *spd_cache; - size_t spd_cache_sz; - bool need_update_cache = false; - bool dimm_changed = true; - - /* load spd cache from RW_SPD_CACHE */ - if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) { - if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) { - printk(BIOS_WARNING, "Invalid SPD cache\n"); - } else { - dimm_changed = check_if_dimm_changed(spd_cache, &blk); - if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) { - /* Set mrc_cache as invalid */ - printk(BIOS_INFO, "Set mrc_cache as invalid\n"); - memupd->FspmArchUpd.NvsBufferPtr = NULL; - } - } - need_update_cache = true; - } - - if (!dimm_changed) { - spd_fill_from_cache(spd_cache, &blk); - } else { - /* Access memory info through SMBUS. */ - get_spd_smbus(&blk); - - if (need_update_cache && update_spd_cache(&blk) == CB_ERR) - printk(BIOS_WARNING, "update SPD cache failed\n"); - } - - if (blk.spd_array[0] == NULL) { - memcfg.spd[0].read_type = NOT_EXISTING; - } else { - memcfg.spd[0].read_type = READ_SPD_MEMPTR; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; - } - + /* DDR4 SODIMMs located at CH0D0, CH1D0 */ + memcfg.spd[0].read_type = READ_SMBUS; + memcfg.spd[0].spd_spec.spd_smbus_address = 0xa0; memcfg.spd[1].read_type = NOT_EXISTING; - - if (blk.spd_array[1] == NULL) { - memcfg.spd[2].read_type = NOT_EXISTING; - } else { - memcfg.spd[2].read_type = READ_SPD_MEMPTR; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; - } - + memcfg.spd[2].read_type = READ_SMBUS; + memcfg.spd[2].spd_spec.spd_smbus_address = 0xa4; memcfg.spd[3].read_type = NOT_EXISTING; - dump_spd_info(&blk); /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ memcfg.vref_ca_config = 2; -- To view, visit https://review.coreboot.org/c/coreboot/+/47899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e4db9ba9fdb0fa9fafb2645819b111d381b5756 Gerrit-Change-Number: 47899 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Nico Huber (Code Review) 10 Dec '20

10 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: I only now realized that you stripped the most important part when quoting me: > > > > What > > > > about all the mainboards that use this driver by properly > > > > matching the PCI IDs? Maybe you misunderstood. This driver is not only used via a `chip` entry in the devicetree. It is foremost used as a usual PCI driver. $ git grep 'device pci 1[89e].* on.*UART' src/mainboard/ This says there are at least 120 cases in the tree that potentially use it and might break due to this change. The driver would even be used if the device is not mentioned in the dt at all, it's PCI. > > > > I can't say if this is working, or even if it can work. > > > > > > I wonder how this one is different from drivers/wifi/generic, which uses the same dummy model? > > > > Except it doesn't? It does not use a generic device below > > a PCI device. And it checks the device path so it doesn't > > attach PCI ops to a non-PCI device in the first place. > > What is this then? > > device pci 14.3 on > chip drivers/wifi/generic > register "wake" = "GPE0_PME_B0" > device generic 0 on end > end > end # CNVi wifi Sorry, my bad. I didn't realize it's used with two different topologies. The difference is that the driver is prepared for that and attaches the CNVi ops only in case of the generic device. And only then the parent is queried. Here, OTOH, you always use the parent, no matter the topology. > > You really should check the history of drivers/wifi/generic, commit d436750 for example... Well, the history is one thing. The current code is what matters however. How about you read that? -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 00:09:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2020