Change in coreboot[master]: soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48487 )
Change subject: soc/amd/picasso/reset: use port and bit defines from cf9_reset.h ......................................................................
soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but have the same functionality.
Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/reset.c 3 files changed, 3 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/48487/1
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index a49768f..b33feb4 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,7 +83,6 @@ #define BIOSRAM_DATA 0xcd5 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) -#define SYS_RESET 0xcf9
/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 6fdc5ab..b485399 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -171,11 +171,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12)
-/* IO 0xcf9 - Reset control port*/ -#define FULL_RST BIT(3) -#define RST_CMD BIT(2) -#define SYS_RST BIT(1) - /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */
diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index dea166a..e16223a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -2,6 +2,7 @@
#include <arch/io.h> #include <console/console.h> +#include <cf9_reset.h> #include <reset.h> #include <soc/reset.h> #include <soc/southbridge.h> @@ -27,7 +28,7 @@ /* De-assert and then assert all PwrGood signals on CF9 reset. */ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); }
void do_warm_reset(void) @@ -35,7 +36,7 @@ set_warm_reset_flag();
/* Assert reset signals only. */ - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); }
void do_board_reset(void)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48487 )
Change subject: soc/amd/picasso/reset: use port and bit defines from cf9_reset.h ......................................................................
Patch Set 3: Code-Review+2
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48487 )
Change subject: soc/amd/picasso/reset: use port and bit defines from cf9_reset.h ......................................................................
Patch Set 3: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48487 )
Change subject: soc/amd/picasso/reset: use port and bit defines from cf9_reset.h ......................................................................
soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but have the same functionality.
Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/reset.c 3 files changed, 3 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Arthur Heymans: Looks good to me, approved
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index cec3aaf..43e5658 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,6 +83,5 @@ #define BIOSRAM_DATA 0xcd5 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) -#define SYS_RESET 0xcf9
#endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 08e2428..220d92e 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -163,11 +163,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12)
-/* IO 0xcf9 - Reset control port*/ -#define FULL_RST BIT(3) -#define RST_CMD BIT(2) -#define SYS_RST BIT(1) - /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */
diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index dea166a..e16223a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -2,6 +2,7 @@
#include <arch/io.h> #include <console/console.h> +#include <cf9_reset.h> #include <reset.h> #include <soc/reset.h> #include <soc/southbridge.h> @@ -27,7 +28,7 @@ /* De-assert and then assert all PwrGood signals on CF9 reset. */ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); }
void do_warm_reset(void) @@ -35,7 +36,7 @@ set_warm_reset_flag();
/* Assert reset signals only. */ - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); }
void do_board_reset(void)
-
Arthur Heymans (Code Review) -
Felix Held (Code Review)
-
Marshall Dawson (Code Review)