Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48368 )
Change subject: mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/supermicro/x11ssm-f: enable LTR for all root ports
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Patch Set 3: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48100 )
Change subject: mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads
......................................................................
Patch Set 14: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48100/14/src/mainboard/supermicro/…
File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c:
https://review.coreboot.org/c/coreboot/+/48100/14/src/mainboard/supermicro/…
PS14, Line 46: DN_20K
just checking pulldown is intentional, most NCs here are pullup
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48099 )
Change subject: mb/supermicro/x11ssm-f: (re)configure unconnected pads
......................................................................
Patch Set 14: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48099/14/src/mainboard/supermicro/…
File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c:
https://review.coreboot.org/c/coreboot/+/48099/14/src/mainboard/supermicro/…
PS14, Line 90: DN_20K
i assume this pulldown vs. everythihng else pullup was intentional?
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Change subject: mb/supermicro/x11ssm-f: (re)configure and document various pads
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Patch Set 14: Code-Review+2
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Jes Klinke has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48222 )
Change subject: drivers/i2c/tpm: Unconditionally allow I2C TPM ACPI node
......................................................................
drivers/i2c/tpm: Unconditionally allow I2C TPM ACPI node
Volteer has two "sub-variants" sharing the same overridetree.cb, one
having I2C TPM and another having I2C TPM. The former will have a
disabled ACPI node representing the I2C TPM, while its Kconfig is such
that coreboot itself does not have I2C TPM support.
In order to export even a disabled ACPI node representing the I2C
connected TPM, coreboot needs DRIVER_I2C_TPM_ACPI. Hence, that will
have to be enabled in a case where coreboot does not have I2C_TPM.
BUG=b:173461736
TEST=Tested as part of next CL in chain
Change-Id: I9717f6b68afd90fbc294fbbd2a5b8d0c6ee9ae55
Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org>
---
M src/drivers/i2c/tpm/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48222/1
diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig
index 6a27224..e0f7fbf 100644
--- a/src/drivers/i2c/tpm/Kconfig
+++ b/src/drivers/i2c/tpm/Kconfig
@@ -41,7 +41,6 @@
depends on I2C_TPM
config DRIVER_I2C_TPM_ACPI
- depends on I2C_TPM
bool "Generate I2C TPM ACPI device"
default y if ARCH_X86 && I2C_TPM
default n
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48476 )
Change subject: soc/amd/cezanne: print APU family and model in bootblock_soc_init
......................................................................
soc/amd/cezanne: print APU family and model in bootblock_soc_init
Change-Id: I457188c905167affc1ebcea835a36df822ecb23c
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/cezanne/bootblock.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48476/1
diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index 8e1bff0..9fb99bd 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -2,6 +2,7 @@
#include <amdblocks/amd_pci_mmconf.h>
#include <bootblock_common.h>
+#include <console/console.h>
#include <cpu/x86/tsc.h>
#include <soc/southbridge.h>
#include <stdint.h>
@@ -26,5 +27,7 @@
void bootblock_soc_init(void)
{
+ u32 val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
fch_early_init();
}
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 )
Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT
......................................................................
Patch Set 69:
(4 comments)
https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base…
File src/soc/intel/common/basecode/fw_update/ucode_update.c:
https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base…
PS67, Line 260: BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ucode_fw_sync, NULL);
> This will be moved as part of intel_fw_update where coreboot triggers CSE FW Update and UCODE Update.
>
> https://review.coreboot.org/c/coreboot/+/46819/6/src/soc/intel/common/basec…
>
> This is required to consolidate number of resets required as part of FW Update.
ok.
Maybe use a static variable inside intel_microcode_find() to avoid finding it multiple times? Just a suggestion for a followup.
https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base…
File src/soc/intel/common/basecode/fw_update/ucode_update.c:
https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base…
PS69, Line 58: halt();
: }
die already calls halt()
https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base…
PS69, Line 131: goto failure;
There is only one occurrence of this so remove the goto?
https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base…
PS69, Line 249: void ucode_fw_sync(void *unused)
any reason to not make this static?
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