coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/tigerlake: Enable support for extended BIOS window
by Furquan Shaikh (Code Review) 09 Dec '20

09 Dec '20

Hello build bot (Jenkins), Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48186 to look at the new patch set (#5). Change subject: soc/intel/tigerlake: Enable support for extended BIOS window ...................................................................... soc/intel/tigerlake: Enable support for extended BIOS window This change enables support for extended BIOS window by selecting FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW and providing base and size of the extended window in host address space. BUG=b:171534504 Cq-Depend: chromium:2566231 Change-Id: I039155506380310cf867f5f8c5542278be40838a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48186/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/48186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I039155506380310cf867f5f8c5542278be40838a Gerrit-Change-Number: 48186 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Update Boten GPIO setting for PEN detection.
by Stanley Wu (Code Review) 09 Dec '20

09 Dec '20

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48294 ) Change subject: mb/google/dedede: Update Boten GPIO setting for PEN detection. ...................................................................... mb/google/dedede: Update Boten GPIO setting for PEN detection. AP_PEN_DET_ODL isolated by a diode and need to pull up internally. BUG=b:160752604 BRANCH=firmware-dedede-13606.B TEST=Build and confirm waveform by google EE parter. Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2 --- M src/mainboard/google/dedede/variants/boten/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48294/1 diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index c27daa4..0c81872 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -11,7 +11,7 @@ PAD_CFG_GPO(GPP_A10, 0, PLTRST), /* C12 : AP_PEN_DET_ODL */ - PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_SCI(GPP_C12, UP_20K, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), /* C19 : AP_I2C_EMR_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2 Gerrit-Change-Number: 48294 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/vliboz: update telemetry settings
by John Su (Code Review) 09 Dec '20

09 Dec '20

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48288 ) Change subject: mb/google/zork/var/vliboz: update telemetry settings ...................................................................... mb/google/zork/var/vliboz: update telemetry settings Update telemetry settings. VDD Slope : 32643 -> 26939 VDD Offset: 208 -> 125 SOC Slope : 22742 -> 20001 SOC Offset: -83 -> 168 BUG=b:171668654 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE test report Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4 --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48288/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 3b3bdd4..9d6f132 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -18,10 +18,10 @@ # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope_mA" = "32643" - register "telemetry_vddcr_vdd_offset" = "208" - register "telemetry_vddcr_soc_slope_mA" = "22742" - register "telemetry_vddcr_soc_offset" = "-83" + register "telemetry_vddcr_vdd_slope_mA" = "26939" + register "telemetry_vddcr_vdd_offset" = "125" + register "telemetry_vddcr_soc_slope_mA" = "20001" + register "telemetry_vddcr_soc_offset" = "168" # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4 Gerrit-Change-Number: 48288 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Frank Chu (Code Review) 09 Dec '20

09 Dec '20

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48194 ) Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 50: 3 > USB2_BIAS_39P35MV Done https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 51: 2 > USB2_PRE_EMP_ON Done https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 52: 7 > USB2_BIAS_56P3MV Done https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 53: 1 > USB2_HALF_BIT_PRE_EMP Done -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Dec 2020 09:37:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Frank Chu (Code Review) 09 Dec '20

09 Dec '20

Hello build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48194 to look at the new patch set (#4). Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48194/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2/3
by V Sowmya (Code Review) 09 Dec '20

09 Dec '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48230 ) Change subject: mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2/3 ...................................................................... mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2/3 This patch adds the PMC MUX and CONx devices for adlrvp for conn2/3. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/48230/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index 8033d3d..e5d7bb2 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -27,6 +27,20 @@ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "4" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 3 alias conn3 on end + end end end end # PMC -- To view, visit https://review.coreboot.org/c/coreboot/+/48230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c Gerrit-Change-Number: 48230 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Sridhar Siricilla (Code Review) 09 Dec '20

09 Dec '20

Sridhar Siricilla has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/48281 ) Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/volteer: Update drobit device tree
by Frank Chu (Code Review) 09 Dec '20

09 Dec '20

Frank Chu has removed Daniel Peng from this change. ( https://review.coreboot.org/c/coreboot/+/48495 ) Change subject: mb/google/volteer: Update drobit device tree ...................................................................... Removed reviewer Daniel Peng. -- To view, visit https://review.coreboot.org/c/coreboot/+/48495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1 Gerrit-Change-Number: 48495 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Sridhar Siricilla (Code Review) 09 Dec '20

09 Dec '20

Hello build bot (Jenkins), Jamie Ryu, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48281 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage This patch sets up cse_fw_sync() call in the romstage. BUG=b:174694480 Test=Verified on Tigerlake platform Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 --- M src/soc/intel/tigerlake/romstage/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/48281/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the...
by Sridhar Siricilla (Code Review) 09 Dec '20

09 Dec '20

Hello build bot (Jenkins), Jamie Ryu, Sugnan Prabhu S, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48280 to look at the new patch set (#2). Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage ...................................................................... soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage This patch sets up cse_fw_sync() call in the romstage. BUG=b:174694480 Test=Verified on Drawlet Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a --- M src/soc/intel/jasperlake/romstage/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48280/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Gerrit-Change-Number: 48280 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2020