coreboot-gerrit December 2020

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Change in coreboot[master]: soc/amd: factor out legacy I/O and cf9 decode enable functions
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48435 ) Change subject: soc/amd: factor out legacy I/O and cf9 decode enable functions ...................................................................... soc/amd: factor out legacy I/O and cf9 decode enable functions Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmui_util file to have them all in one place. Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 7 files changed, 24 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/48435/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 5084672..6231d49 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -58,6 +58,21 @@ pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw); } +void fch_enable_cf9_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | CF9_IO_EN); +} + +void fch_enable_legacy_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + +void fch_io_enable_legacy_io(void) +{ + pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + /* PM registers are accessed a byte at a time via CD6/CD7 */ uint8_t pm_io_read8(uint8_t reg) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 865ad48..0e42ee6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -73,6 +73,9 @@ /* For newer integrated FCHs */ void enable_acpimmio_decode_pm04(void); +void fch_enable_cf9_io(void); +void fch_enable_legacy_io(void); +void fch_io_enable_legacy_io(void); /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index b813770..e6c70f6 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -102,11 +102,6 @@ return addr; } -void sb_enable_legacy_io(void) -{ - pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); -} - static uint32_t map_fch_devices(void) { void *bar; diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index f367dce..8ef2dcd 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -2,6 +2,7 @@ #include "psp_verstage.h" +#include <amdblocks/acpimmio.h> #include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> #include <cbfs.h> @@ -237,7 +238,7 @@ verstage_mainboard_early_init(); svc_write_postcode(POSTCODE_LATE_INIT); - sb_enable_legacy_io(); + fch_io_enable_legacy_io(); verstage_soc_init(); verstage_mainboard_init(); diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index ef5c452..4f85d7c 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -55,6 +55,5 @@ uint32_t verstage_soc_early_init(void); void verstage_soc_init(void); uintptr_t *map_spi_rom(void); -void sb_enable_legacy_io(void); #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index bc801a3..3110dea 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -91,20 +91,6 @@ return irq_association; } -static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -131,8 +117,8 @@ fch_spi_early_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); - sb_enable_legacy_io(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); enable_aoac_devices(); sb_reset_i2c_slaves(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7661607..46fdeb2 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -200,20 +200,6 @@ lpc_enable_decode(tmp); } -static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; @@ -347,14 +333,14 @@ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); + fch_enable_cf9_io(); setup_spread_spectrum(&reboot); setup_misc(&reboot); if (reboot) warm_reset(); - sb_enable_legacy_io(); + fch_enable_legacy_io(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Gerrit-Change-Number: 48435 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: factor out PM_DECODE_EN register definitions
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48433 ) Change subject: soc/amd: factor out PM_DECODE_EN register definitions ...................................................................... soc/amd: factor out PM_DECODE_EN register definitions Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 3 files changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/48433/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 62f7190..3887f73 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -11,6 +11,17 @@ #define PM_DATA 0xcd7 /* + * Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7. Valid for Mullins and + * newer SoCs, but not for the generations with separate FCH or Kabini. + */ +#define PM_DECODE_EN 0x00 +#define SMBUS_ASF_IO_EN (1 << 4) +#define CF9_IO_EN (1 << 1) +#define LEGACY_IO_EN (1 << 0) + +#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */ + +/* * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs * and the Kabini SoC fall into this category. Kabini's successor, Mullins, uses * this newer method of enable in PMx04. diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index c0a5057..13ef53f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -22,11 +22,6 @@ #define SMB_UART_1_8M_SHIFT 28 /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ -#define PM_DECODE_EN 0x00 -#define SMBUS_ASF_IO_EN BIT(4) -#define CF9_IO_EN BIT(1) -#define LEGACY_IO_EN BIT(0) -#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */ #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9b2dcf0..0a5832b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -15,15 +15,10 @@ */ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ -#define PM_DECODE_EN 0x00 -#define CF9_IO_EN BIT(1) -#define LEGACY_IO_EN BIT(0) #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) #define FORCE_STPCLK_RETRY BIT(24) -#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */ - #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD BIT(1) -- To view, visit https://review.coreboot.org/c/coreboot/+/48433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da Gerrit-Change-Number: 48433 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: remove unused PM_ISA_CONTROL definitions
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48432 ) Change subject: soc/amd: remove unused PM_ISA_CONTROL definitions ...................................................................... soc/amd: remove unused PM_ISA_CONTROL definitions ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO code block that actually gets used. Also fix the indentation of the ACPIMMIO register decode defines in the common code. Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 3 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48432/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 932ae47..62f7190 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -16,10 +16,10 @@ * this newer method of enable in PMx04. */ -#define ACPIMMIO_DECODE_REGISTER_24 0x24 +#define ACPIMMIO_DECODE_REGISTER_24 0x24 #define PM_24_ACPIMMIO_DECODE_EN BIT(0) -#define ACPIMMIO_DECODE_REGISTER_04 0x4 +#define ACPIMMIO_DECODE_REGISTER_04 0x04 #define PM_04_BIOSRAM_DECODE_EN BIT(0) #define PM_04_ACPIMMIO_DECODE_EN BIT(1) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 6fdc5ab..c0a5057 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -27,8 +27,6 @@ #define CF9_IO_EN BIT(1) #define LEGACY_IO_EN BIT(0) #define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */ -#define PM_ISA_CONTROL 0x04 -#define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d346197..9b2dcf0 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -18,8 +18,6 @@ #define PM_DECODE_EN 0x00 #define CF9_IO_EN BIT(1) #define LEGACY_IO_EN BIT(0) -#define PM_ISA_CONTROL 0x04 -#define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) #define FORCE_STPCLK_RETRY BIT(24) -- To view, visit https://review.coreboot.org/c/coreboot/+/48432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45 Gerrit-Change-Number: 48432 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge: make sb_disable_4dw_burst static
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48431 ) Change subject: soc/amd/stoneyridge/southbridge: make sb_disable_4dw_burst static ...................................................................... soc/amd/stoneyridge/southbridge: make sb_disable_4dw_burst static sb_disable_4dw_burst is only used in the same compilation unit, so no need to make it externally visible. Change-Id: I6c7c96f67b98fb8ed808f45a7685c4d72a10d32c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48431/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d346197..e0ffd61 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -248,7 +248,6 @@ void enable_aoac_devices(void); void sb_clk_output_48Mhz(u32 osc); -void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7661607..8815702 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -255,7 +255,7 @@ spi_write16(SPI100_ENABLE, SPI_USE_SPI100); } -void sb_disable_4dw_burst(void) +static void sb_disable_4dw_burst(void) { spi_write16(SPI100_HOST_PREF_CONFIG, spi_read16(SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); -- To view, visit https://review.coreboot.org/c/coreboot/+/48431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c7c96f67b98fb8ed808f45a7685c4d72a10d32c Gerrit-Change-Number: 48431 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Add $(xcompile) to specify where to write xcompile
by Nico Huber (Code Review) 08 Dec '20

08 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28101 ) Change subject: Makefile: Add $(xcompile) to specify where to write xcompile ...................................................................... Patch Set 11: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/28101/11/Makefile File Makefile: https://review.coreboot.org/c/coreboot/+/28101/11/Makefile@154 PS11, Line 154: util/xcompile/xcompile $(XGCCPATH) > $(xcompile) || rm -f $(xcompile))) Should we redirect stderr to /dev/null just in case? The `include` below should give a reasonable error message if something goes wrong but any output of the `$(shell )` call would likely result in a mess. -- To view, visit https://review.coreboot.org/c/coreboot/+/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)google.com> Gerrit-Comment-Date: Tue, 08 Dec 2020 23:49:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable support for extended BIOS window
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48186 ) Change subject: soc/intel/tigerlake: Enable support for extended BIOS window ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/48186/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48186/4//COMMIT_MSG@13 PS4, Line 13: BUG=b:171534504 Waiting to land the earlier patches in chromium tree and then I will cherry-pick rest of the changes here to ensure I can set up Cq-Depend correctly. -- To view, visit https://review.coreboot.org/c/coreboot/+/48186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I039155506380310cf867f5f8c5542278be40838a Gerrit-Change-Number: 48186 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 22:59:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: Restrict RW_DIAG to lower 16MiB
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48190 ) Change subject: mb/google/deltaur: Restrict RW_DIAG to lower 16MiB ...................................................................... mb/google/deltaur: Restrict RW_DIAG to lower 16MiB This change restricts RW_DIAG region to lower 16MiB to ensure that the extended BIOS checker for FMAP does not complain about 16MiB boundary crossing. I haven't updated any other regions to occupy the newly freed space but it is fine since this board is dead and should be dropped from coreboot soon. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 --- M src/mainboard/google/deltaur/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/48190/1 diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd index bbec112..a84a448 100644 --- a/src/mainboard/google/deltaur/chromeos.fmd +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -6,9 +6,9 @@ SI_PDR(PRESERVE)@0x602000 0x4000 } SI_BIOS@0x606000 0x19fa000 { - RW_DIAG@0x0 0x10ca000 { - RW_LEGACY(CBFS)@0x0 0x10ba000 - DIAG_NVRAM@0x10ba000 0x10000 + RW_DIAG@0x0 0x9fa000 { + RW_LEGACY(CBFS)@0x0 0x9ea000 + DIAG_NVRAM@0x9ea000 0x10000 } RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 -- To view, visit https://review.coreboot.org/c/coreboot/+/48190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 Gerrit-Change-Number: 48190 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48189 ) Change subject: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB ...................................................................... mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB This change restricts SI_ME region to live below the 16MiB boundary to ensure that no regions cross the 16MiB boundary as the extended BIOS window checker for FMAP complains about it. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 --- M src/mainboard/intel/tglrvp/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48189/1 diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index bfbd304..1e2e792 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,8 +1,8 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1000000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_ME@0x81000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/48189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 Gerrit-Change-Number: 48189 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/fast_spi: Add Lockdown of extended BIOS region
by Srinidhi N Kaushik (Code Review) 08 Dec '20

08 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48068 ) Change subject: soc/intel/common/fast_spi: Add Lockdown of extended BIOS region ...................................................................... soc/intel/common/fast_spi: Add Lockdown of extended BIOS region This change adds support to Lock down the configuration of extended BIOS region. This is done as part of fast_spi_lockdown_cfg() so that it is consistent with the other lockdown. Change includes: 1. New helper function fast_spi_lock_ext_bios_cfg() added that will basically set EXT_BIOS_LOCK. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/pch/lockdown/lockdown.c 4 files changed, 21 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48068/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index e4d23a6..d4e6230 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -64,7 +64,7 @@ /* * Set FAST_SPIBAR BIOS Control register based on input bit field. */ -static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit) +static void fast_spi_set_bios_control_reg(uint32_t bios_cntl_bit) { #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_SPI; @@ -74,9 +74,9 @@ uint8_t bc_cntl; assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0); - bc_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); + bc_cntl = pci_read_config32(dev, SPIBAR_BIOS_CONTROL); bc_cntl |= bios_cntl_bit; - pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_cntl); + pci_write_config32(dev, SPIBAR_BIOS_CONTROL, bc_cntl); } /* @@ -108,6 +108,16 @@ } /* + * Set FAST_SPIBAR BIOS Control EXT BIOS LE bit. + */ +void fast_spi_set_ext_bios_lock_enable(void) +{ + fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE); + + fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); +} + +/* * Set FAST_SPIBAR BIOS Control EISS bit. */ void fast_spi_set_eiss(void) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index f1c0f1e..9784797 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -14,6 +14,7 @@ /* Bit definitions for BIOS_CONTROL */ #define SPIBAR_BIOS_CONTROL_WPD (1 << 0) #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28) #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) #define SPIBAR_BIOS_CONTROL_EISS (1 << 5) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 58bf25b..729690a 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -23,6 +23,10 @@ */ void fast_spi_set_lock_enable(void); /* + * Set FAST_SPIBAR BIOS Control Ext Bios LE bit. + */ +void fast_spi_set_ext_bios_lock_enable(void); +/* * Set FAST_SPIBAR BIOS Control EISS bit. */ void fast_spi_set_eiss(void); diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 906f8b0..b10306e 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -63,6 +63,9 @@ /* BIOS Lock */ fast_spi_set_lock_enable(); + + /* EXT BIOS Lock */ + fast_spi_set_ext_bios_lock_enable(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518 Gerrit-Change-Number: 48068 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/fast_spi: Add support for configuring MTRRs
by Srinidhi N Kaushik (Code Review) 08 Dec '20

08 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47991 ) Change subject: soc/intel/common/fast_spi: Add support for configuring MTRRs ...................................................................... soc/intel/common/fast_spi: Add support for configuring MTRRs This change enables caching for extended BIOS region. Currently, caching is enabled for the standard BIOS region upto a maximum of 16MiB using fast_spi_cache_bios_region, used the same function to add the support for caching for extended BIOS region as well. Changes include: 1. Add a new helper function fast_spi_cache_ext_bios_region() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 2. Make a call to fast_spi_cache_ext_bios_region() from fast_spi_cache_bios_region (). 3. If the extended window is used, then it enables caching for this window similar to how it is done for the standard window. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779 --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47991/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index a3ec0d7..d5c6218 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -213,6 +213,40 @@ return bios_start; } +static void fast_spi_cache_ext_bios_window(void) +{ + + size_t ext_bios_size; + uint32_t alignment; + uintptr_t ext_bios_base; + const int type = MTRR_TYPE_WRPROT; + + if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) + return; + + fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size); + + /* Enable extended bios only if Size of Bios region is greater than 16MiB */ + if (ext_bios_size == 0 || ext_bios_base == 0) + return; + + /* Round to power of two */ + alignment = 1UL << (log2_ceil(ext_bios_size)); + ext_bios_size = ALIGN_UP(ext_bios_size, alignment); + ext_bios_base = ALIGN_DOWN(ext_bios_base, ext_bios_size); + + if (ENV_PAYLOAD_LOADER) { + mtrr_use_temp_range(ext_bios_base, ext_bios_size, type); + } else { + int mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); + } +} + void fast_spi_cache_bios_region(void) { size_t bios_size; @@ -246,6 +280,9 @@ set_var_mtrr(mtrr, base, bios_size, type); } + + /* Check if caching is needed for extended bios region if supported */ + fast_spi_cache_ext_bios_window(); } /* Enable extended bios support -- To view, visit https://review.coreboot.org/c/coreboot/+/47991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779 Gerrit-Change-Number: 47991 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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