coreboot-gerrit December 2020

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Change in coreboot[master]: cbmem: Make cbmem_online() accurate on stages after romstage
by Julius Werner (Code Review) 08 Dec '20

08 Dec '20

Hello Patrick Georgi, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48428 to review the following change. Change subject: cbmem: Make cbmem_online() accurate on stages after romstage ...................................................................... cbmem: Make cbmem_online() accurate on stages after romstage cbmem_online() always returns 1 in stages after romstage. However, CBMEM isn't actually immediately available in those stages -- instead, it will only become available when cbmem_initialize() is called. That usually happens very early in the stage, but there are still small amounts of code running beforehand, so it is useful to reflect this distinction. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I623c0606a4f49ea98c4c7559436bf32ebb83b456 --- M src/include/cbmem.h 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48428/1 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7e1da17..9e12afe 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -163,10 +163,7 @@ if (!cbmem_possibly_online()) return 0; - if (ENV_ROMSTAGE) - return cbmem_initialized; - - return 1; + return cbmem_initialized; } #endif /* _CBMEM_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I623c0606a4f49ea98c4c7559436bf32ebb83b456 Gerrit-Change-Number: 48428 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configurati...
by Stanley Wu (Code Review) 08 Dec '20

08 Dec '20

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47434 ) Change subject: mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration for lindar ...................................................................... mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration for lindar This patch adds the PMC MUX and CONx devices for lindar. Device specific method contains the port and orientation details used to configure the mux. BUG=b:172533907 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c --- M src/mainboard/google/volteer/variants/lindar/overridetree.cb 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47434/1 diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 87ca0a3..182077c 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -71,6 +71,35 @@ device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end device ref north_xhci on chip drivers/usb/acpi device ref tcss_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/47434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c Gerrit-Change-Number: 47434 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Abandoned See CB:48385 -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Duncan Laurie, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48385 to look at the new patch set (#3). Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... soc/intel/common/block/uart: rework to use dummy device This change reorganizes the uart chip driver to use a dummy device instead of wrapping the actual UART controller by the chip. This is done to make the organization of the UART PCI device in the devicetree consistent with all the other internal PCI devices of the SoC i.e. without a chip around the PCI device. Thus, with this change, UART entry in devicetrees can be changed from: ``` chip soc/intel/common/block/uart device pci xx.y hidden register "devid" = "PCI_DEVICE_ID_INTEL_XXX_UART2" end # UART #2, in ACPI mode ``` to: ``` device pci xx.y hidden chip soc/intel/common/block/uart register "devid" = "PCI_DEVICE_ID_INTEL_XXX_UART2" device generic 0 on end # Dummy UART device end end # UART #2, in ACPI mode ``` This change also corrects the devicetree of the only board currently using this driver, prodrive/hermes. Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/soc/intel/common/block/uart/uart.c 2 files changed, 38 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48385/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 21:20:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Restore alphabetical order of Kconfig selects
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48396 ) Change subject: soc/intel/cannonlake: Restore alphabetical order of Kconfig selects ...................................................................... soc/intel/cannonlake: Restore alphabetical order of Kconfig selects Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48396 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 11 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f427340..48de0c1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -80,15 +80,18 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION + select DISPLAY_FSP_VERSION_INFO select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT - select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER + select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE select IDT_IN_EVERY_STAGE + select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -96,9 +99,9 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 - select REG_SCRIPT select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK + select REG_SCRIPT select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK @@ -111,26 +114,23 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS - select SOC_INTEL_COMMON_BLOCK_XHCI - select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_THERMAL - select SOC_INTEL_COMMON_PCH_BASE - select SOC_INTEL_COMMON_NHLT - select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET + select SOC_INTEL_COMMON_NHLT + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING - select DISPLAY_FSP_VERSION_INFO - select FSP_T_XIP if FSP_CAR - select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/48396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753 Gerrit-Change-Number: 48396 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/*: Remove SATA mode config for CNL based mainboards
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48391 ) Change subject: mb/*: Remove SATA mode config for CNL based mainboards ...................................................................... mb/*: Remove SATA mode config for CNL based mainboards SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb 6 files changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 67d35b3..3329f63 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -113,7 +113,6 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" # Port 2 (J_SSD2) register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 5826f79..7d9d1e6 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ # FSP configuration register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 69e4e7d..c975b99 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -16,7 +16,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 021feba..6a807a3 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -16,7 +16,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 571a336..6b326f0 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -172,7 +172,6 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[2]" = "1" # m.2 register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 1f92fec..3a0758a 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -113,7 +113,6 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" # Port 2 (J_SSD2) register "SataPortsEnable[1]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/48391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Gerrit-Change-Number: 48391 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Align SATA mode names with soc/skl
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48390 ) Change subject: soc/intel/cannonlake: Align SATA mode names with soc/skl ...................................................................... soc/intel/cannonlake: Align SATA mode names with soc/skl Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/chip.h 7 files changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 3bb802e..67d35b3 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -113,7 +113,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" # Port 2 (J_SSD2) register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 31f6652..5826f79 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -20,7 +20,7 @@ # FSP configuration register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 9e05213..69e4e7d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -16,7 +16,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 005a783..021feba 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -16,7 +16,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index c39bccf..571a336 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -172,7 +172,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[2]" = "1" # m.2 register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 8e45eba..1f92fec 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -113,7 +113,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" # Port 2 (J_SSD2) register "SataPortsEnable[1]" = "1" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a084f67..70aab92 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -129,8 +129,8 @@ /* SATA related */ enum { - Sata_AHCI, - Sata_RAID, + SATA_AHCI, + SATA_RAID, } SataMode; /* SATA devslp pad reset configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Gerrit-Change-Number: 48390 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Makefile: Allow platform to provide additional params for add cmd
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47884 ) Change subject: Makefile: Allow platform to provide additional params for add cmd ...................................................................... Makefile: Allow platform to provide additional params for add cmd This change adds optional CBFSTOOL_ADD_CMD_OPTIONS that can be used by arch/SoC/mainboard Makefiles to supply any additional arguments that need to be passed into cbfstool when using cbfstool add command. This is useful when platform wants to add these parameters depending upon some arch/SoC/mainboard specific configs. Immediate use case is the fast SPI controller on Intel platforms adding arguments for extended window base and size. BUG=b:171534504 Change-Id: I2f48bc3f494d9a5da7e99b530a39d6078b4a881c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M Makefile.inc 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/47884/1 diff --git a/Makefile.inc b/Makefile.inc index 9273961..2dc615f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -836,6 +836,10 @@ # cbfs-add-cmd-for-region # $(call cbfs-add-cmd-for-region,file in extract_nth format,region name) +# +# CBFSTOOL_ADD_CMD_OPTIONS can be used by arch/SoC/mainboard to supply +# add commands with any additional arguments for cbfstool. +# Example: --ext-win-base <base> --ext-win-size <size> define cbfs-add-cmd-for-region $(CBFSTOOL) $@.tmp \ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \ @@ -850,8 +854,8 @@ -r $(2) \ $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ - $(call extract_nth,7,$(1)) - + $(call extract_nth,7,$(1)) \ + $(CBFSTOOL_ADD_CMD_OPTIONS) endef # Empty line before endef is necessary so cbfs-add-cmd-for-region ends in a @@ -1086,7 +1090,8 @@ $(TXTIBB) \ $(CBNTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ - $(TS_OPTIONS) + $(TS_OPTIONS) \ + $(CBFSTOOL_ADD_CMD_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -1098,10 +1103,11 @@ -f $@.tmp.2 \ -n "header pointer" \ -t "cbfs header" \ - -b -4 + -b -4 \ + $(CBFSTOOL_ADD_CMD_OPTIONS) rm -f $@.tmp.2 endif # ifeq ($(CONFIG_ARCH_X86),y) - $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) + $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS) $(prebuild-files) true mv $@.tmp $@ else # ifneq ($(CONFIG_UPDATE_IMAGE),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/47884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f48bc3f494d9a5da7e99b530a39d6078b4a881c Gerrit-Change-Number: 47884 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/cannonlake: Restore alphabetical order of Kconfig selects
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48396 ) Change subject: soc/intel/cannonlake: Restore alphabetical order of Kconfig selects ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753 Gerrit-Change-Number: 48396 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 21:10:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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