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Change in coreboot[master]: util/cbfstool: Rename IS_TOP_ALIGNED_ADDRESS to IS_HOST_SPACE_ADDRESS
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47830 ) Change subject: util/cbfstool: Rename IS_TOP_ALIGNED_ADDRESS to IS_HOST_SPACE_ADDRESS ...................................................................... util/cbfstool: Rename IS_TOP_ALIGNED_ADDRESS to IS_HOST_SPACE_ADDRESS This change renames the macro `IS_TOP_ALIGNED_ADDRESS` to `IS_HOST_SPACE_ADDRESS` to make it clear that the macro checks if given address is an address in the host space as opposed to the SPI flash space. Change-Id: I84bb505df62ac41f1d364a662be145603c0bd5fa Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c M util/cbfstool/common.h 3 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47830/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 3f1bf43..da65960 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -731,7 +731,7 @@ assert(image); assert(buffer); assert(buffer->data); - assert(!IS_TOP_ALIGNED_ADDRESS(content_offset)); + assert(!IS_HOST_SPACE_ADDRESS(content_offset)); const char *name = header->filename; diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c719b8f..061ff82 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -563,7 +563,7 @@ return -1; } - if (IS_TOP_ALIGNED_ADDRESS(offset)) + if (IS_HOST_SPACE_ADDRESS(offset)) offset = convert_to_from_absolute_top_aligned(param.image_region, -offset); if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { @@ -646,7 +646,7 @@ * passed in by the caller. */ if (param.stage_xip) { - if (!IS_TOP_ALIGNED_ADDRESS(address)) + if (!IS_HOST_SPACE_ADDRESS(address)) address = -convert_to_from_absolute_top_aligned( param.image_region, address); } else { diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 7dbc1f5..9f62e77 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -15,7 +15,12 @@ /* Endianness */ #include "swab.h" -#define IS_TOP_ALIGNED_ADDRESS(x) ((uint32_t)(x) > 0x80000000) +/* + * There are two address spaces that this tool deals with - SPI flash address space and host + * address space. This macros checks if the address is greater than 2GiB under the assumption + * that the low MMIO lives in the top half of the 4G address space of the host. + */ +#define IS_HOST_SPACE_ADDRESS(addr) ((uint32_t)(addr) > 0x80000000) #define unused __attribute__((unused)) -- To view, visit https://review.coreboot.org/c/coreboot/+/47830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bb505df62ac41f1d364a662be145603c0bd5fa Gerrit-Change-Number: 47830 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: util/cbfstool: Treat region offsets differently than absolute addresses
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47829 ) Change subject: util/cbfstool: Treat region offsets differently than absolute addresses ...................................................................... util/cbfstool: Treat region offsets differently than absolute addresses cbfstool overloads baseaddress to represent multiple things: 1. Address in SPI flash space 2. Address in host space (for x86 platforms) 3. Offset from end of region (accepted as negative number) This was done so that the different functions that use these addresses/offsets don't need to be aware of what the value represents and can use the helper functions convert_to_from* to get the required values. Thus, even if the user provides a negative value to represent offset from end of region, it was stored as an unsigned integer. There are special checks in convert_to_from_top_aligned which guesses if the value provided is really an offset from the end of region and converts it to an offset from start of region. This has worked okay until now for x86 platforms because there is a single fixed decode window mapping the SPI flash to host address space. However, going forward new platforms might need to support more decode windows that are not contiguous in the host space. Thus, it is important to distinguish between offsets from end of region and addresses in host/SPI flash space and treat them separately. As a first step towards supporting this requirement for multiple decode windows on new platforms, this change handles the negative offset provided as input in dispatch_command before the requested cbfs operation is performed. This change adds baseaddress_input, headeroffset_input and cbfsoffset_input to struct param and converts them to offsets from start of region before storing into baseaddress, headeroffset and cbfsoffset if the inputs are negative. In follow up changes, cbfstool will be extended to add support for multiple decode windows. TEST=Verified using abuild with timeless option for all coreboot boards that there is no change in the resultant coreboot.rom file. Change-Id: Ib74a7e6ed9e88fbc5489640d73bedac14872953f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c 2 files changed, 54 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47829/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index a042f0d..3f1bf43 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -277,14 +277,6 @@ bootblock_offset, bootblock->size, header_offset, sizeof(image->header), entries_offset); - // Adjust legacy top-aligned address to ROM offset. - if (IS_TOP_ALIGNED_ADDRESS(entries_offset)) - entries_offset = size + (int32_t)entries_offset; - if (IS_TOP_ALIGNED_ADDRESS(bootblock_offset)) - bootblock_offset = size + (int32_t)bootblock_offset; - if (IS_TOP_ALIGNED_ADDRESS(header_offset)) - header_offset = size + (int32_t)header_offset; - DEBUG("cbfs_create_image: (real offset) bootblock=0x%x, " "header=0x%x, entries_offset=0x%x\n", bootblock_offset, header_offset, entries_offset); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index d2df1cc..c719b8f 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -47,15 +47,22 @@ uint64_t u64val; uint32_t type; uint32_t baseaddress; + /* + * Input can be negative. It will be transformed to corresponding region offset and + * stored in baseaddress. + */ + long long int baseaddress_input; uint32_t baseaddress_assigned; uint32_t loadaddress; uint32_t headeroffset; + long long int headeroffset_input; uint32_t headeroffset_assigned; uint32_t entrypoint; uint32_t size; uint32_t alignment; uint32_t pagesize; uint32_t cbfsoffset; + long long int cbfsoffset_input; uint32_t cbfsoffset_assigned; uint32_t arch; uint32_t padding; @@ -102,8 +109,7 @@ /* * Converts between offsets from the start of the specified image region and - * "top-aligned" offsets from the top of the entire boot media. See comment - * below for convert_to_from_top_aligned() about forming addresses. + * "top-aligned" offsets from the top of the entire boot media. */ static unsigned convert_to_from_absolute_top_aligned( const struct buffer *region, unsigned offset) @@ -116,25 +122,26 @@ } /* - * Converts between offsets from the start of the specified image region and - * "top-aligned" offsets from the top of the image region. Works in either - * direction: pass in one type of offset and receive the other type. - * N.B. A top-aligned offset is always a positive number, and should not be - * confused with a top-aligned *address*, which is its arithmetic inverse. */ -static unsigned convert_to_from_top_aligned(const struct buffer *region, - unsigned offset) + * This function takes offset value which represents the offset from one end of the region and + * returns the offset from the other end of the region. offset is expected to be positive. + */ +static unsigned convert_region_offset(unsigned offset) { - assert(region); + size_t size; - /* Cover the situation where a negative base address is given by the - * user. Callers of this function negate it, so it'll be a positive - * number smaller than the region. - */ - if ((offset > 0) && (offset < region->size)) { - return region->size - offset; + if (param.size) { + size = param.size; + } else { + assert(param.image_region); + size = param.image_region->size; } - return convert_to_from_absolute_top_aligned(region, offset); + if (size < offset) { + ERROR("Cannot convert region offset (size=0x%zx, offset=0x%x\n", size, offset); + return 0; + } + + return size - offset; } static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size, @@ -242,10 +249,6 @@ goto done; } - if (IS_TOP_ALIGNED_ADDRESS(offset)) - offset = convert_to_from_top_aligned(param.image_region, - -offset); - header = cbfs_create_file_header(CBFS_COMPONENT_RAW, buffer.size, name); if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { @@ -434,8 +437,7 @@ buffer_clone(buffer, &new_bootblock); /* Update the location (offset) of bootblock in the region */ - *offset = convert_to_from_top_aligned(param.image_region, - buffer_size(buffer)); + *offset = convert_region_offset(buffer_size(buffer)); return 0; } @@ -519,11 +521,9 @@ /* to the cbfs file and therefore set the position */ /* the real beginning of the data. */ if (type == CBFS_COMPONENT_STAGE) - attrs->position = htonl(offset + - sizeof(struct cbfs_stage)); + attrs->position = htonl(offset - sizeof(struct cbfs_stage)); else if (type == CBFS_COMPONENT_SELF) - attrs->position = htonl(offset + - sizeof(struct cbfs_payload)); + attrs->position = htonl(offset - sizeof(struct cbfs_payload)); else attrs->position = htonl(offset); } @@ -564,8 +564,8 @@ } if (IS_TOP_ALIGNED_ADDRESS(offset)) - offset = convert_to_from_top_aligned(param.image_region, - -offset); + offset = convert_to_from_absolute_top_aligned(param.image_region, + -offset); if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); free(header); @@ -1336,6 +1336,16 @@ {NULL, 0, 0, 0 } }; +static uint32_t get_region_offset(long long int offset) +{ + /* If offset is not negative, no transformation required. */ + if (offset >= 0) + return offset; + + /* Calculate offset from start of region. */ + return convert_region_offset(-offset); +} + static int dispatch_command(struct command command) { if (command.accesses_region) { @@ -1373,6 +1383,17 @@ return 1; } } + + /* + * Once image region is read, input offsets can be adjusted accordingly if the + * inputs are provided as negative integers i.e. offsets from end of region. + */ + if (param.baseaddress_assigned) + param.baseaddress = get_region_offset(param.baseaddress_input); + if (param.headeroffset_assigned) + param.headeroffset = get_region_offset(param.headeroffset_input); + if (param.cbfsoffset_assigned) + param.cbfsoffset = get_region_offset(param.cbfsoffset_input); } if (command.function()) { @@ -1592,7 +1613,7 @@ param.source_region = optarg; break; case 'b': - param.baseaddress = strtoul(optarg, &suffix, 0); + param.baseaddress_input = strtoll(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { ERROR("Invalid base address '%s'.\n", optarg); @@ -1643,8 +1664,7 @@ param.bootblock = optarg; break; case 'H': - param.headeroffset = strtoul( - optarg, &suffix, 0); + param.headeroffset_input = strtoll(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { ERROR("Invalid header offset '%s'.\n", optarg); @@ -1680,7 +1700,7 @@ param.force_pow2_pagesize = 1; break; case 'o': - param.cbfsoffset = strtoul(optarg, &suffix, 0); + param.cbfsoffset_input = strtoll(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { ERROR("Invalid cbfs offset '%s'.\n", optarg); @@ -1817,6 +1837,7 @@ seen_primary_cbfs = true; param.image_region = image_regions + region; + if (dispatch_command(commands[i])) { partitioned_file_close(param.image_file); return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/47829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74a7e6ed9e88fbc5489640d73bedac14872953f Gerrit-Change-Number: 47829 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: mb/google/volteer: ACPI nodes for volteer2_ti50
by Jes Klinke (Code Review) 08 Dec '20

08 Dec '20

Jes Klinke has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48223 ) Change subject: mb/google/volteer: ACPI nodes for volteer2_ti50 ...................................................................... mb/google/volteer: ACPI nodes for volteer2_ti50 Unique among the Volteer devices, the volteer2_ti50 variant connects to the TPM via I2C. This CL introduces the proper devicestree declarations for the Linux kernel to recognize that. overridetree.cb is shared between "sub"-variants volteer2 and volteer2_ti50, so both will have two TPM nodes, the I2C being disabled by default. The odd _ti50 variant then has code in variant.c to enable the I2C node and disable the SPI node. BUG=b:173461736 TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/Makefile.inc M src/mainboard/google/volteer/variants/volteer2/overridetree.cb A src/mainboard/google/volteer/variants/volteer2/variant.c 6 files changed, 57 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/48223/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 7536dc5..43304cb 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -61,6 +61,7 @@ select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVER_I2C_TPM_ACPI # Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board config BOARD_GOOGLE_VOLTEER2_TI50 @@ -69,6 +70,7 @@ select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVER_I2C_TPM_ACPI config BOARD_GOOGLE_VOXEL bool "-> Voxel" diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index ea9e08f..1f20e18 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -23,8 +23,8 @@ static bool is_port1(struct device *dev) { - return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == 1 && - dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == 1 + && dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; } static void typec_orientation_fixup(void) @@ -53,14 +53,15 @@ if (!conn) return; - if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) || - fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) { + if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) + || fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) + || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) + || fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) { struct drivers_intel_pmc_mux_conn_config *config = conn->chip_info; if (config) { - printk(BIOS_INFO, "Configure Right Type-C port orientation for retimer\n"); + printk(BIOS_INFO, + "Configure Right Type-C port orientation for retimer\n"); config->sbu_orientation = TYPEC_ORIENTATION_NORMAL; } } @@ -70,6 +71,11 @@ { mainboard_ec_init(); typec_orientation_fixup(); + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ } static void add_fw_config_oem_string(const struct fw_config *config, void *arg) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 8408198..4d5dc87 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -21,4 +21,7 @@ const struct ddr_memory_cfg *variant_memory_params(void); int variant_memory_sku(void); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/volteer2/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc index 13269db..04af3ae 100644 --- a/src/mainboard/google/volteer/variants/volteer2/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc @@ -3,3 +3,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index a1012a6..916777c 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -201,6 +201,11 @@ register "key.label" = ""pen_eject"" device generic 0 on end end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device i2c 50 off end + end end device ref i2c2 on chip drivers/i2c/sx9310 diff --git a/src/mainboard/google/volteer/variants/volteer2/variant.c b/src/mainboard/google/volteer/variants/volteer2/variant.c new file mode 100644 index 0000000..057bb8a --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/variant.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <soc/pci_devs.h> +#include <acpi/acpi_device.h> + +extern struct chip_operations drivers_i2c_tpm_ops; + +static bool match_i2c_tpm(DEVTREE_CONST struct device *dev) +{ + return dev->chip_ops == &drivers_i2c_tpm_ops; +} + +/* + * This function runs only on the volteer_ti50 variant, which has the GSC on a + * reworked I2C bus. + */ +static void devtree_enable_i2c_tpm(void) +{ + struct device *spi_tpm = pcidev_path_on_root(PCH_DEVFN_GSPI0)->link_list->children; + struct device *i2c_tpm = dev_find_matching_device_on_bus( + pcidev_path_on_root(PCH_DEVFN_I2C1)->link_list, match_i2c_tpm); + if (!i2c_tpm || !spi_tpm) + return; + spi_tpm->enabled = 0; + i2c_tpm->enabled = 1; +} + +void variant_devtree_update(void) +{ + if (CONFIG(MAINBOARD_HAS_I2C_TPM_CR50)) + devtree_enable_i2c_tpm(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b Gerrit-Change-Number: 48223 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/google/volteer/variants: Update Power Limit2 minimum value
by Sumeet R Pawnikar (Code Review) 08 Dec '20

08 Dec '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48292 ) Change subject: mb/google/volteer/variants: Update Power Limit2 minimum value ...................................................................... mb/google/volteer/variants: Update Power Limit2 minimum value Update Power Limit2 (PL2) minimum value to the same as maximum value for volteer variants like baseboard, delbin, eldrid, terrador and todor. All other variants uses the DTT entries from baseboard devicetree since there is no override present for those variants. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on volteer system Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/48292/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1b3b1cc..353aa27 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -401,7 +401,7 @@ .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, - .pl2 = {.min_power = 15000, + .pl2 = {.min_power = 60000, .max_power = 60000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 904f3e0..c0eaedb 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -102,7 +102,7 @@ .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, - .pl2 = {.min_power = 15000, + .pl2 = {.min_power = 51000, .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 129d704..1b86e0e 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -102,7 +102,7 @@ .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, - .pl2 = {.min_power = 15000, + .pl2 = {.min_power = 51000, .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 45f1033..039dc85 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -48,7 +48,7 @@ .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, - .pl2 = {.min_power = 9000, + .pl2 = {.min_power = 40000, .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index bbfc016..be1b250 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -50,7 +50,7 @@ .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, - .pl2 = {.min_power = 9000, + .pl2 = {.min_power = 40000, .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/48292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6 Gerrit-Change-Number: 48292 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/gpio_defs: Add a macro for EDGE_BOTH trigger pad
by Kaiyen Chang (Code Review) 08 Dec '20

08 Dec '20

Hello Kaiyen Chang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48302 to review the following change. Change subject: soc/intel/common/gpio_defs: Add a macro for EDGE_BOTH trigger pad ...................................................................... soc/intel/common/gpio_defs: Add a macro for EDGE_BOTH trigger pad Adds a new macro to configure the pad to EDGE_BOTH trigger mode. BUG=b:174336541 TEST=emerge-dedede coreboot Signed-off-by: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com> Change-Id: Icc805f5cfe45e5cc991fb0561f669907ac454a03 --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/48302/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 422720b..f082470 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -276,6 +276,12 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_GPIO_DRIVER_EDGE_BOTH(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_CFG0_TRIG_EDGE_BOTH, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE)) + #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ -- To view, visit https://review.coreboot.org/c/coreboot/+/48302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc805f5cfe45e5cc991fb0561f669907ac454a03 Gerrit-Change-Number: 48302 Gerrit-PatchSet: 1 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Reviewer: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: add maintainers for AMD family 17h and 19h reference boards
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48382 ) Change subject: MAINTAINERS: add maintainers for AMD family 17h and 19h reference boards ...................................................................... MAINTAINERS: add maintainers for AMD family 17h and 19h reference boards Change-Id: I90673a3244c5f2d5eda8e8805779fdad3a2b3226 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M MAINTAINERS 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48382/1 diff --git a/MAINTAINERS b/MAINTAINERS index 14444aa..49fbc38 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -137,6 +137,14 @@ # Mainboards ################################################################################ +AMD family 17h and 19h reference boards +M: Marshall Dawson <marshalldawson3rd(a)gmail.com> +M: Felix Held <felix-coreboot(a)felixheld.de> +M: Jason Glenesk <jason.glenesk(a)gmail.com> +S: Maintained +F: src/mainboard/amd/majolica/ +F: src/mainboard/amd/mandolin/ + APPLE MAINBOARDS M: Evgeny Zinoviev <me(a)ch1p.io> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/48382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90673a3244c5f2d5eda8e8805779fdad3a2b3226 Gerrit-Change-Number: 48382 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S Audio for ADLRVP
by Sathya Prakash M R (Code Review) 08 Dec '20

08 Dec '20

Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48000 ) Change subject: mb/intel/adlrvp: Enable I2S Audio for ADLRVP ...................................................................... Patch Set 7: Code-Review+1 This looks good. with this we can use RT711 when no I2S cards are present. Helps all teams. @subrata : this can be merged once we validate on both Lp4x and DDR5. -- To view, visit https://review.coreboot.org/c/coreboot/+/48000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Gerrit-Change-Number: 48000 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 10:10:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp/fsp2_0: Use more direct includes
by Patrick Rudolph (Code Review) 08 Dec '20

08 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47761 ) Change subject: drivers/fsp/fsp2_0: Use more direct includes ...................................................................... drivers/fsp/fsp2_0: Use more direct includes * Forwared declare structs in fsp/util.h * Include the correct header files in source files directly * Stop including everything in fsp/util.h and fsp/debug.h * This reduces the used headers to prevent conflicts with non FSP header files included in the following patch Change-Id: I8668608a6867876268b08cbd6d9eeafd9cd35687 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/debug.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c M src/soc/intel/apollolake/meminit.c 12 files changed, 21 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/47761/1 diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 3d66587..650e648 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -3,7 +3,7 @@ #include <console/console.h> #include <console/streams.h> #include <cpu/x86/mtrr.h> -#include <fsp/util.h> +#include <fsp/debug.h> asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) { diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 60ab7cb..9d29f4e 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> +#include <fsp/debug.h> #include <stdint.h> #include <string.h> diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index f21ebfe..1529148 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <console/console.h> -#include <fsp/util.h> +#include <fsp/debug.h> struct hob_type_name { uint16_t type; diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 9bfb0f1..28b45af 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -2,7 +2,7 @@ #include <cbmem.h> #include <console/console.h> -#include <fsp/util.h> +#include <fsp/debug.h> void fsp_verify_memory_init_hobs(void) { diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 97e2fea..3c2978c 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -31,6 +31,10 @@ END_OF_FIRMWARE = 0xF0 }; +struct fsp_notify_params { + enum fsp_notify_phase phase; +}; + /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index e3d1918..5afaec3 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -3,7 +3,9 @@ #ifndef _FSP2_0_DEBUG_H_ #define _FSP2_0_DEBUG_H_ +#include <fsp/api.h> #include <fsp/util.h> +#include <fsp/info_header.h> /* FSP debug API */ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index a57b1bb..077f9cd 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -6,8 +6,6 @@ #include <boot/coreboot_tables.h> #include <commonlib/region.h> #include <arch/cpu.h> -#include <fsp/api.h> -#include <fsp/info_header.h> #include <memrange.h> #include <program_loading.h> #include <types.h> @@ -19,10 +17,6 @@ uint16_t length; } __packed; -struct fsp_notify_params { - enum fsp_notify_phase phase; -}; - enum fsp_multi_phase_action { GET_NUMBER_OF_PHASES = 0, EXECUTE_PHASE = 1 @@ -91,6 +85,7 @@ void lb_string_platform_blob_version(struct lb_header *header); void report_fspt_output(void); +struct fsp_header; /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, const struct region_device *rdev); @@ -131,7 +126,6 @@ (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); typedef asmlinkage uint32_t (*fsp_multi_phase_si_init_fn)(struct fsp_multi_phase_params *); +struct fsp_notify_params; typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *); -#include <fsp/debug.h> - #endif /* _FSP2_0_UTIL_H_ */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 68cc121..3542c8b 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -11,6 +11,7 @@ #include <elog.h> #include <fsp/api.h> #include <fsp/util.h> +#include <fsp/debug.h> #include <memrange.h> #include <mrc_cache.h> #include <program_loading.h> diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf12..3632fca 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -3,6 +3,9 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <fsp/api.h> +#include <fsp/info_header.h> +#include <fsp/debug.h> #include <fsp/util.h> #include <timestamp.h> diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0b6540e..a9b39c0 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -6,6 +6,7 @@ #include <commonlib/stdlib.h> #include <console/console.h> #include <fsp/api.h> +#include <fsp/debug.h> #include <fsp/util.h> #include <program_loading.h> #include <soc/intel/common/vbt.h> diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index acc3f4b..3a980be 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -7,7 +7,10 @@ #include <commonlib/bsd/compression.h> #include <commonlib/fsp.h> #include <console/console.h> +#include <fsp/api.h> #include <fsp/util.h> +#include <fsp/info_header.h> +#include <fsp/debug.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 8601571..6d969b2 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <fsp/api.h> #include <fsp/util.h> #include <memory_info.h> #include <soc/meminit.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/47761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8668608a6867876268b08cbd6d9eeafd9cd35687 Gerrit-Change-Number: 47761 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Disable HWP support
by Sugnan Prabhu S (Code Review) 08 Dec '20

08 Dec '20

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48459 to review the following change. Change subject: soc/intel/alderlake: Disable HWP support ...................................................................... soc/intel/alderlake: Disable HWP support Change-Id: I88c9907cdbe9d237f058f5362db42276ecf4770b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48459/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index a21ca4a..f176785 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -273,7 +273,7 @@ sizeof(config->PcieRpClkReqDetect)); params->PmSupport = 1; - params->Hwp = 1; + params->Hwp = 0; params->Cx = 1; params->PsOnEnable = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/48459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c9907cdbe9d237f058f5362db42276ecf4770b Gerrit-Change-Number: 48459 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/intel/sm: Disable IGD
by Sugnan Prabhu S (Code Review) 08 Dec '20

08 Dec '20

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48458 to review the following change. Change subject: mb/intel/sm: Disable IGD ...................................................................... mb/intel/sm: Disable IGD Disabled IGD until the IGD is enabled on ADL-P chrome Change-Id: I7808bdf204b615ec64762517b830686c45187090 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48458/1 diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 5a4d9a5..ee85d4b 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -1,5 +1,5 @@ chip soc/intel/alderlake - + device cpu_cluster 0 on device lapic 0 on end end @@ -180,7 +180,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Graphics + device pci 02.0 off end # Graphics device pci 04.0 on end # DPTF device pci 05.0 on end # IPU device pci 06.0 on end # PEG60 -- To view, visit https://review.coreboot.org/c/coreboot/+/48458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7808bdf204b615ec64762517b830686c45187090 Gerrit-Change-Number: 48458 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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