Hello Felix Singer, Nico Huber, Arthur Heymans, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48419
to review the following change.
Change subject: nb/intel/sandybridge: Extend rcven coarse range with fast RAM
......................................................................
nb/intel/sandybridge: Extend rcven coarse range with fast RAM
If memory frequency is high, extend rcven coarse search range two
additional QCLKs to prevent raminit errors on some mainboards.
Tested on Asus P8Z77-V LX2, memory can now run at DDR3-2133 speeds.
Change-Id: Ia65ee41f75974a7095b7dec54168fb889ecbe4a0
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48419/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index f495d9d..6949420 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1207,7 +1207,10 @@
u32 statistics[NUM_LANES][4];
int lane;
- for (u32 logic_delay = 0; logic_delay < 2; logic_delay++) {
+ /* Extend coarse search range for faster clock speeds */
+ const u32 max_logic_delay = ctrl->tCK < TCK_933MHZ ? 4 : 2;
+
+ for (u32 logic_delay = 0; logic_delay < max_logic_delay; logic_delay++) {
for (rcven = 0; rcven < 64; rcven++) {
FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven =
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia65ee41f75974a7095b7dec54168fb889ecbe4a0
Gerrit-Change-Number: 48419
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28101 )
Change subject: Makefile: Add $(xcompile) to specify where to write xcompile
......................................................................
Patch Set 11:
PTAL
--
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Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0
Gerrit-Change-Number: 28101
Gerrit-PatchSet: 11
Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
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Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org>
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Gerrit-Comment-Date: Mon, 07 Dec 2020 16:11:31 +0000
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Meng-Huan Yu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48259 )
Change subject: libpayload: Unified the type of _start, _end in ARM64 mmu.h
......................................................................
libpayload: Unified the type of _start, _end in ARM64 mmu.h
The type of _start and _end symbols in depthcharge is "uint8_t",
it will cause compile error if trying to includes arm64/arch/mmu.h from
depthcharge.
BUG=b:171858277
TEST=Built on arm64 board
emerge-asurada libpayload depthcharge
Signed-off-by: Meng-Huan Yu <menghuan(a)google.com>
Change-Id: I5756f63f5cae22ecda6873c711bef16aeabc89f6
---
M payloads/libpayload/include/arm64/arch/mmu.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48259/1
diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h
index 9ead5d6..1126e76 100644
--- a/payloads/libpayload/include/arm64/arch/mmu.h
+++ b/payloads/libpayload/include/arm64/arch/mmu.h
@@ -46,7 +46,7 @@
* Symbols taken from linker script
* They mark the start and end of the region used by payload
*/
-extern char _start[], _end[];
+extern uint8_t _start, _end;
/* Memory attributes for mmap regions
* These attributes act as tag values for memrange regions
--
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