coreboot-gerrit December 2020

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Change in coreboot[master]: G505S good IRQs: scripts for applying the unofficial (not-merged-yet)...
by Mike Banon (Code Review) 07 Dec '20

07 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48266 ) Change subject: G505S good IRQs: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... G505S good IRQs: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply four changes CB:48161, CB:48162, CB:48163, CB:48179 - for the good IRQs on AMD Lenovo G505S. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I59fde56d1a630371d6eb72b59a14b3408fac074c --- A apply_irq_patches.sh A check_irq_patches.sh A get_irq_patches.sh A sha256sums_irq_correct.txt 4 files changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48266/1 diff --git a/apply_irq_patches.sh b/apply_irq_patches.sh new file mode 100755 index 0000000..fdaa19c --- /dev/null +++ b/apply_irq_patches.sh @@ -0,0 +1,22 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +patch -p1 < "./9ffa290.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +patch -p1 < "./8517e5a.diff" +### diff --git a/check_irq_patches.sh b/check_irq_patches.sh new file mode 100755 index 0000000..8069c95 --- /dev/null +++ b/check_irq_patches.sh @@ -0,0 +1,15 @@ +#!/bin/sh +rm -f "./sha256sums_irq_my.txt" +sha256sum "./cd096f9.diff" > "./sha256sums_irq_my.txt" +sha256sum "./42aeed4.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./9ffa290.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./8517e5a.diff" >> "./sha256sums_irq_my.txt" +if cmp -s "./sha256sums_irq_my.txt" "./sha256sums_irq_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_irq_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_irq_my.txt and ./sha256sums_irq_correct.txt" + exit 1 +fi +# diff --git a/get_irq_patches.sh b/get_irq_patches.sh new file mode 100755 index 0000000..833b813 --- /dev/null +++ b/get_irq_patches.sh @@ -0,0 +1,30 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +rm -f "./cd096f9.diff" +wget "https://review.coreboot.org/changes/48161/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +rm -f "./42aeed4.diff" +wget "https://review.coreboot.org/changes/48162/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +rm -f "./9ffa290.diff" +wget "https://review.coreboot.org/changes/48163/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./9ffa290.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +rm -f "./8517e5a.diff" +wget "https://review.coreboot.org/changes/48179/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8517e5a.diff" +### diff --git a/sha256sums_irq_correct.txt b/sha256sums_irq_correct.txt new file mode 100755 index 0000000..0d83e64 --- /dev/null +++ b/sha256sums_irq_correct.txt @@ -0,0 +1,4 @@ +9fd4cca063bb6e6c9063f00f4c972c019d616560883b9bda76177a462817ae8e ./cd096f9.diff +357a1e1e9f250149127fa8f7aac089e481a39f96b313ae1a0310c7e5d22faa72 ./42aeed4.diff +306e2a1e92b5b0c5885d7384c4b99ecaa83935a9e5242fb720266c0eb1d98529 ./9ffa290.diff +ab0b347af164e5c50c580f036e7ed55757e90158ad3cb04fc2f8154b5392f804 ./8517e5a.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/48266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59fde56d1a630371d6eb72b59a14b3408fac074c Gerrit-Change-Number: 48266 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Tim Wawrzynczak (Code Review) 07 Dec '20

07 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48194 ) Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 50: 3 USB2_BIAS_39P35MV https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 51: 2 USB2_PRE_EMP_ON https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 52: 7 USB2_BIAS_56P3MV https://review.coreboot.org/c/coreboot/+/48194/3/src/mainboard/google/volte… PS3, Line 53: 1 USB2_HALF_BIT_PRE_EMP -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Dec 2020 19:12:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asus/a88xm-e: update the ACPI routing to match the new IRQ routing
by Mike Banon (Code Review) 07 Dec '20

07 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48425 ) Change subject: asus/a88xm-e: update the ACPI routing to match the new IRQ routing ...................................................................... asus/a88xm-e: update the ACPI routing to match the new IRQ routing Update the ACPI routing in accordance with the new IRQ tables. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I53850e89bbc192b11cbc56525287ebbb05094b22 --- M src/mainboard/asus/a88xm-e/acpi/routing.asl 1 file changed, 135 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/48425/1 diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl index 99511c5..1f75602 100644 --- a/src/mainboard/asus/a88xm-e/acpi/routing.asl +++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl @@ -4,217 +4,219 @@ Name(PR0, Package(){ /* NB devices */ /* Bus 0, Dev 0 - F15 Host Controller */ + /* IOMMU: 0:00.02 - IRQ 3 */ Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 1, INTB, 0 }, Package(){0x0000FFFF, 2, INTC, 0 }, Package(){0x0000FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics (IGP) */ + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + Package(){0x0001FFFF, 0, INTA, 0 }, + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + Package(){0x0001FFFF, 1, INTB, 0 }, - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */ + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + Package(){0x0002FFFF, 0, INTA, 0 }, + Package(){0x0002FFFF, 1, INTB, 0 }, + Package(){0x0002FFFF, 2, INTC, 0 }, + Package(){0x0002FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 5 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - - * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB - */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + Package(){0x0006FFFF, 0, INTB, 0 }, + Package(){0x0006FFFF, 1, INTC, 0 }, + Package(){0x0006FFFF, 2, INTD, 0 }, + Package(){0x0006FFFF, 3, INTA, 0 }, /* SB devices */ - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + /* USB XHCI: 0:10.00 - IRQ 5 */ Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ + /* SATA: 0:11.00 - IRQ 7 */ Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + /* USB EHCI1: 0:12.02 - IRQ 4 */ + Package(){0x0012FFFF, 1, INTB, 0 }, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + Package(){0x0013FFFF, 0, INTC, 0 }, + /* USB EHCI2: 0:13.02 - IRQ 4 */ + Package(){0x0013FFFF, 1, INTB, 0 }, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + Package(){0x0016FFFF, 0, INTC, 0 }, + /* USB EHCI3: 0:16.02 - IRQ 4 */ + Package(){0x0016FFFF, 1, INTB, 0 }, + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + /* USB OHCI4: 0:14.05 - IRQ 5 */ + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + Package(){0x0015FFFF, 0, INTB, 0 }, + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + Package(){0x0015FFFF, 1, INTC, 0 }, + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + Package(){0x0015FFFF, 2, INTD, 0 }, + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ + Package(){0x0015FFFF, 3, INTA, 0 }, }) Name(APR0, Package(){ /* NB devices in APIC mode */ /* Bus 0, Dev 0 - F15 Host Controller */ + /* IOMMU: 0:00.02 - IRQ 3 */ Package(){0x0000FFFF, 0, 0, 16 }, Package(){0x0000FFFF, 1, 0, 17 }, Package(){0x0000FFFF, 2, 0, 18 }, Package(){0x0000FFFF, 3, 0, 19 }, + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics (IGP) */ + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + Package(){0x0001FFFF, 0, 0, 16 }, + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + Package(){0x0001FFFF, 1, 0, 17 }, - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - - /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */ + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + Package(){0x0002FFFF, 0, 0, 16 }, + Package(){0x0002FFFF, 1, 0, 17 }, + Package(){0x0002FFFF, 2, 0, 18 }, + Package(){0x0002FFFF, 3, 0, 19 }, + /* Bus 0, Dev 4 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ Package(){0x0004FFFF, 0, 0, 16 }, Package(){0x0004FFFF, 1, 0, 17 }, Package(){0x0004FFFF, 2, 0, 18 }, Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - - * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB - */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, + /* Bus 0, Dev 5 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + Package(){0x0006FFFF, 0, 0, 17 }, + Package(){0x0006FFFF, 1, 0, 18 }, + Package(){0x0006FFFF, 2, 0, 19 }, + Package(){0x0006FFFF, 3, 0, 16 }, /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ + /* USB XHCI: 0:10.00 - IRQ 5 */ + Package(){0x0010FFFF, 0, 0, 18 }, + /* SATA: 0:11.00 - IRQ 7 */ Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 21 PCIE Bridge */ + /* USB OHCI1: 0:12.00 - IRQ 5 */ + Package(){0x0012FFFF, 0, 0, 18 }, + /* USB EHCI1: 0:12.02 - IRQ 4 */ + Package(){0x0012FFFF, 1, 0, 17 }, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + Package(){0x0013FFFF, 0, 0, 18 }, + /* USB EHCI2: 0:13.02 - IRQ 4 */ + Package(){0x0013FFFF, 1, 0, 17 }, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + Package(){0x0016FFFF, 0, 0, 18 }, + /* USB EHCI3: 0:16.02 - IRQ 4 */ + Package(){0x0016FFFF, 1, 0, 17 }, + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + /* USB OHCI4: 0:14.05 - IRQ 5 */ + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ Package(){0x0015FFFF, 0, 0, 17 }, + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ Package(){0x0015FFFF, 1, 0, 18 }, + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ Package(){0x0015FFFF, 2, 0, 19 }, + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ Package(){0x0015FFFF, 3, 0, 16 }, }) Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, }) - /* black slot */ Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 1, INTB, 0 }, Package(){0x0000FFFF, 2, INTC, 0 }, Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ Package(){0x0000FFFF, 0, 0, 16 }, Package(){0x0000FFFF, 1, 0, 17 }, Package(){0x0000FFFF, 2, 0, 18 }, Package(){0x0000FFFF, 3, 0, 19 }, }) - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ Package(){0x0000FFFF, 0, INTB, 0 }, Package(){0x0000FFFF, 1, INTC, 0 }, Package(){0x0000FFFF, 2, INTD, 0 }, Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ Package(){0x0000FFFF, 0, 0, 17 }, Package(){0x0000FFFF, 1, 0, 18 }, Package(){0x0000FFFF, 2, 0, 19 }, Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, }) - Name(PBR0, Package(){ - /* PCIx1 on SB */ + /* PCIe x1 slot on SB - Hooked to PCIe Bridge 0 */ Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 1, INTB, 0 }, Package(){0x0000FFFF, 2, INTC, 0 }, Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(ABR0, Package(){ - /* PCIx1 on SB */ + /* PCIe x1 slot on SB - Hooked to PCIe Bridge 0 */ Package(){0x0000FFFF, 0, 0, 0x10 }, Package(){0x0000FFFF, 1, 0, 0x11 }, Package(){0x0000FFFF, 2, 0, 0x12 }, @@ -222,21 +224,20 @@ }) Name(PBR1, Package(){ - /* Onboard network */ + /* Onboard network - Hooked to PCIe Bridge 1 */ Package(){0x0000FFFF, 0, INTB, 0 }, Package(){0x0000FFFF, 1, INTC, 0 }, Package(){0x0000FFFF, 2, INTD, 0 }, Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(ABR1, Package(){ - /* Onboard network */ + /* Onboard network - Hooked to PCIe Bridge 1 */ Package(){0x0000FFFF, 0, 0, 0x11 }, Package(){0x0000FFFF, 1, 0, 0x12 }, Package(){0x0000FFFF, 2, 0, 0x13 }, Package(){0x0000FFFF, 3, 0, 0x10 }, }) - - /* SB PCI Bridge */ + /* SB PCI Bridge */ Name(PCIB, Package(){ /* PCI slots: slot 0 behind Dev14, Fun4. */ Package(){0x0005FFFF, 0, 0, 0x14 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/48425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53850e89bbc192b11cbc56525287ebbb05094b22 Gerrit-Change-Number: 48425 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Extend rcven coarse range with fast RAM
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Hello Felix Singer, Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48419 to review the following change. Change subject: nb/intel/sandybridge: Extend rcven coarse range with fast RAM ...................................................................... nb/intel/sandybridge: Extend rcven coarse range with fast RAM If memory frequency is high, extend rcven coarse search range two additional QCLKs to prevent raminit errors on some mainboards. Tested on Asus P8Z77-V LX2, memory can now run at DDR3-2133 speeds. Change-Id: Ia65ee41f75974a7095b7dec54168fb889ecbe4a0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48419/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index f495d9d..6949420 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1207,7 +1207,10 @@ u32 statistics[NUM_LANES][4]; int lane; - for (u32 logic_delay = 0; logic_delay < 2; logic_delay++) { + /* Extend coarse search range for faster clock speeds */ + const u32 max_logic_delay = ctrl->tCK < TCK_933MHZ ? 4 : 2; + + for (u32 logic_delay = 0; logic_delay < max_logic_delay; logic_delay++) { for (rcven = 0; rcven < 64; rcven++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rcven = -- To view, visit https://review.coreboot.org/c/coreboot/+/48419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia65ee41f75974a7095b7dec54168fb889ecbe4a0 Gerrit-Change-Number: 48419 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] plot TxDQS
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Hello Felix Singer, Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48418 to review the following change. Change subject: [WIP] plot TxDQS ...................................................................... [WIP] plot TxDQS Change-Id: I08677ee75826e1638142e221b4b5eedfd25f8b26 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/48418/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b0a75fc..f495d9d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1738,6 +1738,17 @@ (tx_dqs % 32)) & 1); } } + + printk(BIOS_ERR, "channel %d rank %d results:\n", channel, slotrank); + printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + for (tx_dqs = 0; tx_dqs <= 128; tx_dqs++) { + printk(BIOS_ERR, "% 5d\t", tx_dqs); + FOR_ALL_LANES { + printk(BIOS_ERR, "%c", statistics[lane][tx_dqs] ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + FOR_ALL_LANES { struct run rn = get_longest_zero_run(statistics[lane], 128); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/48418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08677ee75826e1638142e221b4b5eedfd25f8b26 Gerrit-Change-Number: 48418 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOTFORMERGE] force DDR3-2133 speeds
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Hello Felix Singer, Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48417 to review the following change. Change subject: [NOTFORMERGE] force DDR3-2133 speeds ...................................................................... [NOTFORMERGE] force DDR3-2133 speeds Change-Id: Ie4a057c736f85e246f00f10e9a07368a92ecd859 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/48417/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 3613c05..49b17bf 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -294,7 +294,7 @@ } if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) - return TCK_1333MHZ; + return TCK_1066MHZ; rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); @@ -348,6 +348,9 @@ ctrl->tCK = get_mem_min_tck(); + ctrl->cas_supported |= 1 << (14 - 4); + ctrl->cas_supported |= 1 << (13 - 4); + /* Find CAS latency */ while (1) { /* @@ -379,6 +382,9 @@ printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; + + if (NS2MHZ_DIV256 / ctrl->tCK == 800) + die("rip"); } static void dram_timing(ramctr_timing *ctrl) -- To view, visit https://review.coreboot.org/c/coreboot/+/48417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a057c736f85e246f00f10e9a07368a92ecd859 Gerrit-Change-Number: 48417 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Add $(xcompile) to specify where to write xcompile
by Raul Rangel (Code Review) 07 Dec '20

07 Dec '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28101 ) Change subject: Makefile: Add $(xcompile) to specify where to write xcompile ...................................................................... Patch Set 11: PTAL -- To view, visit https://review.coreboot.org/c/coreboot/+/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)google.com> Gerrit-Comment-Date: Mon, 07 Dec 2020 16:11:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake: Introduce memmap.h
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45379 ) Change subject: nb/intel/ironlake: Introduce memmap.h ...................................................................... nb/intel/ironlake: Introduce memmap.h Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I1f37ad9cae39041f98871c613b308b5ac5da01b3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h A src/northbridge/intel/ironlake/memmap.h 2 files changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/45379/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 9faa661..7198446a 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -25,10 +25,7 @@ #define IRONLAKE_DESKTOP 1 #define IRONLAKE_SERVER 2 -/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#include "memmap.h" #define QUICKPATH_BUS 0xff diff --git a/src/northbridge/intel/ironlake/memmap.h b/src/northbridge/intel/ironlake/memmap.h new file mode 100644 index 0000000..882a867 --- /dev/null +++ b/src/northbridge/intel/ironlake/memmap.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__ + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f37ad9cae39041f98871c613b308b5ac5da01b3 Gerrit-Change-Number: 45379 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45378 ) Change subject: nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR} ...................................................................... nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR} This allows dropping some casts. Changes the binary, though. Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h 2 files changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45378/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index fa89bd9..e0120fe 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -19,9 +19,9 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index aa9a8b7..9faa661 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -26,13 +26,8 @@ #define IRONLAKE_SERVER 2 /* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define QUICKPATH_BUS 0xff -- To view, visit https://review.coreboot.org/c/coreboot/+/45378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2 Gerrit-Change-Number: 45378 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Unified the type of _start, _end in ARM64 mmu.h
by Meng-Huan Yu (Code Review) 07 Dec '20

07 Dec '20

Meng-Huan Yu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48259 ) Change subject: libpayload: Unified the type of _start, _end in ARM64 mmu.h ...................................................................... libpayload: Unified the type of _start, _end in ARM64 mmu.h The type of _start and _end symbols in depthcharge is "uint8_t", it will cause compile error if trying to includes arm64/arch/mmu.h from depthcharge. BUG=b:171858277 TEST=Built on arm64 board emerge-asurada libpayload depthcharge Signed-off-by: Meng-Huan Yu <menghuan(a)google.com> Change-Id: I5756f63f5cae22ecda6873c711bef16aeabc89f6 --- M payloads/libpayload/include/arm64/arch/mmu.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48259/1 diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h index 9ead5d6..1126e76 100644 --- a/payloads/libpayload/include/arm64/arch/mmu.h +++ b/payloads/libpayload/include/arm64/arch/mmu.h @@ -46,7 +46,7 @@ * Symbols taken from linker script * They mark the start and end of the region used by payload */ -extern char _start[], _end[]; +extern uint8_t _start, _end; /* Memory attributes for mmap regions * These attributes act as tag values for memrange regions -- To view, visit https://review.coreboot.org/c/coreboot/+/48259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5756f63f5cae22ecda6873c711bef16aeabc89f6 Gerrit-Change-Number: 48259 Gerrit-PatchSet: 1 Gerrit-Owner: Meng-Huan Yu <menghuan(a)google.com> Gerrit-MessageType: newchange

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