coreboot-gerrit December 2020

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Change in coreboot[master]: mb/supermicro/x11ssm-f: (re)configure and document various pads
by Michael Niewöhner (Code Review) 07 Dec '20

07 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48098 ) Change subject: mb/supermicro/x11ssm-f: (re)configure and document various pads ...................................................................... Patch Set 14: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93 Gerrit-Change-Number: 48098 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 07 Dec 2020 11:53:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: common/block/cse: Rename cbfs_boot_load_file() to cbfs_load()
by V Sowmya (Code Review) 07 Dec '20

07 Dec '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48291 ) Change subject: common/block/cse: Rename cbfs_boot_load_file() to cbfs_load() ...................................................................... common/block/cse: Rename cbfs_boot_load_file() to cbfs_load() This patch renames the cbfs_boot_load_file() to cbfs_load() to avoid the build errors for cselite and align with the new changes to API https://review.coreboot.org/c/coreboot/+/39304 . Change-Id: I717f0a3291f781cc3cf60aae88e7479762ede9f9 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/48291/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9011593..eb4be6e 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -746,8 +746,8 @@ struct cse_rw_metadata source_metadata; /* Read CSE CBFS RW metadata */ - if (cbfs_boot_load_file(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, &source_metadata, - sizeof(source_metadata), CBFS_TYPE_RAW) != sizeof(source_metadata)) { + if (cbfs_load(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, &source_metadata, + sizeof(source_metadata)) != sizeof(source_metadata)) { printk(BIOS_ERR, "cse_lite: Failed to get CSE CBFS RW metadata\n"); return CSE_LITE_SKU_RW_METADATA_NOT_FOUND; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I717f0a3291f781cc3cf60aae88e7479762ede9f9 Gerrit-Change-Number: 48291 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] plot I/O and roundtrip latency errors
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48399 ) Change subject: [WIP] plot I/O and roundtrip latency errors ...................................................................... [WIP] plot I/O and roundtrip latency errors Change-Id: I453e3fe51e4a577f9503350405d9fe4b668bd037 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/48399/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 667ec14..3df234a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1328,6 +1328,9 @@ program_timings(ctrl, channel); test_rcven(ctrl, channel, slotrank); + printram("C%dR%d:\t01234567%c\n\t", channel, slotrank, + ctrl->lanes == NUM_LANES ? '8' : ' '); + FOR_ALL_LANES { works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); @@ -1335,8 +1338,12 @@ some_works = 1; else all_works = 0; + + printram("%c", works[lane] ? '.' : '#'); } + printram("\n"); + /* If every lane is working, exit */ if (all_works) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/48399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I453e3fe51e4a577f9503350405d9fe4b668bd037 Gerrit-Change-Number: 48399 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] plot 2D write margins
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48398 ) Change subject: [WIP] plot 2D write margins ...................................................................... [WIP] plot 2D write margins Looks like they don't work as intended Change-Id: Id76e7f292fdb3813a8dd973273b17279b74ac5c1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 48 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/48398/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3efabdb..667ec14 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2723,6 +2723,9 @@ int aggressive_write_training(ramctr_timing *ctrl) { const u8 wr_vref_offsets[3] = { 0, 0x0f, 0x2f }; + + const bool sweep_vref = 0 && CONFIG(RAMINIT_PLOT_READ_MARGINS); + int i, pat; int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2749,12 +2752,20 @@ printram("discover tx_dq write:\n"); - for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { - FOR_ALL_POPULATED_CHANNELS { - set_write_vref(channel, wr_vref_offsets[i]); + const int max_vref_idx = sweep_vref ? 63 : ARRAY_SIZE(wr_vref_offsets); - for (pat = 0; pat < NUM_PATTERNS; pat++) { - FOR_ALL_POPULATED_RANKS { + FOR_ALL_POPULATED_CHANNELS { + FOR_ALL_POPULATED_RANKS { + printram("channel %d, rank %d\n", channel, slotrank); + + for (i = 0; i < max_vref_idx; i++) { + const int vref = i >= 32 ? i : 31 - i; + set_write_vref(channel, sweep_vref ? vref : wr_vref_offsets[i]); + + if (sweep_vref) + printram("% 5d:\t", 31 - i); + + for (pat = 0; pat < NUM_PATTERNS; pat++) { int tx_dq; u32 raw_stats[MAX_TX_DQ + 1]; int stats[MAX_TX_DQ + 1]; @@ -2771,10 +2782,24 @@ } program_timings(ctrl, channel); + MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); + test_aggressive_write(ctrl, channel, slotrank); raw_stats[tx_dq] = MCHBAR32( IOSAV_BYTE_SERROR_C_ch(channel)); + + if (!sweep_vref) + continue; + + printram("%02x ", raw_stats[tx_dq] & 0xff); + +#if 0 + if (i == 31 && tx_dq == (MAX_TX_DQ + 1) / 2) + printram("%c", raw_stats[tx_dq] & 0xff ? 'X' : '+'); + else + printram("%c", raw_stats[tx_dq] & 0xff ? '#' : '.'); +#endif } FOR_ALL_LANES { struct run rn; @@ -2792,12 +2817,6 @@ return MAKE_ERR; } - printram("tx_dq: %d, %d, %d: " - "0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, - i, rn.start, rn.middle, rn.end, - rn.start + ctrl->tx_dq_offset[i], - rn.end - ctrl->tx_dq_offset[i]); lower[channel][slotrank][lane] = MAX(rn.start + ctrl->tx_dq_offset[i], @@ -2807,9 +2826,27 @@ MIN(rn.end - ctrl->tx_dq_offset[i], upper[channel][slotrank][lane]); + if (sweep_vref) + continue; + + printram("tx_dq: %d, %d, %d: " + "0x%02x-0x%02x-0x%02x, " + "0x%02x-0x%02x\n", channel, slotrank, + i, rn.start, rn.middle, rn.end, + rn.start + ctrl->tx_dq_offset[i], + rn.end - ctrl->tx_dq_offset[i]); } + + if (sweep_vref) + printram(" "); } + + if (sweep_vref) + printram("\n"); } + + if (sweep_vref) + printram("\n"); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id76e7f292fdb3813a8dd973273b17279b74ac5c1 Gerrit-Change-Number: 48398 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch
by Johnny Lin (Code Review) 07 Dec '20

07 Dec '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48228 ) Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch ...................................................................... vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch Tested=On OCP Delta Lake, verify the memory map hob data are correct. Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48228/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 53b7305..598d78c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -159,7 +159,7 @@ UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved5[2216]; + UINT8 reserved5[2249]; MEMMAP_SOCKET Socket[MAX_SOCKET]; UINT8 reserved6[1603]; -- To view, visit https://review.coreboot.org/c/coreboot/+/48228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716 Gerrit-Change-Number: 48228 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/microcode: Mark assemblycode as 32bit
by Patrick Rudolph (Code Review) 07 Dec '20

07 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48164 ) Change subject: cpu/intel/microcode: Mark assemblycode as 32bit ...................................................................... cpu/intel/microcode: Mark assemblycode as 32bit Allows to compile the file under x86_64 without errors. The caller has to make sure to call the functions while in protected mode, which is usually the case in early bootblock. Change-Id: Ic6d98febb357226183c293c11ba7961f27fac40c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/microcode/microcode_asm.S 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48164/1 diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a..5173ae5 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -43,6 +43,7 @@ * if the revision of the update is newer than what is installed */ +.code32 .section .text .global update_bsp_microcode -- To view, visit https://review.coreboot.org/c/coreboot/+/48164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d98febb357226183c293c11ba7961f27fac40c Gerrit-Change-Number: 48164 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/early_reset: Mark assemblycode as 32bit
by Patrick Rudolph (Code Review) 07 Dec '20

07 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48165 ) Change subject: cpu/x86/early_reset: Mark assemblycode as 32bit ...................................................................... cpu/x86/early_reset: Mark assemblycode as 32bit Allows to compile the file under x86_64 without errors. The caller has to make sure to call the functions while in protected mode, which is usually the case in early bootblock. Change-Id: Ic6601e2af57e0acc6474fc3a4297e3d2281decd6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/early_reset.S 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48165/1 diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 6ce9d52..07e63f4 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -7,6 +7,7 @@ #include <cpu/x86/mtrr.h> +.code32 .section .text .global check_mtrr -- To view, visit https://review.coreboot.org/c/coreboot/+/48165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6601e2af57e0acc6474fc3a4297e3d2281decd6 Gerrit-Change-Number: 48165 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/solidrun/solidpc: Do initial commit
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Patch Set 12: > Patch Set 12: > > Any updates on this? There's pending comments -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 07 Dec 2020 09:59:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/device: Remove unused TBT IDs for TGL and ADL
by Subrata Banik (Code Review) 07 Dec '20

07 Dec '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48394 ) Change subject: include/device: Remove unused TBT IDs for TGL and ADL ...................................................................... Patch Set 1: > Patch Set 1: > > I would keep the IDs if they are correct, in case they are needed later. Got it, make sense to me as well -- To view, visit https://review.coreboot.org/c/coreboot/+/48394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9ca39070ccb4d6abc18aa8c39b2660f313663f1 Gerrit-Change-Number: 48394 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Dec 2020 09:38:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/device: Remove unused TBT IDs for TGL and ADL
by Angel Pons (Code Review) 07 Dec '20

07 Dec '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48394 ) Change subject: include/device: Remove unused TBT IDs for TGL and ADL ...................................................................... Patch Set 1: I would keep the IDs if they are correct, in case they are needed later. -- To view, visit https://review.coreboot.org/c/coreboot/+/48394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9ca39070ccb4d6abc18aa8c39b2660f313663f1 Gerrit-Change-Number: 48394 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Dec 2020 09:33:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2020