coreboot-gerrit December 2020

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Change in coreboot[master]: soc/amd/picasso/Makefile: use all-y for adding config.c to the build
by Felix Held (Code Review) 06 Dec '20

06 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48313 ) Change subject: soc/amd/picasso/Makefile: use all-y for adding config.c to the build ...................................................................... soc/amd/picasso/Makefile: use all-y for adding config.c to the build Since config.c also gets linked into verstage on PSP and not only into the stages running on the x86 cores, use all-y instead of adding config.c to all classes separately. Change-Id: Icacb13e73e80e6f3d8c2141784702fb895daf7db Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/48313/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d86d97e..d48dffd 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -10,6 +10,8 @@ subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage +all-y += config.c + bootblock-y += bootblock.c bootblock-y += aoac.c bootblock-y += southbridge.c @@ -17,7 +19,6 @@ bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c bootblock-y += gpio.c -bootblock-y += config.c bootblock-y += reset.c romstage-y += i2c.c @@ -30,11 +31,9 @@ romstage-y += aoac.c romstage-y += southbridge.c romstage-y += psp.c -romstage-y += config.c romstage-y += mrc_cache.c verstage-y += i2c.c -verstage-y += config.c verstage-y += aoac.c verstage_x86-y += gpio.c verstage_x86-y += uart.c @@ -63,7 +62,6 @@ ramstage-y += soc_util.c ramstage-y += psp.c ramstage-y += fsp_params.c -ramstage-y += config.c ramstage-y += update_microcode.c ramstage-y += graphics.c ramstage-y += pcie_gpp.c @@ -78,7 +76,6 @@ smm-y += gpio.c smm-y += psp.c smm-y += smu.c -smm-y += config.c CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include -- To view, visit https://review.coreboot.org/c/coreboot/+/48313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icacb13e73e80e6f3d8c2141784702fb895daf7db Gerrit-Change-Number: 48313 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: use common TSC and monotonic timer code
by Felix Held (Code Review) 06 Dec '20

06 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48306 ) Change subject: soc/amd/cezanne: use common TSC and monotonic timer code ...................................................................... soc/amd/cezanne: use common TSC and monotonic timer code Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc D src/soc/amd/cezanne/timer.c 3 files changed, 1 insertion(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48306/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6900ad7..914384b 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -17,8 +17,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF - select NO_MONOTONIC_TIMER # TODO: replace - select UNKNOWN_TSC_RATE # TODO: replace + select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H config EARLY_RESERVED_DRAM_BASE hex diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index d1d8e97..d4f585f 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -7,7 +7,6 @@ romstage-y += romstage.c ramstage-y += chip.c -ramstage-y += timer.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include diff --git a/src/soc/amd/cezanne/timer.c b/src/soc/amd/cezanne/timer.c deleted file mode 100644 index 9054ffd..0000000 --- a/src/soc/amd/cezanne/timer.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <delay.h> - -void init_timer(void) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c Gerrit-Change-Number: 48306 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: factor out common family 17h&19h TSC and monotonic timer code
by Felix Held (Code Review) 06 Dec '20

06 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48305 ) Change subject: soc/amd: factor out common family 17h&19h TSC and monotonic timer code ...................................................................... soc/amd: factor out common family 17h&19h TSC and monotonic timer code The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the code. Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/tsc/Kconfig A src/soc/amd/common/block/tsc/Makefile.inc R src/soc/amd/common/block/tsc/monotonic_timer.c R src/soc/amd/common/block/tsc/tsc_freq.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 6 files changed, 31 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/48305/1 diff --git a/src/soc/amd/common/block/tsc/Kconfig b/src/soc/amd/common/block/tsc/Kconfig new file mode 100644 index 0000000..49f2589 --- /dev/null +++ b/src/soc/amd/common/block/tsc/Kconfig @@ -0,0 +1,10 @@ +config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H + bool + select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function + select TSC_SYNC_LFENCE + select UDELAY_TSC + default n + help + Select this option to add the common functions for getting the TSC + frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC- + based monotonic timer functionality to the build. diff --git a/src/soc/amd/common/block/tsc/Makefile.inc b/src/soc/amd/common/block/tsc/Makefile.inc new file mode 100644 index 0000000..75c6061 --- /dev/null +++ b/src/soc/amd/common/block/tsc/Makefile.inc @@ -0,0 +1,20 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H),y) + +subdirs-y += ../../../../../cpu/x86/tsc + +bootblock-y += tsc_freq.c +bootblock-y += monotonic_timer.c + +verstage_x86-y += tsc_freq.c +verstage_x86-y += monotonic_timer.c + +romstage-y += tsc_freq.c +romstage-y += monotonic_timer.c + +ramstage-y += tsc_freq.c +ramstage-y += monotonic_timer.c + +smm-y += tsc_freq.c +smm-y += monotonic_timer.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H diff --git a/src/soc/amd/picasso/monotonic_timer.c b/src/soc/amd/common/block/tsc/monotonic_timer.c similarity index 100% rename from src/soc/amd/picasso/monotonic_timer.c rename to src/soc/amd/common/block/tsc/monotonic_timer.c diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/common/block/tsc/tsc_freq.c similarity index 100% rename from src/soc/amd/picasso/tsc_freq.c rename to src/soc/amd/common/block/tsc/tsc_freq.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2ac1235..79fc3be 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -24,10 +24,7 @@ select IOAPIC select HAVE_EM100_SUPPORT select HAVE_USBDEBUG_OPTIONS - select COLLECT_TIMESTAMPS_NO_TSC select SOC_AMD_COMMON_BLOCK_SPI - select TSC_SYNC_LFENCE - select UDELAY_TSC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI @@ -44,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMU + select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index c772783..d86d97e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/amd/mtrr/ -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr @@ -17,8 +16,6 @@ bootblock-y += i2c.c bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -bootblock-y += monotonic_timer.c -bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += config.c bootblock-y += reset.c @@ -30,8 +27,6 @@ romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -romstage-y += monotonic_timer.c -romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c romstage-y += psp.c @@ -44,8 +39,6 @@ verstage_x86-y += gpio.c verstage_x86-y += uart.c verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -verstage_x86-y += monotonic_timer.c -verstage_x86-y += tsc_freq.c verstage_x86-y += reset.c ramstage-y += i2c.c @@ -66,8 +59,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -ramstage-y += monotonic_timer.c -ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c @@ -80,8 +71,6 @@ ramstage-y += dmi.c smm-y += smihandler.c -smm-y += monotonic_timer.c -smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-y += uart.c smm-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -- To view, visit https://review.coreboot.org/c/coreboot/+/48305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64 Gerrit-Change-Number: 48305 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/cpu: move Makefile guards into subfolders
by Felix Held (Code Review) 06 Dec '20

06 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48312 ) Change subject: soc/amd/common/block/cpu: move Makefile guards into subfolders ...................................................................... soc/amd/common/block/cpu: move Makefile guards into subfolders The next patch will add a tsc subfolder that might end up containing code that is guarded with different Kconfig options, so move the guards into the Makefiles in the subfolders instead of guarding the inclusion of the Makefiles in the subdirectories with the corresponding Kconfig option. Change-Id: Iafc867eb9adcb23e9a4878cc381684db6f9692d5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/Makefile.inc M src/soc/amd/common/block/cpu/car/Makefile.inc M src/soc/amd/common/block/cpu/noncar/Makefile.inc 3 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/48312/1 diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index 6298f3b..4c02663 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1,2 +1 @@ -subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car -subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR) += noncar +subdirs-y += ./* diff --git a/src/soc/amd/common/block/cpu/car/Makefile.inc b/src/soc/amd/common/block/cpu/car/Makefile.inc index 6399140..130b34b 100644 --- a/src/soc/amd/common/block/cpu/car/Makefile.inc +++ b/src/soc/amd/common/block/cpu/car/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_CAR),y) + bootblock-y += cache_as_ram.S bootblock-y += ap_exit_car.S bootblock-y += exit_car.S @@ -6,3 +8,5 @@ romstage-y += ap_exit_car.S romstage-y += exit_car.S + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_CAR diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index d6b8b52..7a3be34 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) + bootblock-y += pre_c.S + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR -- To view, visit https://review.coreboot.org/c/coreboot/+/48312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafc867eb9adcb23e9a4878cc381684db6f9692d5 Gerrit-Change-Number: 48312 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Angel Pons (Code Review) 06 Dec '20

06 Dec '20

Angel Pons has restored this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: restore

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Change in coreboot[master]: util: Remove 'getpir' and 'mptable' tools
by Mike Banon (Code Review) 06 Dec '20

06 Dec '20

Mike Banon has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/5158 ) Change subject: util: Remove 'getpir' and 'mptable' tools ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/5158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49d7c5c86b908e08a3d79a06f5cb5b28cea1c806 Gerrit-Change-Number: 5158 Gerrit-PatchSet: 2 Gerrit-Owner: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

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Change in coreboot[master]: drivers/ipmi: add code to set BMC/IPMI enablement from jumper
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48094 to look at the new patch set (#14). Change subject: drivers/ipmi: add code to set BMC/IPMI enablement from jumper ...................................................................... drivers/ipmi: add code to set BMC/IPMI enablement from jumper Some boards, like the Supermicro X11SSM-F, have a jumper for enabling or disabling the BMC and IPMI. Add a new devicetree driver option to set the GPIO used for the jumper and enable or disable IPMI according to its value. This gets used in the follow-up change by Supermicro X11SSM-F. Test: Boot with jumper set to each enabled and disabled and see if IPMI gets enabled. Successfully tested on Supermicro X11SSM-F. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Icde3232843a7138797a4b106560f170972edeb9c --- M src/drivers/ipmi/chip.h M src/drivers/ipmi/ipmi_kcs_ops.c 2 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48094/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/48094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde3232843a7138797a4b106560f170972edeb9c Gerrit-Change-Number: 48094 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48366 to look at the new patch set (#3). Change subject: mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME ...................................................................... mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME All X11 boards currently supported have Intel SPS without support for S3/S5. Thus, drop it from Kconfig. Note: not all X11 boards are server boards. When a X11 desktop or workstation board should be added, this can be selected by the boards, where S3/S5 work. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 --- M src/mainboard/supermicro/x11-lga1151-series/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48366/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 Gerrit-Change-Number: 48366 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/chili: Remove unnecessary device declarations
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48374 ) Change subject: mb/siemens/chili: Remove unnecessary device declarations ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620 Gerrit-Change-Number: 48374 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Dec 2020 13:10:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Remove unnecessary device declarations
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48373 ) Change subject: mb/clevo/l140cu: Remove unnecessary device declarations ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef Gerrit-Change-Number: 48373 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Dec 2020 13:09:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020