coreboot-gerrit December 2020

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Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Patrick Rudolph (Code Review) 06 Dec '20

06 Dec '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Patch Set 4: Code-Review-1 (1 comment) > Patch Set 4: > > > I don't understand why this is necessary at all. Looks like you found a bug in sconfig you are trying to work around. > > I don't know if it is a bug actually or if this is just not meant to be. When we started adding the chipset devicetrees for soc/skylake and soc/cannonlake, we encountered that problem on cannonlake. > > If the PCI device on mb/hermes is wrapped by the UART driver and if also the patch for the chipset devicetree is applied, then the PCI device has two declarations in static.c. > > DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_19_2 = &_dev32; > ... > DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_19_2 = &_dev70; > > There was a similar problem with drivers/wifi/generic (CB:46865) as Michael mentioned. Furquan solved that by turning it around. So he moved the driver into the device. Here in this case, only the declaration for &_dev32 (from the example above) is left then, while &_dev72 is declared as a sub device. This is a bug in sconfig as it's clearly the same PCI device (same dev function number, same parent). https://review.coreboot.org/c/coreboot/+/48293/4/src/mainboard/prodrive/her… File src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb: https://review.coreboot.org/c/coreboot/+/48293/4/src/mainboard/prodrive/her… PS4, Line 177: device pci 19.2 on end > 19.2->19.2 won't work; `device generic 0 on end` would be correct, see CB:46865 for example. […] The device must be hidden and as it's not the 19.2 pci device the driver will not work. -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Dec 2020 09:01:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/chili: Remove unnecessary device declarations
by Felix Singer (Code Review) 06 Dec '20

06 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48374 ) Change subject: mb/siemens/chili: Remove unnecessary device declarations ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620 Gerrit-Change-Number: 48374 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Dec 2020 08:44:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Remove unnecessary device declarations
by Felix Singer (Code Review) 06 Dec '20

06 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48373 ) Change subject: mb/clevo/l140cu: Remove unnecessary device declarations ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef Gerrit-Change-Number: 48373 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Dec 2020 08:44:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Use proper indents
by Felix Singer (Code Review) 06 Dec '20

06 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48372 ) Change subject: mb/clevo/l140cu: Use proper indents ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150 Gerrit-Change-Number: 48372 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Dec 2020 08:44:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden
by Felix Singer (Code Review) 06 Dec '20

06 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48371 ) Change subject: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Gerrit-Change-Number: 48371 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Dec 2020 08:44:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] move chip_ops to comm/block/gpio
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48343 ) Change subject: [RFC] move chip_ops to comm/block/gpio ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2ad643f27f0183d6466aec716be8b5d4a289aa6 Gerrit-Change-Number: 48343 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Dec 2020 00:41:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|WIP] current state of making ipmi gpio generic
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48107 ) Change subject: [RFC|WIP] current state of making ipmi gpio generic ...................................................................... Patch Set 8: Updated (moved gpio ops to chip_ops). CB:48343 shows a slight modification that would save us from having to add the same gpio_ops for each soc, because they all use soc/intel/common/block/gpio. Comments and ideas welcome! -- To view, visit https://review.coreboot.org/c/coreboot/+/48107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f604c5a5d82c94e56399e2c37bfeb54927d34f Gerrit-Change-Number: 48107 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Dec 2020 00:40:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Felix Singer (Code Review) 05 Dec '20

05 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Patch Set 4: > I don't understand why this is necessary at all. Looks like you found a bug in sconfig you are trying to work around. I don't know if it is a bug actually or if this is just not meant to be. When we started adding the chipset devicetrees for soc/skylake and soc/cannonlake, we encountered that problem on cannonlake. If the PCI device on mb/hermes is wrapped by the UART driver and if also the patch for the chipset devicetree is applied, then the PCI device has two declarations in static.c. DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_19_2 = &_dev32; ... DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_19_2 = &_dev70; There was a similar problem with drivers/wifi/generic (CB:46865) as Michael mentioned. Furquan solved that by turning it around. So he moved the driver into the device. Here in this case, only the declaration for &_dev32 (from the example above) is left then, while &_dev72 is declared as a sub device. -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Dec 2020 21:44:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: order selected Kconfig options alphabetically
by Felix Held (Code Review) 05 Dec '20

05 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48308 ) Change subject: soc/amd/stoneyridge: order selected Kconfig options alphabetically ...................................................................... soc/amd/stoneyridge: order selected Kconfig options alphabetically TEST=Timeless build doesn't change for amd/gardenia. Change-Id: I5f1873111c07f6dc823b06654e463830d83acc9e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/Kconfig 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/48308/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index d672726..c1989e2 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -9,42 +9,42 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 - select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES + select ACPI_NO_SMI_GNVS + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY - select IOAPIC select HAVE_CF9_RESET + select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS - select SOC_AMD_COMMON_BLOCK_SPI - select TSC_SYNC_LFENCE - select SOC_AMD_PI - select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_IOMMU - select SOC_AMD_COMMON_BLOCK_ACPIMMIO - select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS - select SOC_AMD_COMMON_BLOCK_ACPI - select SOC_AMD_COMMON_BLOCK_AOAC - select SOC_AMD_COMMON_BLOCK_LPC - select SOC_AMD_COMMON_BLOCK_PCI - select SOC_AMD_COMMON_BLOCK_HDA - select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_PSP_GEN1 - select SOC_AMD_COMMON_BLOCK_CAR - select SOC_AMD_COMMON_BLOCK_S3 - select SOC_AMD_COMMON_BLOCK_SMBUS - select SOC_AMD_COMMON_BLOCK_SMI - select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select IOAPIC select PARALLEL_MP select PARALLEL_MP_AP_WORK - select HAVE_SMI_HANDLER - select SSE2 select RTC - select ACPI_NO_SMI_GNVS + select SOC_AMD_PI + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_CAR + select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_IOMMU + select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PI + select SOC_AMD_COMMON_BLOCK_PSP_GEN1 + select SOC_AMD_COMMON_BLOCK_S3 + select SOC_AMD_COMMON_BLOCK_SATA + select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SPI + select SSE2 + select TSC_SYNC_LFENCE + select X86_AMD_FIXED_MTRRS config AMD_APU_STONEYRIDGE bool -- To view, visit https://review.coreboot.org/c/coreboot/+/48308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f1873111c07f6dc823b06654e463830d83acc9e Gerrit-Change-Number: 48308 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Fix X86_RESET_VECTOR location in comments
by Kyösti Mälkki (Code Review) 05 Dec '20

05 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48307 ) Change subject: soc/amd: Fix X86_RESET_VECTOR location in comments ...................................................................... soc/amd: Fix X86_RESET_VECTOR location in comments Change-Id: I3e4b3cbed8abe3988d9f48c13d01400af75a4776 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/root_complex.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/48307/1 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index bf101e3..e6de812 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -29,10 +29,10 @@ * | FSP-M | * | (FSP_M_SIZE) | * +--------------------------------+ FSP_M_ADDR - * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10 * | romstage | * | (ROMSTAGE_SIZE) | * +--------------------------------+ ROMSTAGE_ADDR + * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | * +--------------------------------+ BOOTBLOCK_ADDR diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 72a0974..90d2d4e 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -75,10 +75,10 @@ * | FSP-M | * | (FSP_M_SIZE) | * +--------------------------------+ FSP_M_ADDR - * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10 * | romstage | * | (ROMSTAGE_SIZE) | * +--------------------------------+ ROMSTAGE_ADDR + * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | * +--------------------------------+ BOOTBLOCK_ADDR -- To view, visit https://review.coreboot.org/c/coreboot/+/48307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e4b3cbed8abe3988d9f48c13d01400af75a4776 Gerrit-Change-Number: 48307 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020