coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/volteer/var/voema: Add MIPI camera support
by David Wu (Code Review) 05 Dec '20

05 Dec '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47668 ) Change subject: mb/google/volteer/var/voema: Add MIPI camera support ...................................................................... mb/google/volteer/var/voema: Add MIPI camera support 1. Adds VARIANT_HAS_MIPI_CAMERA to Kconfig.name 2. Adds mipi_camera.asl BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9 --- M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47668/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index b651430..53f1e83 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -86,4 +86,5 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000..418f2e0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/acpi/mipi_camera.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/47668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9 Gerrit-Change-Number: 47668 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff/var/dooly: Update DPTF parameters
by Tony Huang (Code Review) 05 Dec '20

05 Dec '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48206 ) Change subject: mb/google/puff/var/dooly: Update DPTF parameters ...................................................................... mb/google/puff/var/dooly: Update DPTF parameters DPTF paramerters form thermal team. Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W. BUG=b:174514010 BRANCH=puff TEST=build image and verified by thermal team. Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 23 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48206/1 diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index efa7d71..45c43cc 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/cannonlake + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 49, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -176,47 +181,36 @@ chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(90, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(75, 60), + TEMP_PCT(65, 50), + TEMP_PCT(45, 40), + TEMP_PCT(30, 30),}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 70, 60000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 76, 60000)" ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 15-25W PL1 in 1000mW increments, avg over 28-32s interval + # 40-49W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .max_power = 25000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" + register "controls.power_limits.pl2" = "{ + .min_power = 40000, + .max_power = 49000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/48206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955 Gerrit-Change-Number: 48206 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/zork: set APU_EDP_BL_DISABLE to low as default
by chris wang (Code Review) 05 Dec '20

05 Dec '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48203 to review the following change. Change subject: mb/zork: set APU_EDP_BL_DISABLE to low as default ...................................................................... mb/zork: set APU_EDP_BL_DISABLE to low as default set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than APU_DP_BLON. BUG=b:171954512 BRANCH=zork TEST=validate the panel sequence with scope. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48203/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 884862d..e928d8c 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -95,8 +95,8 @@ /* GPIO_77 - GPIO_83: Not available */ /* HP_INT_ODL */ PAD_GPI(GPIO_84, PULL_NONE), - /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ - PAD_GPO(GPIO_85, HIGH), + /* APU_EDP_BL_DISABLE */ + PAD_GPO(GPIO_85, LOW), /* RAM ID 2 - Keep High */ PAD_GPO(GPIO_86, HIGH), /* EMMC_DATA7 */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 818c39b..bb99f5d 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -99,8 +99,8 @@ /* GPIO_77 - GPIO_83: Not available */ /* RAM_ID_4 */ PAD_GPI(GPIO_84, PULL_NONE), - /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ - PAD_GPO(GPIO_85, HIGH), + /* APU_EDP_BL_DISABLE */ + PAD_GPO(GPIO_85, LOW), /* WIFI_AUX_RESET_L */ PAD_GPO(GPIO_86, HIGH), /* EMMC_DATA7 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad Gerrit-Change-Number: 48203 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Create copano variant
by Patrick Georgi (Code Review) 05 Dec '20

05 Dec '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48136 ) Change subject: mb/google/volteer: Create copano variant ...................................................................... mb/google/volteer: Create copano variant Create the copano variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:174413884 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COPANO Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/copano/include/variant/ec.h A src/mainboard/google/volteer/variants/copano/include/variant/gpio.h A src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/copano/overridetree.cb 6 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index f2e4adc..c776ba1 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -107,6 +107,7 @@ default "Elemi" if BOARD_GOOGLE_ELEMI default "Voema" if BOARD_GOOGLE_VOEMA default "Drobit" if BOARD_GOOGLE_DROBIT + default "Copano" if BOARD_GOOGLE_COPANO config MAX_CPUS int @@ -148,6 +149,7 @@ default "elemi" if BOARD_GOOGLE_ELEMI default "voema" if BOARD_GOOGLE_VOEMA default "drobit" if BOARD_GOOGLE_DROBIT + default "copano" if BOARD_GOOGLE_COPANO config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 7536dc5..676054c 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -93,3 +93,7 @@ config BOARD_GOOGLE_DROBIT bool "-> Drobit" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_COPANO + bool "-> Copano" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/copano/include/variant/ec.h b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h b/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt new file mode 100644 index 0000000..f51b3af --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/48136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef Gerrit-Change-Number: 48136 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: Wrap calls into FSP
by Patrick Rudolph (Code Review) 05 Dec '20

05 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48202 ) Change subject: drivers/intel/fsp2_0/memory_init: Wrap calls into FSP ...................................................................... drivers/intel/fsp2_0/memory_init: Wrap calls into FSP Use a wrapper code that does nothing on x86_32, but drops to protected mode to call into FSP when running on x86_64. Tested on Intel Skylake when running in long mode. Successfully run the FSP-M which is compiled for x86_32 and then continued booting in long mode. Change-Id: I9fb37019fb0d04f74d00733ce2e365f484d97d66 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/48202/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 27e34fe..00927ac 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -22,6 +22,7 @@ #include <security/tpm/tspi.h> #include <vb2_api.h> #include <types.h> +#include <mode_switch.h> static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); @@ -296,7 +297,7 @@ post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); - status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); + status = protected_mode_call_2arg(fsp_raminit, (uintptr_t)&fspm_upd, (uintptr_t)fsp_get_hob_list_ptr()); post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0b6540e..fc5b41b 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -13,6 +13,7 @@ #include <string.h> #include <timestamp.h> #include <types.h> +#include <mode_switch.h> struct fsp_header fsps_hdr; @@ -117,7 +118,11 @@ timestamp_add_now(TS_FSP_SILICON_INIT_START); post_code(POST_FSP_SILICON_INIT); - status = silicon_init(upd); + + status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd); + + printk(BIOS_ERR, "FSPS returned %x\n", status); + timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); -- To view, visit https://review.coreboot.org/c/coreboot/+/48202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fb37019fb0d04f74d00733ce2e365f484d97d66 Gerrit-Change-Number: 48202 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]cpu/x86/64bit: Add code to call FSP in protected mode
by Patrick Rudolph (Code Review) 05 Dec '20

05 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48175 ) Change subject: [WIP]cpu/x86/64bit: Add code to call FSP in protected mode ...................................................................... [WIP]cpu/x86/64bit: Add code to call FSP in protected mode Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/cpu/x86/64bit/helper.S M src/cpu/x86/Makefile.inc M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/48175/1 diff --git a/src/cpu/x86/64bit/helper.S b/src/cpu/x86/64bit/helper.S new file mode 100644 index 0000000..dd8f1b5 --- /dev/null +++ b/src/cpu/x86/64bit/helper.S @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifdef ENV_X86_64 +.text +.code64 + .section ".text.protected_mode_call", "ax", @progbits + .globl protected_mode_call_2arg +protected_mode_call_2arg: + + push %rbp + mov %rsp, %rbp + /* Preserve registers */ + push %rbx + push %r12 + push %r13 + push %r14 + push %r15 + + /* Arguments to stack */ + push %rdi + push %rsi + push %rdx + push %rcx + + #include <cpu/x86/64bit/exit32.inc> + + movl -48(%ebp), %eax /* Argument count */ + movl -64(%ebp), %edx /* Argument 0 */ + movl -72(%ebp), %ecx /* Argument 1 */ + + /* Align the stack */ + andl $0xFFFFFFF0, %esp + test %eax, %eax + je 1f /* Zero arguments */ + + subl $1, %eax + test %eax, %eax + je 2f /* One argument */ + + /* Two arguments */ + subl $8, %esp + pushl %ecx /* Argument 1 */ + pushl %edx /* Argument 0 */ + jmp 1f +2: + subl $12, %esp + pushl %edx /* Argument 0 */ + +1: + movl -56(%ebp), %ebx /* Function to call */ + call *%ebx + movl %eax, %ebx + + /* Preserves ebx */ + #include <cpu/x86/64bit/entry64.inc> + + /* Place return value in rax */ + movl %ebx, %eax + + /* Restore registers */ + mov -40(%rbp), %r15 + mov -32(%rbp), %r14 + mov -24(%rbp), %r13 + mov -16(%rbp), %r12 + mov -8(%rbp), %rbx + + /* Restore stack pointer */ + mov %rbp, %rsp + pop %rbp + + ret +#endif diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7..6d0c4ac 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,6 @@ subdirs-y += pae +all-y += 64bit/helper.S + subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d62888e..0f6c701 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -223,6 +223,8 @@ struct memranges memmap; }; +int protected_mode_call_2arg(size_t arg_count, uint64_t func, uint64_t arg1, uint64_t arg2); + static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { uint32_t status; @@ -296,7 +298,11 @@ post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); +#if ENV_X86_64 + status = protected_mode_call_2arg(2, (uintptr_t)fsp_raminit, (uintptr_t)&fspm_upd, (uintptr_t)fsp_get_hob_list_ptr()); +#else status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); +#endif post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); -- To view, visit https://review.coreboot.org/c/coreboot/+/48175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6 Gerrit-Change-Number: 48175 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: mb/google/volteer/variant/lindar: Correct SD crad reader power sequen...
by Kevin Chang (Code Review) 05 Dec '20

05 Dec '20

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47799 ) Change subject: mb/google/volteer/variant/lindar: Correct SD crad reader power sequence for lindar ...................................................................... mb/google/volteer/variant/lindar: Correct SD crad reader power sequence for lindar Modify SD card reader 3.3V power enable timing, add GPIO pin(GPP_D16) in GPIO early table.. BUG=b:173676531 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f --- M src/mainboard/google/volteer/variants/lindar/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47799/1 diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c index 4f3d5f7..08f1401 100644 --- a/src/mainboard/google/volteer/variants/lindar/gpio.c +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -134,6 +134,9 @@ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f Gerrit-Change-Number: 47799 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: drivers/i2c/sx9324: Add more registers and reorder
by EricR Lai (Code Review) 05 Dec '20

05 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47866 ) Change subject: drivers/i2c/sx9324: Add more registers and reorder ...................................................................... drivers/i2c/sx9324: Add more registers and reorder Export all registers that driver is looking for. And put in alphabet order. The missing registers are: reg_irq_msk reg_irq_cfg0 reg_irq_cfg2 reg_afe_ph0/1/2/3 BUG=b:172397658 BRANCH=zork TEST=Build passed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac --- M src/drivers/i2c/sx9324/registers.h 1 file changed, 32 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47866/1 diff --git a/src/drivers/i2c/sx9324/registers.h b/src/drivers/i2c/sx9324/registers.h index 160e5e7..7d00261 100644 --- a/src/drivers/i2c/sx9324/registers.h +++ b/src/drivers/i2c/sx9324/registers.h @@ -4,29 +4,6 @@ #error "define REGISTER(NAME) before including this file" #endif -REGISTER(reg_gnrl_ctrl0); -REGISTER(reg_gnrl_ctrl1); - -REGISTER(reg_afe_ctrl0); -REGISTER(reg_afe_ctrl1); -REGISTER(reg_afe_ctrl2); -REGISTER(reg_afe_ctrl3); -REGISTER(reg_afe_ctrl4); -REGISTER(reg_afe_ctrl5); -REGISTER(reg_afe_ctrl6); -REGISTER(reg_afe_ctrl7); -REGISTER(reg_afe_ctrl8); -REGISTER(reg_afe_ctrl9); - -REGISTER(reg_prox_ctrl0); -REGISTER(reg_prox_ctrl1); -REGISTER(reg_prox_ctrl2); -REGISTER(reg_prox_ctrl3); -REGISTER(reg_prox_ctrl4); -REGISTER(reg_prox_ctrl5); -REGISTER(reg_prox_ctrl6); -REGISTER(reg_prox_ctrl7); - REGISTER(reg_adv_ctrl0); REGISTER(reg_adv_ctrl1); REGISTER(reg_adv_ctrl2); @@ -48,3 +25,35 @@ REGISTER(reg_adv_ctrl18); REGISTER(reg_adv_ctrl19); REGISTER(reg_adv_ctrl20); + +REGISTER(reg_afe_ctrl0); +REGISTER(reg_afe_ctrl1); +REGISTER(reg_afe_ctrl2); +REGISTER(reg_afe_ctrl3); +REGISTER(reg_afe_ctrl4); +REGISTER(reg_afe_ctrl5); +REGISTER(reg_afe_ctrl6); +REGISTER(reg_afe_ctrl7); +REGISTER(reg_afe_ctrl8); +REGISTER(reg_afe_ctrl9); + +REGISTER(reg_afe_ph0); +REGISTER(reg_afe_ph1); +REGISTER(reg_afe_ph2); +REGISTER(reg_afe_ph3); + +REGISTER(reg_gnrl_ctrl0); +REGISTER(reg_gnrl_ctrl1); + +REGISTER(reg_irq_msk); +REGISTER(reg_irq_cfg0); +REGISTER(reg_irq_cfg2); + +REGISTER(reg_prox_ctrl0); +REGISTER(reg_prox_ctrl1); +REGISTER(reg_prox_ctrl2); +REGISTER(reg_prox_ctrl3); +REGISTER(reg_prox_ctrl4); +REGISTER(reg_prox_ctrl5); +REGISTER(reg_prox_ctrl6); +REGISTER(reg_prox_ctrl7); -- To view, visit https://review.coreboot.org/c/coreboot/+/47866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac Gerrit-Change-Number: 47866 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/google/zork/var/vliboz: Add LTE_RST power sequence
by EricR Lai (Code Review) 05 Dec '20

05 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47912 ) Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ...................................................................... mb/google/zork/var/vliboz: Add LTE_RST power sequence Latest HW schematic add LTE_RST pin to control module power sequence. BUG=b:173490220 BRANCH=zork TEST=measure the waveform is meet the LTE module spec. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed --- M src/mainboard/google/zork/smihandler.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/Makefile.inc M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/vilboz/variant.c 5 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47912/1 diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 1c26d45..0b732a8 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -10,11 +10,17 @@ #include <variant/gpio.h> #include <console/console.h> +void __weak variant_smi_sleep(u8 slp_typ) +{ + /* Leave for the variant to implement if necessary. */ +} + void mainboard_smi_gpi(u32 gpi_sts) { if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_process_events(); } + void mainboard_smi_sleep(u8 slp_typ) { size_t num_gpios; @@ -26,6 +32,8 @@ gpios = variant_sleep_gpio_table(&num_gpios, slp_typ); program_gpios(gpios, num_gpios); + + variant_smi_sleep(slp_typ); } int mainboard_smi_apmc(u8 apmc) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 4ec6add..3a360a8 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -82,5 +82,7 @@ bool variant_has_fingerprint(void); /* Return true if the board needs an extra fpmcu delay. */ bool fpmcu_needs_delay(void); +/* allow each variants to customize smi sleep flow. */ +void variant_smi_sleep(u8 slp_typ); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index af38c88..963eee4 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -4,3 +4,5 @@ ramstage-y += variant.c ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 6fba0e2..3ce59db 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -19,6 +19,29 @@ static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { /* P sensor INT */ PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + /* LTE_FW_RST_L */ + PAD_GPO(GPIO_89, HIGH), +}; + +static const struct soc_amd_gpio vilboz_early_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* LTE_FW_RST_L */ + PAD_GPO(GPIO_89, LOW), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -41,3 +64,9 @@ *size = ARRAY_SIZE(vilboz_gpio_set_stage_ram); return vilboz_gpio_set_stage_ram; } + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(vilboz_early_gpio_table); + return vilboz_early_gpio_table; +} diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index cbc160e..3d587cc 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { @@ -31,3 +34,11 @@ *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } + +void variant_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + /* Assert LTE_FW_RST_L */ + gpio_output(GPIO_89, 0); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed Gerrit-Change-Number: 47912 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: mb/google/dedede: Configure Acoustic noise mitigation UPDs
by Maulik V Vaghela (Code Review) 05 Dec '20

05 Dec '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48231 ) Change subject: mb/google/dedede: Configure Acoustic noise mitigation UPDs ...................................................................... mb/google/dedede: Configure Acoustic noise mitigation UPDs Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4 which is calibrated value for board. Other values like PreWake, Rampup and RampDown are 0 bydefault. BUG=b:162192346 BRANCH=dedede TEST=Correct value is passed to UPD and Acoustic noise test passes. Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48231/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index dcb46cc..3e88170 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -66,6 +66,10 @@ register "ImonOffset" = "1400" # Imon Offset = 1.4 register "ImonSlope" = "100" # Imon Slope = 1.0 + # Enable Acoustic noise mitigation and set slew rate to 1/4 + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "1" + device domain 0 on device pci 05.0 on # IPU - MIPI Camera chip drivers/intel/mipi_camera -- To view, visit https://review.coreboot.org/c/coreboot/+/48231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1 Gerrit-Change-Number: 48231 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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