coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/common: [TEST]trigger data_clear everytime system boots fro...
by Rizwan Qureshi (Code Review) 05 Dec '20

05 Dec '20

Rizwan Qureshi has uploaded a new patch set (#3) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/48341 ) Change subject: soc/intel/common: [TEST]trigger data_clear everytime system boots from RO ...................................................................... soc/intel/common: [TEST]trigger data_clear everytime system boots from RO Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I2c2f0c7fc8b4ee692a2b1fc2456578be2d007686 --- M src/console/init.c M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/48341/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c2f0c7fc8b4ee692a2b1fc2456578be2d007686 Gerrit-Change-Number: 48341 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation/mainboard/ocp: Update DeltaLake
by Jonathan Zhang (Code Review) 05 Dec '20

05 Dec '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48252 ) Change subject: Documentation/mainboard/ocp: Update DeltaLake ...................................................................... Documentation/mainboard/ocp: Update DeltaLake DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has reached EVT exit parity. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 48 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/48252/1 diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 57e727f..a3d34eb 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -9,23 +9,25 @@ OCP Delta Lake server platform is a component of multi-host server system Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. -Delta Lake server is a single socket Cooper Lake Scalable Processor server. +Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server. Yosemite-V3 has multiple configurations. Depending on configurations, it may host up to 4 Delta Lake servers in one sled. -The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners +The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative -solution. This development is moving toward EVT exit equivalent status. +solution. This development reached EVT exit equivalent status. ## Required blobs This board currently requires: - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP - (Mass Production) of CooperLake Scalable Processor when the FSP is mature. + (Mass Production) of CPX-SP. - Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. -- ME binary: Not yet available to the public. +- ME binary: Ignition binary will be made public some time after the MP + of CPX-SP. +- ACM binaries: only required for CBnT enablement. ## Payload - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload. @@ -48,6 +50,16 @@ To connect to console through SOL (Serial Over Lan): sol-util slotx +## Firmware configurations +[ChromeOS VPD] is used to store most of the firmware configurations. +RO_VPD region holds default values, while RW_VPD region holds customized +values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. + ## Working features The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root] as initramfs. @@ -61,8 +73,12 @@ - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String + - Type 16 -- Physical Memory Array + - Type 17 -- Memory Device + - Type 19 -- Memory Array Mapped Address - Type 32 -- System Boot Information - Type 38 -- IPMI Device Information + - Type 41 -- Onboard Devices Extended Information - Type 127 -- End-of-Table - BMC integration: - BMC readiness check @@ -71,6 +87,12 @@ - POST complete pin acknowledgement - Check BMC version: ipmidump -device - SEL record generation +- Converged Bootguard and TXT (CBnT) + - TPM + - Bootguard profile 0T + - TXT + - SRTM (verified through tboot) + - memory secret clearance upon ungraceful shutdown - Early serial output - port 80h direct to GPIO - ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT @@ -87,44 +109,40 @@ - Power button - localboot - netboot from IPv6 -- TPM +- basic memory hardware error injection/detection (SMI handler not upstreamed) +- basic PCIe hardware error injection/detection (SMI handler not upstreamed) ## Stress/performance tests passed -- OS warm reboot (300 cycles) -- DC reboot (300 cycles) -- AC reboot (300 cycle) +- OS warm reboot (1000 cycles) +- DC reboot (1000 cycles) +- AC reboot (1000 cycle) - Mprime test (6 hours) - StressAppTest (6 hours) + +## Performance tests on par with traditional firmware - Ptugen (6 hours) -- MLC (Intel Memory Latency Check) - Linkpack - Iperf(IPv6) - FIO -## Firmware configurations -[ChromeOS VPD] is used to store most of the firmware configurations. -RO_VPD region holds default values, while RW_VPD region holds customized -values. - -VPD variables supported are: -- firmware_version: This variable holds overall firmware version. coreboot - uses that value to populate smbios type 1 version field. -- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. +## Other tests passed +- Power +- Thermal ## Known issues -- spsInfoLinux64 command fail to return ME version. -- fwts test failures related to mtrr. -- kernel error message related to SleepButton ACPI event. +- MLC (Intel Memory Latency Check) and stream performance issue +- PCH prochot assertion during FSP-S execution +- HECI access at OS run time: + - spsInfoLinux64 command fail to return ME version + - ptugen command fail to get memory power ## Feature gaps -- SMBIOS: - - Type 16 -- Physical Memory Array - - Type 17 -- Memory Device - - Type 19 -- Memory Array Mapped Address - - Type 41 -- Onboard Devices Extended Information -- Verified measurement through CBnT -- Boot guard of CBnT -- RO_VPD region as well as other RO regions are not write protected. +- flashrom command not able to update ME region +- ACPI APEI tables +- PCIe hotplug, Virtual Pin Ports +- PCIe Live Error Recovery +- RO_VPD region as well as other RO regions are not write protected +- Not able to selectively enable/disable core ## Technology -- To view, visit https://review.coreboot.org/c/coreboot/+/48252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce Gerrit-Change-Number: 48252 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mmu: Provide API to expose mmu memery ranges for all archs
by Meng-Huan Yu (Code Review) 05 Dec '20

05 Dec '20

Meng-Huan Yu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48113 ) Change subject: mmu: Provide API to expose mmu memery ranges for all archs ...................................................................... mmu: Provide API to expose mmu memery ranges for all archs Provide lib_get_mmu_ranges() to let payloads could get mmu information for all used memory regions. * Move mmu related structure from arm64 mmu.h to new include/mmu_range.h * Provide empty API for x86 and arm. BUG=b:171858277 TEST=Build in x86, arm, arm64. emerge-zork libpayload depthcharge emerge-nyan libpayload depthcharge emerge-asurada libpayload depthcharge Signed-off-by: Meng-Huan Yu <menghuan(a)google.com> Change-Id: I39b24aefc9dbe530169b272e839d0e1e7c697742 --- M payloads/libpayload/arch/arm/Makefile.inc A payloads/libpayload/arch/arm/mmu.c M payloads/libpayload/arch/arm64/mmu.c M payloads/libpayload/arch/x86/Makefile.inc A payloads/libpayload/arch/x86/mmu.c M payloads/libpayload/include/arm64/arch/mmu.h M payloads/libpayload/include/libpayload.h A payloads/libpayload/include/mmu_range.h 8 files changed, 131 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/48113/1 diff --git a/payloads/libpayload/arch/arm/Makefile.inc b/payloads/libpayload/arch/arm/Makefile.inc index c973601..6287641 100644 --- a/payloads/libpayload/arch/arm/Makefile.inc +++ b/payloads/libpayload/arch/arm/Makefile.inc @@ -37,6 +37,7 @@ libc-y += exception_asm.S exception.c libc-y += cache.c cpu.S libc-y += selfboot.c +libc-y += mmu.c # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed. libc-$(CONFIG_LP_GPL) += memcpy.S memset.S memmove.S diff --git a/payloads/libpayload/arch/arm/mmu.c b/payloads/libpayload/arch/arm/mmu.c new file mode 100644 index 0000000..e90426a --- /dev/null +++ b/payloads/libpayload/arch/arm/mmu.c @@ -0,0 +1,34 @@ +/* + * + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +const struct mmu_ranges* lib_get_mmu_ranges(void) +{ + return NULL; +} diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index cb0081b..6caf912 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -705,3 +705,8 @@ mmu_init(&usedmem_ranges); mmu_enable(); } + +const struct mmu_ranges* lib_get_mmu_ranges(void) +{ + return &usedmem_ranges; +} diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc index 41228f2..e373a2e 100644 --- a/payloads/libpayload/arch/x86/Makefile.inc +++ b/payloads/libpayload/arch/x86/Makefile.inc @@ -35,6 +35,7 @@ libc-y += selfboot.c libc-y += exception_asm.S exception.c libc-y += delay.c +libc-y += mmu.c # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed. libc-$(CONFIG_LP_GPL) += string.c diff --git a/payloads/libpayload/arch/x86/mmu.c b/payloads/libpayload/arch/x86/mmu.c new file mode 100644 index 0000000..e90426a --- /dev/null +++ b/payloads/libpayload/arch/x86/mmu.c @@ -0,0 +1,34 @@ +/* + * + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +const struct mmu_ranges* lib_get_mmu_ranges(void) +{ + return NULL; +} diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h index 5a1dd98..273e6e4 100644 --- a/payloads/libpayload/include/arm64/arch/mmu.h +++ b/payloads/libpayload/include/arm64/arch/mmu.h @@ -31,31 +31,12 @@ #include <libpayload.h> -struct mmu_memrange { - uint64_t base; - uint64_t size; - uint64_t type; -}; - -struct mmu_ranges { - struct mmu_memrange entries[SYSINFO_MAX_MEM_RANGES]; - size_t used; -}; - /* * Symbols taken from linker script * They mark the start and end of the region used by payload */ extern char _start[], _end[]; -/* Memory attributes for mmap regions - * These attributes act as tag values for memrange regions - */ - -#define TYPE_NORMAL_MEM 1 -#define TYPE_DEV_MEM 2 -#define TYPE_DMA_MEM 3 - /* Descriptor attributes */ #define INVALID_DESC 0x0 diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index f206fea..83f3c25 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -64,6 +64,7 @@ #include <sysinfo.h> #include <pci.h> #include <archive.h> +#include <mmu_range.h> /* Double-evaluation unsafe min/max, for bitfields and outside of functions */ #define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) @@ -526,6 +527,7 @@ int lib_get_sysinfo(void); void lib_sysinfo_get_memranges(struct memrange **ranges, uint64_t *nranges); +const struct mmu_ranges* lib_get_mmu_ranges(void); /* Timer functions. */ /* Defined by each architecture. */ diff --git a/payloads/libpayload/include/mmu_range.h b/payloads/libpayload/include/mmu_range.h new file mode 100644 index 0000000..17aaec6 --- /dev/null +++ b/payloads/libpayload/include/mmu_range.h @@ -0,0 +1,54 @@ +/* + * + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __MMU_MEMRANGE_H__ +#define __MMU_MEMRANGE_H__ + +#include <stddef.h> +#include <sysinfo.h> + +struct mmu_memrange { + uint64_t base; + uint64_t size; + uint64_t type; +}; + +struct mmu_ranges { + struct mmu_memrange entries[SYSINFO_MAX_MEM_RANGES]; + size_t used; +}; + +/* Memory attributes for mmap regions + * These attributes act as tag values for memrange regions + */ + +#define TYPE_NORMAL_MEM 1 +#define TYPE_DEV_MEM 2 +#define TYPE_DMA_MEM 3 + +#endif // __MMU_MEMRANGE_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/48113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39b24aefc9dbe530169b272e839d0e1e7c697742 Gerrit-Change-Number: 48113 Gerrit-PatchSet: 1 Gerrit-Owner: Meng-Huan Yu <menghuan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/tsc: fix clock divisor range check
by Felix Held (Code Review) 05 Dec '20

05 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48287 ) Change subject: soc/amd/picasso/tsc: fix clock divisor range check ...................................................................... soc/amd/picasso/tsc: fix clock divisor range check The CPU core clock divisor ID needs to be in the range from 8 to 0x30 including both numbers. TEST=Compared with Picasso's PPR #55570 Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/tsc_freq.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/48287/1 diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 8a541fc..55c8665 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -33,7 +33,7 @@ if (!cpudid) { mhz = TSC_DEFAULT_FREQ_MHZ; printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz); - } else if ((cpudid >= 8) && (cpudid < 0x3c)) { + } else if ((cpudid >= 8) && (cpudid <= 0x30)) { mhz = (200 * cpufid) / cpudid; } else { mhz = 25 * cpufid; -- To view, visit https://review.coreboot.org/c/coreboot/+/48287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196 Gerrit-Change-Number: 48287 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/majolica: add functionality to ad EC blob to build
by Felix Held (Code Review) 05 Dec '20

05 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48250 ) Change subject: mb/amd/majolica: add functionality to ad EC blob to build ...................................................................... mb/amd/majolica: add functionality to ad EC blob to build Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/majolica/Kconfig A src/mainboard/amd/majolica/Makefile.inc A src/mainboard/amd/majolica/board.fmd 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/48250/1 diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index b7f8763..2af1c35 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -5,10 +5,26 @@ select SOC_AMD_CEZANNE select MISSING_BOARD_RESET +config FMDFILE + string + default "src/mainboard/amd/majolica/board.fmd" + config MAINBOARD_DIR default "amd/majolica" config MAINBOARD_PART_NUMBER default "MAJOLICA" +config MAJOLICA_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config MAJOLICA_MCHP_FW_FILE + string + depends on MAJOLICA_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/majolica/EC_majolica.bin" + help + The EC firmware blob is usually the first 128kByte of the stock + firmware image. + endif # BOARD_AMD_MAJOLICA diff --git a/src/mainboard/amd/majolica/Makefile.inc b/src/mainboard/amd/majolica/Makefile.inc new file mode 100644 index 0000000..ce3119c --- /dev/null +++ b/src/mainboard/amd/majolica/Makefile.inc @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +PHONY+=add_mchp_fw +INTERMEDIATE+=add_mchp_fw + +ifeq ($(CONFIG_MAJOLICA_HAVE_MCHP_FW),y) +add_mchp_fw: $(obj)/coreboot.pre + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MAJOLICA_MCHP_FW_FILE) --fill-upward +else +files_added:: warn_no_mchp +endif # CONFIG_MAJOLICA_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an the Microchip EC FW.\n" + printf "Do not flash this image. Your Majolica's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/majolica/board.fmd b/src/mainboard/amd/majolica/board.fmd new file mode 100644 index 0000000..442d80f --- /dev/null +++ b/src/mainboard/amd/majolica/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 128K + RW_MRC_CACHE 64K + FMAP 4K + COREBOOT(CBFS) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6 Gerrit-Change-Number: 48250 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/majolica: add skeleton of Cezanne reference board
by Felix Held (Code Review) 05 Dec '20

05 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48238 ) Change subject: mb/amd/majolica: add skeleton of Cezanne reference board ...................................................................... mb/amd/majolica: add skeleton of Cezanne reference board This is an adapted copy of mainboard/example/min86 that is currently only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't expected to reach boot block at the moment. It will be extended in future follow-up commits. Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/mainboard/amd/majolica/Kconfig A src/mainboard/amd/majolica/Kconfig.name A src/mainboard/amd/majolica/board_info.txt A src/mainboard/amd/majolica/devicetree.cb 4 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48238/1 diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig new file mode 100644 index 0000000..b7f8763 --- /dev/null +++ b/src/mainboard/amd/majolica/Kconfig @@ -0,0 +1,14 @@ +if BOARD_AMD_MAJOLICA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_CEZANNE + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + default "amd/majolica" + +config MAINBOARD_PART_NUMBER + default "MAJOLICA" + +endif # BOARD_AMD_MAJOLICA diff --git a/src/mainboard/amd/majolica/Kconfig.name b/src/mainboard/amd/majolica/Kconfig.name new file mode 100644 index 0000000..8c305cf7 --- /dev/null +++ b/src/mainboard/amd/majolica/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_MAJOLICA + bool "Majolica" diff --git a/src/mainboard/amd/majolica/board_info.txt b/src/mainboard/amd/majolica/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/majolica/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb new file mode 100644 index 0000000..62d9edf --- /dev/null +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/amd/cezanne + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/48238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933 Gerrit-Change-Number: 48238 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: add skeleton for new SoC
by Felix Held (Code Review) 05 Dec '20

05 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48237 ) Change subject: soc/amd/cezanne: add skeleton for new SoC ...................................................................... soc/amd/cezanne: add skeleton for new SoC This is based on the minimal example code in soc/example/min86 and was adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF support. In its current state this won't even reach the boot block, but will pass the build bot. The missing parts for that will be added in future patches. This is an attempt to not go the usual route to create a copy of a previous SoC generation and the make changes to the code to work for the new SoC, but to start from a nearly empty directory and then add the actual code stage by stage and component by component. Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/bootblock.c A src/soc/amd/cezanne/chip.c A src/soc/amd/cezanne/include/soc/psp_transfer.h A src/soc/amd/cezanne/romstage.c A src/soc/amd/cezanne/timer.c 7 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/48237/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig new file mode 100644 index 0000000..50d2720 --- /dev/null +++ b/src/soc/amd/cezanne/Kconfig @@ -0,0 +1,108 @@ +config SOC_AMD_CEZANNE + bool + help + AMD Cezanne support + +if SOC_AMD_CEZANNE + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select RESET_VECTOR_IN_RAM + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select NO_MONOTONIC_TIMER # TODO: replace + select UNKNOWN_TSC_RATE # TODO: replace + +config EARLY_RESERVED_DRAM_BASE + hex + default 0x2000000 + help + This variable defines the base address of the DRAM which is reserved + for usage by coreboot in early stages (i.e. before ramstage is up). + This memory gets reserved in BIOS tables to ensure that the OS does + not use it, thus preventing corruption of OS memory in case of S3 + resume. + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x1000 + +config PSP_APOB_DRAM_ADDRESS + hex + default 0x2001000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Increase this value if preram cbmem console is getting truncated + +config BOOTBLOCK_ADDR + hex + default 0x2030000 + help + Sets the address in DRAM where bootblock should be loaded. + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x10000 + help + Sets the size of the bootblock stage that should be loaded in DRAM. + This variable controls the DRAM allocation size in linker script + for bootblock stage. + +config X86_RESET_VECTOR + hex + depends on ARCH_X86 + default 0x203fff0 + help + Sets the reset vector within bootblock where x86 starts execution. + Reset vector is supposed to live at offset -0x10 from end of + bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10. + +config ROMSTAGE_ADDR + hex + default 0x2040000 + help + Sets the address in DRAM where romstage should be loaded. + +config ROMSTAGE_SIZE + hex + default 0x80000 + help + Sets the size of DRAM allocation for romstage in linker script. + +config FSP_M_ADDR + hex + default 0x20C0000 + help + Sets the address in DRAM where FSP-M should be loaded. cbfstool + performs relocation of FSP-M to this address. + +config FSP_M_SIZE + hex + default 0x80000 + help + Sets the size of DRAM allocation for FSP-M in linker script. + +config RAMBASE + hex + default 0x10000000 + +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 + +config MMCONF_BUS_NUMBER + int + default 64 + +endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc new file mode 100644 index 0000000..67eb427 --- /dev/null +++ b/src/soc/amd/cezanne/Makefile.inc @@ -0,0 +1,12 @@ +ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include + +endif diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c new file mode 100644 index 0000000..43cac33 --- /dev/null +++ b/src/soc/amd/cezanne/bootblock.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <bootblock_common.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ +} + +void bootblock_soc_early_init(void) +{ +} + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c new file mode 100644 index 0000000..9ab409f --- /dev/null +++ b/src/soc/amd/cezanne/chip.c @@ -0,0 +1,3 @@ +#include <device/device.h> + +struct chip_operations soc_amd_cezanne_ops = { NULL }; diff --git a/src/soc/amd/cezanne/include/soc/psp_transfer.h b/src/soc/amd/cezanne/include/soc/psp_transfer.h new file mode 100644 index 0000000..f5cd427 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/psp_transfer.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_PSP_TRANSFER_H +#define AMD_CEZANNE_PSP_TRANSFER_H + +#define TRANSFER_INFO_SIZE 64 +#define TIMESTAMP_BUFFER_SIZE 0x200 + +#endif /* AMD_CEZANNE_PSP_TRANSFER_H */ diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c new file mode 100644 index 0000000..91074b2 --- /dev/null +++ b/src/soc/amd/cezanne/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/amd/cezanne/timer.c b/src/soc/amd/cezanne/timer.c new file mode 100644 index 0000000..9054ffd --- /dev/null +++ b/src/soc/amd/cezanne/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5 Gerrit-Change-Number: 48237 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: [TEST]trigger data_clear everytime system boots fro...
by Sridhar Siricilla (Code Review) 05 Dec '20

05 Dec '20

Sridhar Siricilla has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/48341 ) Change subject: soc/intel/common: [TEST]trigger data_clear everytime system boots from RO ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/48341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c2f0c7fc8b4ee692a2b1fc2456578be2d007686 Gerrit-Change-Number: 48341 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/common: [TEST]trigger data_clear everytime system boots fro...
by Sridhar Siricilla (Code Review) 05 Dec '20

05 Dec '20

Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48341 to look at the new patch set (#2). Change subject: soc/intel/common: [TEST]trigger data_clear everytime system boots from RO ...................................................................... soc/intel/common: [TEST]trigger data_clear everytime system boots from RO Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2c2f0c7fc8b4ee692a2b1fc2456578be2d007686 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/48341/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c2f0c7fc8b4ee692a2b1fc2456578be2d007686 Gerrit-Change-Number: 48341 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Felix Singer (Code Review) 05 Dec '20

05 Dec '20

Hello build bot (Jenkins), Patrick Rudolph, Christian Walter, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48293 to look at the new patch set (#4). Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... mb/prodrive/hermes: Wrap UART driver by PCI device Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/48293/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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