Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48299 )
Change subject: mb/siemens/chili: Move mainboard/gpio.h to variant/gpio.h
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Patch Set 2: Code-Review+2
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Change subject: mb/clevo/kbl-u: Add a seperate method for early GPIOs
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Patch Set 2: Code-Review+2
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Change subject: mb/clevo/kbl-u: Move mainboard/gpio.h to variant/gpio.h
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Change subject: mb/clevo/cml-u: Move mainboard/gpio.h to variant/gpio.h
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Change subject: mb/siemens/chili: Move mainboard/gpio.h to variant/gpio.h
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Change subject: mb/clevo/kbl-u: Add a seperate method for early GPIOs
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Change subject: mb/clevo/kbl-u: Move mainboard/gpio.h to variant/gpio.h
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Change subject: mb/clevo/cml-u: Move mainboard/gpio.h to variant/gpio.h
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48304 )
Change subject: soc/intel/skl: set PEG port state to auto
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG@13
PS1, Line 13: Test: powertop on X11SSM-F shows SoC in PC8 instead of just PC3
> I'm not sure, iirc I got to PC5 only or so on vendor; if you insist, I can test it, but not sure if […]
tested; PC8 on vendor oob
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48304
to look at the new patch set (#3).
Change subject: soc/intel/skl: set PEG port state to auto
......................................................................
soc/intel/skl: set PEG port state to auto
Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.
Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
instead of just PC3.
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
---
M src/soc/intel/skylake/romstage/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48304/3
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