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Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48304 ) Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... Patch Set 1: > Patch Set 1: Code-Review+1 > > (2 comments) > > Does this need testing on a lot of devices, or is it relatively safe to enable? shouln't, as it's the default for other platforms as well -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Dec 2020 15:04:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Paul Menzel (Code Review) 04 Dec '20

04 Dec '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48304 ) Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Does this need testing on a lot of devices, or is it relatively safe to enable? https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG@9 PS1, Line 9: them Nit: Does that mean the PEG ports? Maybe write it out. https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG@13 PS1, Line 13: Test: powertop on X11SSM-F shows SoC in PC8 instead of just PC3 Wow. Very nice! Maybe mention if the vendor firmware does that too. -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Dec 2020 14:45:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48304 ) Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Dec 2020 14:04:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: move smi_util to common block
by Felix Held (Code Review) 04 Dec '20

04 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48220 ) Change subject: soc/amd: move smi_util to common block ...................................................................... soc/amd: move smi_util to common block Since both SoCs unconditionally select HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any functions that are only present when this option is selected, so this patch also drops the guards in the Makefile.inc file. Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/smi/Kconfig A src/soc/amd/common/block/smi/Makefile.inc R src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/smi_util.c 8 files changed, 17 insertions(+), 137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48220/1 diff --git a/src/soc/amd/common/block/smi/Kconfig b/src/soc/amd/common/block/smi/Kconfig new file mode 100644 index 0000000..1b05b14 --- /dev/null +++ b/src/soc/amd/common/block/smi/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_SMI + bool + default n + help + Select this option to add the common functions for setting up the SMI + configuration to the build. diff --git a/src/soc/amd/common/block/smi/Makefile.inc b/src/soc/amd/common/block/smi/Makefile.inc new file mode 100644 index 0000000..b6239ae --- /dev/null +++ b/src/soc/amd/common/block/smi/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMI),y) + +bootblock-y += smi_util.c +romstage-y += smi_util.c +ramstage-y += smi_util.c +smm-y += smi_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMI diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c similarity index 97% rename from src/soc/amd/picasso/smi_util.c rename to src/soc/amd/common/block/smi/smi_util.c index 39b2b95..d63f585 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * SMM utilities used in both SMM and normal mode - */ +/* SMI utilities used in both SMM and normal mode */ #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9e9c99a..5da4731 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b5e409b..c772783 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -20,7 +20,6 @@ bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += gpio.c -bootblock-y += smi_util.c bootblock-y += config.c bootblock-y += reset.c @@ -35,7 +34,6 @@ romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c romstage-y += config.c romstage-y += mrc_cache.c @@ -66,7 +64,6 @@ ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c ramstage-y += monotonic_timer.c @@ -83,7 +80,6 @@ ramstage-y += dmi.c smm-y += smihandler.c -smm-y += smi_util.c smm-y += monotonic_timer.c smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index f24d202..d672726 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -37,6 +37,7 @@ select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 8cdf6cc..969f512 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -19,7 +19,6 @@ bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -32,7 +31,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c verstage-y += gpio.c @@ -61,7 +59,6 @@ ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c @@ -72,7 +69,6 @@ smm-y += monotonic_timer.c smm-y += smihandler.c -smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c deleted file mode 100644 index 39b2b95..0000000 --- a/src/soc/amd/stoneyridge/smi_util.c +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * SMM utilities used in both SMM and normal mode - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/southbridge.h> -#include <soc/smi.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/smi.h> - -void configure_smi(uint8_t smi_num, uint8_t mode) -{ - uint8_t reg32_offset, bit_offset; - uint32_t reg32; - - if (smi_num >= NUMBER_SMITYPES) { - printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); - return; - } - - /* 16 sources per register, 2 bits per source; registers are 4 bytes */ - reg32_offset = (smi_num / 16) * 4; - bit_offset = (smi_num % 16) * 2; - - reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); - reg32 &= ~(0x3 << (bit_offset)); - reg32 |= (mode & 0x3) << bit_offset; - smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); -} - -/** - * Configure generation of interrupts for given GEVENT pin - * - * @param gevent The GEVENT pin number. Valid values are 0 thru 23 - * @param mode The type of event this pin should generate. Note that only - * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. - * @param level SMI__SCI_LVL_LOW or SMI_SCI_LVL_HIGH - */ -void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) -{ - uint32_t reg32; - /* GEVENT pins range from [0:23] */ - if (gevent >= SMI_GEVENTS) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, mode); - - /* And set set the trigger level */ - reg32 = smi_read32(SMI_REG_SMITRIG0); - reg32 &= ~(1 << gevent); - reg32 |= (level & 0x1) << gevent; - smi_write32(SMI_REG_SMITRIG0, reg32); -} - -/** - * Configure generation of SCIs. - */ -void configure_scimap(const struct sci_source *sci) -{ - uint32_t reg32; - - /* GEVENT pins range */ - if (sci->scimap >= SCIMAPS) { - printk(BIOS_WARNING, "BUG: Invalid SCIMAP: %u\n", - sci->scimap); - return; - } - - /* GPEs range from [0:31] */ - if (sci->gpe >= SCI_GPES) { - printk(BIOS_WARNING, "BUG: Invalid SCI GPE: %u\n", sci->gpe); - return; - } - - printk(BIOS_DEBUG, "SCIMAP %u maps to GPE %u (active %s, %s trigger)\n", - sci->scimap, sci->gpe, - (!!sci->direction) ? "high" : "low", - (!!sci->level) ? "level" : "edge"); - - /* Map Gevent to SCI GPE# */ - smi_write8(SMI_SCI_MAP(sci->scimap), sci->gpe); - - /* Set the trigger direction (high/low) */ - reg32 = smi_read32(SMI_SCI_TRIG); - reg32 &= ~(1 << sci->gpe); - reg32 |= !!sci->direction << sci->gpe; - smi_write32(SMI_SCI_TRIG, reg32); - - /* Set the trigger level (edge/level) */ - reg32 = smi_read32(SMI_SCI_LEVEL); - reg32 &= ~(1 << sci->gpe); - reg32 |= !!sci->level << sci->gpe; - smi_write32(SMI_SCI_LEVEL, reg32); -} - -void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes) -{ - size_t i; - - for (i = 0; i < num_gpes; i++) - configure_scimap(scis + i); -} - -/** Disable events from given GEVENT pin */ -void disable_gevent_smi(uint8_t gevent) -{ - /* GEVENT pins range from [0:23] */ - if (gevent > 23) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, SMI_MODE_DISABLE); -} - -uint16_t pm_acpi_smi_cmd_port(void) -{ - return pm_read16(PM_ACPI_SMI_CMD); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e Gerrit-Change-Number: 48220 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/mandolin: Unify devicetree formatting for 00:14 devices
by Paul Menzel (Code Review) 04 Dec '20

04 Dec '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46560 ) Change subject: mb/amd/mandolin: Unify devicetree formatting for 00:14 devices ...................................................................... mb/amd/mandolin: Unify devicetree formatting for 00:14 devices To accommodate also `off`, two spaces are used after `on` to align comments. This unifies the devicetree files of the two variants. Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46560/1 diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 1553288..fd07e19 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -160,8 +160,8 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SMBus - device pci 14.3 on # D14F3 bridge + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index b519e4a..2651916 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -160,8 +160,8 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SM - device pci 14.3 on # - D14F3 bridge + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Gerrit-Change-Number: 46560 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment
by Paul Menzel (Code Review) 04 Dec '20

04 Dec '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46559 ) Change subject: mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment ...................................................................... mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment This reduces the difference with Cereme’s devicetree file. Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46559/1 diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 3de5812..b519e4a 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -148,7 +148,7 @@ device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocesor + device pci 0.2 on end # Crypto Coprocessor device pci 0.3 on end # USB 3.1 device pci 0.4 on end # USB 3.1 device pci 0.5 on end # Audio -- To view, visit https://review.coreboot.org/c/coreboot/+/46559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Gerrit-Change-Number: 46559 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/mandolin: use more readable size formats in FMAP files
by Felix Held (Code Review) 04 Dec '20

04 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48245 ) Change subject: mb/amd/mandolin: use more readable size formats in FMAP files ...................................................................... mb/amd/mandolin: use more readable size formats in FMAP files Since the FMD file isn't parsed any more by a shell script in the SoC's Makefile.inc, we can use better human-readable numbers for the section sizes. TEST=Timeless build results in identical image. Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/variants/cereme/board.fmd M src/mainboard/amd/mandolin/variants/mandolin/board.fmd 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48245/1 diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd index b55b8b5..442d80f 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/board.fmd +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -1,8 +1,8 @@ FLASH@0xFF000000 16M { BIOS { - EC 0x20000 - RW_MRC_CACHE 0x10000 - FMAP 0x1000 + EC 128K + RW_MRC_CACHE 64K + FMAP 4K COREBOOT(CBFS) } } diff --git a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd index 2845e64..33b281d 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd +++ b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd @@ -1,8 +1,8 @@ FLASH@0xFF800000 8M { BIOS { - EC 0x20000 + EC 128K RW_MRC_CACHE 64K - FMAP 0x1000 + FMAP 4K COREBOOT(CBFS) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734 Gerrit-Change-Number: 48245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSET
by Felix Held (Code Review) 04 Dec '20

04 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48243 ) Change subject: mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSET ...................................................................... mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSET TEST=Timeless build results in identical image. Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Makefile.inc 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48243/1 diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 795a28f..448c12a 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -21,7 +21,6 @@ ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y) -MANDOLIN_MICROCHIP_FW_OFFSET=0 add_mchp_fw: $(obj)/coreboot.pre $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MANDOLIN_MCHP_FW_FILE) --fill-upward -- To view, visit https://review.coreboot.org/c/coreboot/+/48243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123 Gerrit-Change-Number: 48243 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/x86: Add optional parallel_mp init support
by Arthur Heymans (Code Review) 04 Dec '20

04 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48210 ) Change subject: mb/emulation/x86: Add optional parallel_mp init support ...................................................................... mb/emulation/x86: Add optional parallel_mp init support This makes it possible to select both the legacy LAPIC AP init or the newer parallel MP init. Tested on i440fx with -smp 32. Note does not work on x86_64! Change-Id: I007b052ccd3c34648cd172344d55768232acfd88 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/northbridge.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48210/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 06d0ba8..c92bdf2 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -9,6 +9,19 @@ if CPU_QEMU_X86 choice + prompt "AP init" + default CPU_QEMU_X86_LAPIC_INIT + +config CPU_QEMU_X86_LAPIC_INIT + bool "Legacy serial LAPIC init" + +config CPU_QEMU_X86_PARALLEL_MP + bool "Parallel MP init" + select PARALLEL_MP + +endchoice + +choice prompt "SMM support" default CPU_QEMU_X86_ASEG_SMM @@ -18,6 +31,7 @@ config CPU_QEMU_X86_ASEG_SMM bool "SMM ASEG" + depends on !PARALLEL_MP select SMM_ASEG #config CPU_QEMU_X86_TSEG_SMM diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index d19d6c8..f49d47da 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/lapic_def.h> +#include <cpu/x86/mp.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -244,9 +245,22 @@ #endif }; +static const struct mp_ops mp_ops_no_smm = { + .get_cpu_count = fw_cfg_max_cpus, +}; + +void mp_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops_no_smm)) + printk(BIOS_ERR, "MP initialization failure.\n"); +} + static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + if (CONFIG(PARALLEL_MP)) + mp_cpu_bus_init(dev); + else + initialize_cpus(dev->link_list); } static void cpu_bus_scan(struct device *bus) -- To view, visit https://review.coreboot.org/c/coreboot/+/48210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I007b052ccd3c34648cd172344d55768232acfd88 Gerrit-Change-Number: 48210 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/qemu-x86: Increase MAX_CPUS to have actual AP init
by Arthur Heymans (Code Review) 04 Dec '20

04 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48209 ) Change subject: cpu/qemu-x86: Increase MAX_CPUS to have actual AP init ...................................................................... cpu/qemu-x86: Increase MAX_CPUS to have actual AP init CONFIG_MAX_CPUS=4 is the maximum supported with SMM_ASEG. TESTED: on q35 and i440fx -smp 4/32. Change-Id: I696856870e34e7a7ad580bc83c6b38f1dfb4511d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48209/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 8ccf437..06d0ba8 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -26,6 +26,11 @@ endchoice +config MAX_CPUS + int + default 4 if SMM_ASEG + default 32 + config CPU_QEMU_X86_64 bool "Experimental 64bit support" select ARCH_ALL_STAGES_X86_64 -- To view, visit https://review.coreboot.org/c/coreboot/+/48209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I696856870e34e7a7ad580bc83c6b38f1dfb4511d Gerrit-Change-Number: 48209 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020