coreboot-gerrit December 2020

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Change in coreboot[master]: cpu/x86/lapic/secondary.S: Adapt for x86_64
by Arthur Heymans (Code Review) 04 Dec '20

04 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48221 ) Change subject: cpu/x86/lapic/secondary.S: Adapt for x86_64 ...................................................................... cpu/x86/lapic/secondary.S: Adapt for x86_64 Adapt the old lapic init code for x86_64. Change-Id: I5128ed574323025e927137870fb10b23d06bc01d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/lapic/secondary.S 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/48221/1 diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 8a44112..c5784cc 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -33,7 +33,11 @@ _secondary_gdt_addr: gdtaddr: .word 0 /* the table limit */ +#ifdef __x86_64__ + .quad 0 +#else .long 0 /* we know the offset */ +#endif _secondary_start_end: @@ -54,14 +58,22 @@ /* Load the Interrupt descriptor table */ lidt idtarg +#ifdef __x86_64__ + /* entry64.inc preserves ebx. */ + #include <cpu/x86/64bit/entry64.inc> + mov secondary_stack, %rsp + mov secondary_cpu_index, %rdi +#else /* Set the stack pointer, and flag that we are done */ xorl %eax, %eax movl secondary_stack, %esp + andl $0xfffffff0, %esp sub $12, %esp /* maintain 16-byte alignment for the call below */ movl secondary_cpu_index, %edi pushl %edi movl %eax, secondary_stack +#endif call secondary_cpu_init 1: hlt -- To view, visit https://review.coreboot.org/c/coreboot/+/48221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5128ed574323025e927137870fb10b23d06bc01d Gerrit-Change-Number: 48221 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/qemu-x86: Add the option to have no SMM
by Arthur Heymans (Code Review) 04 Dec '20

04 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48208 ) Change subject: cpu/qemu-x86: Add the option to have no SMM ...................................................................... cpu/qemu-x86: Add the option to have no SMM Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Kconfig M src/southbridge/intel/i82801ix/Kconfig 2 files changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/48208/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 87d02fc..8ccf437 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -5,10 +5,27 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE - select SMM_ASEG if CPU_QEMU_X86 +choice + prompt "SMM support" + default CPU_QEMU_X86_ASEG_SMM + +config CPU_QEMU_X86_NO_SMM + bool "No SMM" + select NO_SMM + +config CPU_QEMU_X86_ASEG_SMM + bool "SMM ASEG" + select SMM_ASEG + +#config CPU_QEMU_X86_TSEG_SMM +# bool "SMM TSEG" +# select SMM_TSEG + +endchoice + config CPU_QEMU_X86_64 bool "Experimental 64bit support" select ARCH_ALL_STAGES_X86_64 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index e1405cf..11a6d39 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -3,7 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select HAVE_SMI_HANDLER + select HAVE_SMI_HANDLER if !NO_SMM select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select IOAPIC @@ -15,7 +15,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_SMM if !NO_SMM select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG -- To view, visit https://review.coreboot.org/c/coreboot/+/48208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a Gerrit-Change-Number: 48208 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/cbfs.c: Update the ro bootdevice in CBMEM init in romstage
by Arthur Heymans (Code Review) 04 Dec '20

04 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48283 ) Change subject: lib/cbfs.c: Update the ro bootdevice in CBMEM init in romstage ...................................................................... lib/cbfs.c: Update the ro bootdevice in CBMEM init in romstage Use the cbmem mcache in romstage when cbmem is online. Change-Id: I8d05c38ad0a1dc4b275efc71b0db8b8a7e7c27ec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/cbfs.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48283/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 5df1d8b..646f912 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -439,9 +439,10 @@ return err; } +static struct cbfs_boot_device ro; + const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro) { - static struct cbfs_boot_device ro; /* Ensure we always init RO mcache, even if first file is from RW. Otherwise it may not be available when needed in later stages. */ @@ -485,12 +486,16 @@ size_t real_size = cbfs_mcache_real_size(cbd->mcache, cbd->mcache_size); void *cbmem_mcache = cbmem_add(cbmem_id, real_size); + printk(BIOS_DEBUG, "CBMEM_MCACHE 0x%08lx\n", (uintptr_t)cbmem_mcache); if (!cbmem_mcache) { printk(BIOS_ERR, "ERROR: Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n", cbmem_id, real_size); return; } memcpy(cbmem_mcache, cbd->mcache, real_size); + + ro.mcache = cbmem_mcache; + ro.mcache_size = real_size; } static void cbfs_mcache_migrate(int unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/48283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d05c38ad0a1dc4b275efc71b0db8b8a7e7c27ec Gerrit-Change-Number: 48283 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHE
by Arthur Heymans (Code Review) 04 Dec '20

04 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48282 ) Change subject: drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHE ...................................................................... drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHE When FSP-T is used, the first thing done in postcar is to call FSP-M to tear down CAR. This is done before cbmem is initialized, which means CBFS_MCACHE is not accessible, which results in FSP-M not being found, failing the boot. TESTED: ocp/deltalake boots again. Change-Id: Icb41b802c636d42b0ebeb3e3850551813accda91 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48282/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 03b9c2b..96ae282 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -113,6 +113,7 @@ config FSP_CAR bool default n + select NO_CBFS_MCACHE help Use FSP APIs to initialize & Tear Down the Cache-As-Ram -- To view, visit https://review.coreboot.org/c/coreboot/+/48282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb41b802c636d42b0ebeb3e3850551813accda91 Gerrit-Change-Number: 48282 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Stanislaw Kaminski (Code Review) 04 Dec '20

04 Dec '20

Stanislaw Kaminski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 12: > I've created https://code.fe80.eu/lynxis/vbtparse to modify the vbt. Surely took me a while, but I figured it out. I used intel_vbt_decode tool to find what's different in VBT provided by you and the one from Coreboot tree (x230.vbt). Turns out that yours has header that says: VBT signature: "$VBT SNB/IVB-MOBILE " While the one provided in your patch is VBT signature: "$VBT SANDYBRIDGE-M " I have used your tool on x230.vbt from the tree, flashed, and now both Linux and Windows boot perfectly fine on FHD screen. Awesome! I hope that you'll excuse me not proposing a merge for this - I'm not a developer by any means, and learning how to do that seems like an investment of time that I don't have. I'll be glad to upload my modified VBT wherever you please, though - just say the word. And thanks for all the help you provided, and for your tool! -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 12 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kilian Neuner <cb(a)9-r.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Stanislaw Kaminski <stanislaw.kaminski(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: clayton craft Gerrit-CC: slact Gerrit-Comment-Date: Fri, 04 Dec 2020 08:38:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/alderlake: Enable the PCH HDA
by V Sowmya (Code Review) 04 Dec '20

04 Dec '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48272 ) Change subject: src/soc/intel/alderlake: Enable the PCH HDA ...................................................................... src/soc/intel/alderlake: Enable the PCH HDA This patch enables the PCH HDA device based on the devicetree configuration. Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/48272/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 868d75e..7e842a2 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -100,6 +100,9 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + m_cfg->PchHdaEnable = is_dev_enabled(dev); + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, -- To view, visit https://review.coreboot.org/c/coreboot/+/48272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0 Gerrit-Change-Number: 48272 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/common: Program SF Mask MSRs for eNEM
by Shreesh Chhabbi (Code Review) 04 Dec '20

04 Dec '20

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47983 to review the following change. Change subject: soc/common: Program SF Mask MSRs for eNEM ...................................................................... soc/common: Program SF Mask MSRs for eNEM Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5781008a1447813317878a722cb894edcd6df946 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 36 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47983/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f427340..06f8c2e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -315,7 +315,7 @@ config USE_CANNONLAKE_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select USE_CAR_NEM_ENHANCED_V1 + select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..e66b0fb 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,21 +51,6 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_CAR_NEM_ENHANCED_V1 - bool - select INTEL_CAR_NEM_ENHANCED - help - This config supports INTEL_CAR_NEM_ENHANCED mode on - SKL, KBL, CNL, WHL, CML and ICL and JSL platforms. - -config USE_CAR_NEM_ENHANCED_V2 - bool - select INTEL_CAR_NEM_ENHANCED - select COS_MAPPED_TO_MSB - help - This config supports INTEL_CAR_NEM_ENHANCED mode on - TGL platform. - config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED @@ -73,6 +58,14 @@ On TGL and JSL platform the class of service configuration is mapped to MSB of MSR IA32_PQR_ASSOC. +config CAR_HAS_SF_MASKS + bool + depends on INTEL_CAR_NEM_ENHANCED + help + In the case of non-inclusive cache architecture Snoop Filter MSR + IA32_L3_SF_MASK_x programming is required along with the data ways. + This is applicable for TGL and beyond. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc6..600399c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -403,8 +403,28 @@ set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ mov %eax, %ebx /* back up the non-eviction mask*/ + +#if CONFIG(CAR_HAS_SF_MASKS) /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 + * Program MSR 0x1891 IA32_CR_SF_QOS_MASK_1 with + * total number of LLC ways + */ + mov %ecx, %eax + movl $IA32_CR_SF_QOS_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with + * total number of LLC ways + */ + movl $IA32_CR_SF_QOS_MASK_2, %ecx + xorl %edx, %edx + wrmsr +#endif + + /* + * Program MSR 0xC91 IA32_L3_MASK_1 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction @@ -417,26 +437,18 @@ xor $~0, %eax /* invert 32 bits */ and %ecx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_1, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_1, %ecx -#endif xorl %edx, %edx wrmsr /* - * Set MSR 0xC92 IA32_L3_MASK_1 or MSR 0x1892 IA32_CR_SF_QOS_MASK_2 + * Program MSR 0xC92 IA32_L3_MASK_2 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ mov %ebx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_2, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_2, %ecx -#endif xorl %edx, %edx wrmsr /* diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 4981205..4fe491f 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -170,7 +170,7 @@ config USE_DENVERTON_NS_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select USE_CAR_NEM_ENHANCED_V1 + select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 52e9a74..fee52e6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -23,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -64,7 +65,6 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - select USE_CAR_NEM_ENHANCED_V1 config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 294f19f8..0a15f05 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -23,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -61,7 +62,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING - select USE_CAR_NEM_ENHANCED_V1 select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ba3af84..731e033 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -32,6 +32,7 @@ select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_INTEL_FSP_REPO @@ -77,7 +78,6 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING - select USE_CAR_NEM_ENHANCED_V1 config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b97b92e..dd14ad2 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -23,7 +23,8 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM + select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM + select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP -- To view, visit https://review.coreboot.org/c/coreboot/+/47983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5781008a1447813317878a722cb894edcd6df946 Gerrit-Change-Number: 47983 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: use load_blob_file API to load SSPM
by tinghan shen (Code Review) 04 Dec '20

04 Dec '20

tinghan shen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47798 ) Change subject: soc/mediatek/mt8183: use load_blob_file API to load SSPM ...................................................................... soc/mediatek/mt8183: use load_blob_file API to load SSPM TEST=build pass Signed-off-by: TingHan.Shen <tinghan.shen(a)mediatek.com> Change-Id: Ia72c852caad0cf63f00b5a461f89725e4d7241c2 --- M src/soc/mediatek/mt8183/sspm.c 1 file changed, 4 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47798/1 diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index efcf545..9287321 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -1,29 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/barrier.h> -#include <cbfs.h> -#include <console/console.h> #include <device/mmio.h> +#include <soc/mtlib_common.h> #include <soc/sspm.h> -#include <string.h> - -#define BUF_SIZE (64 * KiB) -static uint8_t sspm_bin[BUF_SIZE] __aligned(8); void sspm_init(void) { - const char *file_name = "sspm.bin"; - size_t fw_size = cbfs_boot_load_file(file_name, - sspm_bin, - sizeof(sspm_bin), - CBFS_TYPE_RAW); - - if (fw_size == 0) - die("SSPM file :sspm.bin not found."); - - memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); - /* Memory barrier to ensure that all fw code is loaded - before we release the reset pin. */ - mb(); - write32(&mt8183_sspm->sw_rstn, 0x1); + const char *sspm_file_name = "sspm.bin"; + if (load_blob_file(sspm_file_name, SSPM_SRAM_BASE) == CB_SUCCESS) + write32(&mt8183_sspm->sw_rstn, 0x1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72c852caad0cf63f00b5a461f89725e4d7241c2 Gerrit-Change-Number: 47798 Gerrit-PatchSet: 1 Gerrit-Owner: tinghan shen <tinghan.shen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK: soc/mediatek/mt8192: Support sspm uart
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Erin Lo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47349 to review the following change. Change subject: HACK: soc/mediatek/mt8192: Support sspm uart ...................................................................... HACK: soc/mediatek/mt8192: Support sspm uart After rework asurada board, switch gpio pinmux Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> Change-Id: Ief8410aee7e06c32040fbae87e2360cd0bb9d441 --- M src/soc/mediatek/mt8192/sspm.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47349/1 diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c index c9ed840..3fcc1e2 100755 --- a/src/soc/mediatek/mt8192/sspm.c +++ b/src/soc/mediatek/mt8192/sspm.c @@ -3,6 +3,7 @@ #include <arch/barrier.h> #include <cbfs.h> #include <console/console.h> +#include <soc/gpio.h> #include <device/mmio.h> #include <soc/sspm.h> #include <string.h> @@ -24,6 +25,10 @@ memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); /* Memory barrier to ensure that all fw code is loaded before we release the reset pin. */ + + gpio_set_mode(GPIO(URXD1), 4); + gpio_set_mode(GPIO(UTXD1), 4); + mb(); write32(&mt8192_sspm->sw_rstn, 0x1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8410aee7e06c32040fbae87e2360cd0bb9d441 Gerrit-Change-Number: 47349 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: enlarge sspm buffer size
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Ben Ho, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47348 to review the following change. Change subject: enlarge sspm buffer size ...................................................................... enlarge sspm buffer size Signed-off-by: Ben Ho <Ben.Ho(a)mediatek.com> Change-Id: Id470399dd2167f67b3e80fe5f268f1cd0cb8fda2 --- M src/soc/mediatek/mt8192/sspm.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47348/1 diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c old mode 100644 new mode 100755 index 7f66535..c9ed840 --- a/src/soc/mediatek/mt8192/sspm.c +++ b/src/soc/mediatek/mt8192/sspm.c @@ -7,7 +7,7 @@ #include <soc/sspm.h> #include <string.h> -#define BUF_SIZE (64 * KiB) +#define BUF_SIZE (192 * KiB) static uint8_t sspm_bin[BUF_SIZE] __aligned(8); void sspm_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/47348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id470399dd2167f67b3e80fe5f268f1cd0cb8fda2 Gerrit-Change-Number: 47348 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Ben Ho <Ben.Ho(a)mediatek.com> Gerrit-MessageType: newchange

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