coreboot-gerrit December 2020

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Change in coreboot[master]: cbfs: Add more error messages for lookup
by Julius Werner (Code Review) 04 Dec '20

04 Dec '20

Hello Furquan Shaikh, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48278 to review the following change. Change subject: cbfs: Add more error messages for lookup ...................................................................... cbfs: Add more error messages for lookup The new CBFS stack will log messages for found files but leaves error messages up to the caller. This patch adds appropriate generic error messages to cbfs_lookup(), matching the behavior of the old CBFS stack for not found files. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I8cf44026accc03c466105d06683027caf1693ff0 --- M src/lib/cbfs.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48278/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 5df1d8b..d66c5d6 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -52,8 +52,17 @@ name); return cbfs_boot_lookup(name, true, mdata, rdev); } - if (err) + if (err) { + if (err == CB_CBFS_NOT_FOUND) + printk(BIOS_WARNING, "CBFS: '%s' not found.\n", name); + else if (err == CB_CBFS_HASH_MISMATCH) + die("CBFS FATAL ERROR: metadata hash mismatch!\n"); + else + printk(BIOS_ERR, + "CBFS ERROR: error %d when looking up '%s'\n", + err, name); return err; + } if (rdev_chain(rdev, &cbd->rdev, data_offset, be32toh(mdata->h.len))) return CB_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/48278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cf44026accc03c466105d06683027caf1693ff0 Gerrit-Change-Number: 48278 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add additional SD cards to device list
by Duncan Laurie (Code Review) 04 Dec '20

04 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48159 ) Change subject: mb/google/volteer: Add additional SD cards to device list ...................................................................... mb/google/volteer: Add additional SD cards to device list The initial commit only focused on GL9755S and RTS5261, but there were recently other cards added to the fw_config and those also need to be added to the probe lists. BUG=b:173207454 TEST=abuild google/volteer Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48159/1 diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 5080d9b..c444b4c 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -66,7 +66,7 @@ PAD_NC(GPP_R7, NONE), }; -static const struct pad_config sd_gl9755s_pads[] = { +static const struct pad_config sd_power_enable_pads[] = { PAD_CFG_GPO(GPP_D16, 1, DEEP), }; @@ -99,9 +99,12 @@ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } - if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) { - printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n"); - gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads)); + if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_RTS5227S)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_GL9750)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_OZ711LV2LN))) { + printk(BIOS_INFO, "Configure GPIOs for SD power enable.\n"); + gpio_configure_pads(sd_power_enable_pads, ARRAY_SIZE(sd_power_enable_pads)); } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index bc1febb..455b9ab 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -39,7 +39,7 @@ option SD_GL9755S 1 option SD_RTS5261 2 option SD_RTS5227S 3 - option SD_L9750 4 + option SD_GL9750 4 option SD_OZ711LV2LN 5 end field KB_LAYOUT 20 21 @@ -459,12 +459,18 @@ device ref pcie_rp8 on probe DB_SD SD_GL9755S probe DB_SD SD_RTS5261 + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" register "srcclk_pin" = "3" device generic 0 on probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN end end chip soc/intel/common/block/pcie/rtd3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82 Gerrit-Change-Number: 48159 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Add $(xcompile) to specify where to write xcompile
by Raul Rangel (Code Review) 04 Dec '20

04 Dec '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28101 ) Change subject: Makefile: Add $(xcompile) to specify where to write xcompile ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/c/coreboot/+/28101/6/src/soc/nvidia/tegra124/lp… File src/soc/nvidia/tegra124/lp0/Makefile: https://review.coreboot.org/c/coreboot/+/28101/6/src/soc/nvidia/tegra124/lp… PS6, Line 16: xcompile > since this file doesn't respect the $(obj) variable I was hesitant to write anything into the src di […] I want to leave the build cleanup for another day. https://review.coreboot.org/c/coreboot/+/28101/6/util/testing/Makefile.inc File util/testing/Makefile.inc: https://review.coreboot.org/c/coreboot/+/28101/6/util/testing/Makefile.inc@… PS6, Line 94: > If the nvidia makefiles create .xcompile on their own, this is not needed. Same -- To view, visit https://review.coreboot.org/c/coreboot/+/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)google.com> Gerrit-Comment-Date: Fri, 04 Dec 2020 22:27:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile: Add $(xcompile) to specify where to write xcompile
by Raul Rangel (Code Review) 04 Dec '20

04 Dec '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28101 ) Change subject: Makefile: Add $(xcompile) to specify where to write xcompile ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/28101/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/28101/6//COMMIT_MSG@21 PS6, Line 21: a > an Done -- To view, visit https://review.coreboot.org/c/coreboot/+/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)google.com> Gerrit-Comment-Date: Fri, 04 Dec 2020 22:23:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile: Add $(xcompile) to specify where to write xcompile
by Raul Rangel (Code Review) 04 Dec '20

04 Dec '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Stefan Reinauer, Paul Menzel, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28101 to look at the new patch set (#11). Change subject: Makefile: Add $(xcompile) to specify where to write xcompile ...................................................................... Makefile: Add $(xcompile) to specify where to write xcompile This file was being written to the root src directory. It is the only file being written to src during a normal build, while all others are being written to $(obj). I added a new variable to allow specifying the xcompile path. This allows generating a single file if building multiple boards. I also moved the default location into $(obj) so we don't pollute the src directory by default. I also cleaned up the generation of xcompile by removing the unnecessary eval and NOCOMPILE check. I also left .xcompile in distclean so it cleans up stale files. Since .xcompile is written into $(obj), `make clean` will now remove it. The tegra Makefiles are outside of the normal build process, so I just updated those Makefiles to point to the default xcompile location of a normal build. The what-jenkins-does target had to be updated to support these special targets. We generate an xcompile specifically for these targets and pass it into the Makefile. Ideally we should get these targets added to the main build. BUG=b:112267918 TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does` Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 --- M Makefile M Makefile.inc M src/soc/nvidia/tegra124/lp0/Makefile M src/soc/nvidia/tegra210/lp0/Makefile M util/abuild/abuild M util/crossgcc/Makefile.inc M util/docker/Makefile M util/testing/Makefile.inc 8 files changed, 29 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28101/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Raul Rangel <rrangel(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller
by Felix Held (Code Review) 04 Dec '20

04 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48270 ) Change subject: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller ...................................................................... soc/amd/picassso/acpi: increase MMIO region size of GPIO controller The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256 bytes each, so increase the reserved size to match the hardware. Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/acpi/sb_fch.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48270/1 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 6cbfc5f..0401313 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -34,7 +34,7 @@ ActiveLow, Exclusive, , , IRQR) { 0 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, 0xFED81500, 0x400) } CreateDWordField (Local0, IRQR._INT, IRQN) If (PMOD) { @@ -44,7 +44,7 @@ } If (IRQN == 0x1f) { Return (ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, 0xFED81500, 0x400) }) } Else { Return (Local0) -- To view, visit https://review.coreboot.org/c/coreboot/+/48270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556 Gerrit-Change-Number: 48270 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Initiate device tree
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48139 ) Change subject: mb/google/brya: Initiate device tree ...................................................................... mb/google/brya: Initiate device tree Initiate device tree based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/48139/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index fbd7d72..e01c4ff 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -2,4 +2,42 @@ device cpu_cluster 0 on device lapic 0 on end end + + device domain 0 on + device ref igpu on end + device ref dptf on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_dma0 on end + device ref tbt_dma1 on end + device ref gna on end + device ref north_xhci on end + device ref cnvi_bt on end + device ref south_xhci on end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end #USB3-1 Type A + device ref pcie_rp4 on end #USB3-4 WWAN + device ref pcie_rp5 on end #PCIE5 WLAN + device ref pcie_rp6 on end #PCIE6 WWAN + device ref pcie_rp8 on end #PCIE8 SD card + device ref pcie_rp9 on end #PCIE9-12 SSD + device ref uart0 on end + device ref gspi0 on end + device ref gspi1 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd Gerrit-Change-Number: 48139 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Align chipset.cb with pci_devs.h
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48153 ) Change subject: soc/intel/alderlake: Align chipset.cb with pci_devs.h ...................................................................... soc/intel/alderlake: Align chipset.cb with pci_devs.h Refer pci_devs.h naming to align chipset.cb. Correct thc0, thc1 and add cnvi_bt. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 --- M src/soc/intel/alderlake/chipset.cb 1 file changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/48153/1 diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index ff81560..de880e3 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -13,18 +13,19 @@ device pci 08.0 alias gna off end device pci 09.0 alias north_tracehub off end device pci 0a.0 alias crashlog off end - device pci 0d.0 alias north_xhci off end - device pci 0d.1 alias north_xdci off end - device pci 0d.2 alias tbt_dma0 off end - device pci 0d.3 alias tbt_dma1 off end + device pci 0d.0 alias tcss_xhci off end + device pci 0d.1 alias tcss_xdci off end + device pci 0d.2 alias tcss_dma0 off end + device pci 0d.3 alias tcss_dma1 off end device pci 0e.0 alias vmd off end - device pci 10.6 alias thc0 off end - device pci 10.7 alias thc1 off end + device pci 10.0 alias thc0 off end + device pci 10.1 alias thc1 off end + device pci 10.2 alias cnvi_bt off end device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end - device pci 14.0 alias south_xhci off end - device pci 14.1 alias south_xdci off end + device pci 14.0 alias xhci off end + device pci 14.1 alias usb_otg off end device pci 14.2 alias shared_sram off end device pci 14.3 alias cnvi_wifi off end device pci 15.0 alias i2c0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/48153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 Gerrit-Change-Number: 48153 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya:Add EC smihandler
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48115 ) Change subject: mb/google/brya:Add EC smihandler ...................................................................... mb/google/brya:Add EC smihandler Add implementation of EC smihandler BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 --- M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/smihandler.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/48115/1 diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index ba81ff5..6f73181 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -10,6 +10,8 @@ ramstage-y += mainboard.c ramstage-y += ec.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/baseboard diff --git a/src/mainboard/google/brya/smihandler.c b/src/mainboard/google/brya/smihandler.c new file mode 100644 index 0000000..717facff --- /dev/null +++ b/src/mainboard/google/brya/smihandler.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> +#include <elog.h> +#include <intelblocks/smihandler.h> +#include <variant/ec.h> + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ + /* TODO: Process SMI events from GPI */ +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 Gerrit-Change-Number: 48115 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable EC
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48114 ) Change subject: mb/google/brya: Enable EC ...................................................................... mb/google/brya: Enable EC Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Makefile.inc M src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/dsdt.asl A src/mainboard/google/brya/ec.c M src/mainboard/google/brya/mainboard.c A src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/brya/variants/brya0/include/variant/ec.h 9 files changed, 122 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/48114/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1d29f90..89c09ae 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,8 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_ROMSIZE_KB_32768 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS @@ -15,6 +17,8 @@ config CHROMEOS bool default y + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH config DEVICETREE diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index 3735e20..ba81ff5 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -8,6 +8,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += ec.c VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index e222ca2..b6f747b 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -17,18 +17,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_lid_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 0; -} - int get_write_protect_state(void) { /* No write protect */ diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 5930430..50dca76 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> +#include <variant/ec.h> DefinitionBlock( "dsdt.aml", @@ -29,4 +30,13 @@ /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } } diff --git a/src/mainboard/google/brya/ec.c b/src/mainboard/google/brya/ec.c new file mode 100644 index 0000000..6d0c426 --- /dev/null +++ b/src/mainboard/google/brya/ec.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 4a56f97..f4758cf 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) @@ -19,8 +20,14 @@ return current; } +static void mainboard_dev_init(struct device *dev) +{ + mainboard_ec_init(); +} + static void mainboard_enable(struct device *dev) { + dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..09906d9 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. Key press + * 4. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* + * ACPI related definitions for ASL code. + */ +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index a708db1..6f41718 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -6,4 +6,9 @@ #include <soc/gpe.h> #include <soc/gpio.h> +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/brya0/include/variant/ec.h b/src/mainboard/google/brya/variants/brya0/include/variant/ec.h new file mode 100644 index 0000000..4fc0622 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif /* MAINBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Gerrit-Change-Number: 48114 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020