coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

1 participants
3168 discussions

Change in coreboot[master]: soc/intel/jasperlake: Fill software noise mitigation related UPDs
by Maulik V Vaghela (Code Review) 05 Dec '20

05 Dec '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47879 ) Change subject: soc/intel/jasperlake: Fill software noise mitigation related UPDs ...................................................................... soc/intel/jasperlake: Fill software noise mitigation related UPDs Purpose of this patch is to expose and fill software noise mitigation related parameters from coreboot so that we can fine tune noise mitigation This is work in progress patch and final patchset will allow values to be filled from devietree once values are finalized BUG=NONE BRANCH=NONE TEST=code compiles and UPDs are updated Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47879/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 92c35c6..a76bea3 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -236,6 +236,25 @@ config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, config->PchPmPwrCycDur); + /* Disable Fast slew rate for Deeper C states */ + /* Note that each index is for specific VR */ + params->FastPkgCRampDisable[0] = 0x00; + params->FastPkgCRampDisable[1] = 0x00; + params->FastPkgCRampDisable[2] = 0x00; + params->FastPkgCRampDisable[3] = 0x00; + params->FastPkgCRampDisable[4] = 0x00; + + params->SlowSlewRate[0] = 0x00; + params->SlowSlewRate[1] = 0x00; + params->SlowSlewRate[2] = 0x00; + params->SlowSlewRate[3] = 0x00; + params->SlowSlewRate[4] = 0x00; + + params->AcousticNoiseMitigation = 0x00; + params->PreWake = 0x00; + params->RampUp = 0x00; + params->RampDown = 0x00; + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02 Gerrit-Change-Number: 47879 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/xeon_sp: Don't use common block acpi.h
by Marc Jones (Code Review) 05 Dec '20

05 Dec '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48254 ) Change subject: soc/intel/xeon_sp: Don't use common block acpi.h ...................................................................... soc/intel/xeon_sp: Don't use common block acpi.h Don't use the common block acpi.h when we aren't using the COMMON_ACPI config. Fixes a dependency build issue in an upcoming commit. Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 5 files changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48254/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index fb4cd78..4fe8b20 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -4,12 +4,12 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <intelblocks/acpi.h> #include <device/pci.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/cpu.h> +#include <soc/intel/common/acpi.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_util.h> diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 599ccff..8e73008 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -8,7 +8,7 @@ #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> -#include <intelblocks/acpi.h> +#include <intelblocks/cpulib.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 60d6321..2f22c62 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -19,8 +19,13 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); - - +unsigned long southbridge_write_acpi_tables(const struct device *device, + unsigned long current, struct acpi_rsdp *rsdp); +uint32_t soc_read_sci_irq_select(void); +int soc_madt_sci_irq_polarity(int sci); +void soc_power_states_generation(int core, int cores_per_package); +acpi_tstate_t *soc_get_tss_table(int *entries); +acpi_cstate_t *soc_get_cstate_map(size_t *entries); int calculate_power(int tdp, int p1_ratio, int ratio); void uncore_inject_dsdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index cb7ae40..19c3921 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -5,7 +5,6 @@ #include <cbmem.h> #include <device/mmio.h> #include <device/pci.h> -#include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 3ac46ff..53b9d27 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -8,7 +8,6 @@ #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> -#include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d Gerrit-Change-Number: 48254 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Patrick Rudolph (Code Review) 05 Dec '20

05 Dec '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Patch Set 3: Code-Review-1 (1 comment) https://review.coreboot.org/c/coreboot/+/48293/3/src/mainboard/prodrive/her… File src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb: https://review.coreboot.org/c/coreboot/+/48293/3/src/mainboard/prodrive/her… PS3, Line 177: device pci 00.0 on end this device doesn't exist -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Dec 2020 06:13:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block/usb4: Add the PCI ID for ADL
by V Sowmya (Code Review) 05 Dec '20

05 Dec '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48271 ) Change subject: soc/intel/common/block/usb4: Add the PCI ID for ADL ...................................................................... soc/intel/common/block/usb4: Add the PCI ID for ADL This patch adds the PCI device ID for Alderlake CPU xHCI. Change-Id: I4074a81aa9be2ef3a0956da08bece32a613415ab Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/common/block/usb4/xhci.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48271/1 diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index 4fe60dd..d4fb3e2 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -27,6 +27,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI, + PCI_DEVICE_ID_INTEL_ADP_TCSS_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4074a81aa9be2ef3a0956da08bece32a613415ab Gerrit-Change-Number: 48271 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: device/pci_id: Add TCSS PCI IDs for Alderlake
by V Sowmya (Code Review) 05 Dec '20

05 Dec '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48242 ) Change subject: device/pci_id: Add TCSS PCI IDs for Alderlake ...................................................................... device/pci_id: Add TCSS PCI IDs for Alderlake Add the PCI IDs for Alderlake TCSS, * USB xHCI * USB xDCI * TBT DMA * TBT PCIe Change-Id: I28bb310c7b031d2766c9e03dbcbe1c79901a7d87 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/48242/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 51c0abf..9e6ac64 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3871,6 +3871,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded #define PCI_DEVICE_ID_INTEL_ADP_P_XHCI 0x51ed #define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0 +#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XHCI 0x461e /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3984,6 +3985,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee #define PCI_DEVICE_ID_INTEL_ADP_P_XDCI 0x51ee #define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 +#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XDCI 0x460e /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35 @@ -4008,8 +4010,14 @@ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP0 0x466e +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP1 0x463f +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP2 0x462f +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP3 0x461f #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d +#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA0 0x463e +#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA1 0x466d /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 -- To view, visit https://review.coreboot.org/c/coreboot/+/48242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bb310c7b031d2766c9e03dbcbe1c79901a7d87 Gerrit-Change-Number: 48242 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/dedede: Set the GPIO to EDGE_BOTH trigger for SD card CD pin
by Kaiyen Chang (Code Review) 05 Dec '20

05 Dec '20

Hello Kaiyen Chang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48303 to review the following change. Change subject: mb/google/dedede: Set the GPIO to EDGE_BOTH trigger for SD card CD pin ...................................................................... mb/google/dedede: Set the GPIO to EDGE_BOTH trigger for SD card CD pin The default setting of LEVEL/EDGE of GPIO is zero, which is LEVEL trigger. So we need to set the GPIO to EDGE_BOTH trigger for SD card CD pin in advance in coreboot to avoid the probabilistic interrupt storm occuring during the period that kernel is configuring the GPIO for SD card CD pin. BUG=b:174336541 TEST=Run 1500 reboot iterations successfully Signed-off-by: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com> Change-Id: I4782c7efd9ab107e4894257b6e042f7477d90fac --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48303/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 1d8d21d..39d35f5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -381,7 +381,7 @@ PAD_NC(GPD10, NONE), /* SD card detect virtual GPIO */ - PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, PLTRST), + PAD_CFG_GPI_GPIO_DRIVER_EDGE_BOTH(VGPIO_39, NONE, PLTRST), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4782c7efd9ab107e4894257b6e042f7477d90fac Gerrit-Change-Number: 48303 Gerrit-PatchSet: 1 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Reviewer: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/intel/cannonlake: Add chipset devicetree
by Felix Singer (Code Review) 05 Dec '20

05 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46315 ) Change subject: soc/intel/cannonlake: Add chipset devicetree ...................................................................... Patch Set 10: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia43a9d490dc336b4470f4ce4f199870f0db0c625 Gerrit-Change-Number: 46315 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 05 Dec 2020 01:47:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Michael Niewöhner (Code Review) 05 Dec '20

05 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Patch Set 3: Code-Review+1 LGTM but should be tested -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Dec 2020 01:47:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Felix Singer (Code Review) 05 Dec '20

05 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Dec 2020 01:47:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer: Reorganize FMAP
by Tim Wawrzynczak (Code Review) 05 Dec '20

05 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48187 ) Change subject: mb/google/volteer: Reorganize FMAP ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Gerrit-Change-Number: 48187 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Dec 2020 01:38:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2020