coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/brya: Set UART console
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48070 ) Change subject: mb/google/brya: Set UART console ...................................................................... mb/google/brya: Set UART console Follow latest schematic UART_PCH_DBG is UART 0. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 --- M src/mainboard/google/brya/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48070/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e448e18..4348ef5 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -31,4 +31,8 @@ string default "brya0" if BOARD_GOOGLE_BRYA0 +config UART_FOR_CONSOLE + int + default 0 + endif # BOARD_GOOGLE_BASEBOARD_BRYA -- To view, visit https://review.coreboot.org/c/coreboot/+/48070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 Gerrit-Change-Number: 48070 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable ACPI and add ACPI table
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48069 ) Change subject: mb/google/brya: Enable ACPI and add ACPI table ...................................................................... mb/google/brya: Enable ACPI and add ACPI table Enable ACPI configuration and add DSDT ACPI table. BUG=b:144768001 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/dsdt.asl M src/mainboard/google/brya/mainboard.c 3 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48069/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 3c08757..e448e18 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SOC_INTEL_ALDERLAKE diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 10d08e2..f15f25e 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -11,4 +11,19 @@ 0x20110725 // OEM revision ) { + /* Some generic macros */ + #include <soc/intel/common/acpi/platform.asl> + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + } + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index d7c3156..27a94dc 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> @@ -11,9 +12,16 @@ gpio_configure_pads(pads, num); } +static unsigned long mainboard_write_acpi_tables( + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) +{ + return current; +} + static void mainboard_enable(struct device *dev) { - /* TODO: Enable mainboard */ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/48069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 Gerrit-Change-Number: 48069 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Coachz: change EN_PP3300_DX_EDP from gpio52 to gpio67
by Bob Moragues (Code Review) 04 Dec '20

04 Dec '20

Hello Bob Moragues, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48224 to review the following change. Change subject: Coachz: change EN_PP3300_DX_EDP from gpio52 to gpio67 ...................................................................... Coachz: change EN_PP3300_DX_EDP from gpio52 to gpio67 Coachz rev1 has changed EN_PP3300_DX_EDP from gpio52 to gpio67. BRANCH=none BUG=b:174123578 TEST=emerge-strongbad coreboot chromeos-bootimage. flash coreboot and boot up normally. Signed-off-by: yuanliding <yuanliding(a)huaqin.corp-partner.google.com> Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf --- M src/mainboard/google/trogdor/board.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48224/1 diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index 4d38378..ebce3b5 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -17,7 +17,8 @@ #define GPIO_BACKLIGHT_ENABLE GPIO(12) #define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) #define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : \ - (CONFIG(BOARD_GOOGLE_COACHZ) ? GPIO(52) : GPIO(30))) + (CONFIG(BOARD_GOOGLE_COACHZ) ? (board_id() == 0 ? GPIO(52) : \ + GPIO(67)) : GPIO(30))) void setup_chromeos_gpios(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/48224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf Gerrit-Change-Number: 48224 Gerrit-PatchSet: 1 Gerrit-Owner: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Felix Singer (Code Review) 04 Dec '20

04 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48304 ) Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Dec 2020 19:26:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48304 ) Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG@9 PS1, Line 9: them > Nit: Does that mean the PEG ports? Maybe write it out. Done https://review.coreboot.org/c/coreboot/+/48304/1//COMMIT_MSG@13 PS1, Line 13: Test: powertop on X11SSM-F shows SoC in PC8 instead of just PC3 > Wow. Very nice! Maybe mention if the vendor firmware does that too. I'm not sure, iirc I got to PC5 only or so on vendor; if you insist, I can test it, but not sure if that helps anything -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Dec 2020 17:49:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48304 to look at the new patch set (#2). Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... soc/intel/skl: set PEG port state to auto Setting PegXEnable to 1, statically enables the PEG ports, which blocks the SoC from going to deeper PC states. Instead, set the state to "auto" (2), so the port gets disabled, when no device was detected. Test: powertop on X11SSM-F shows SoC in PC8 instead of just PC3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I3933a219b77d7234af273217df031cf627b4071f --- M src/soc/intel/skylake/romstage/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48304/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 04 Dec '20

04 Dec '20

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47892/3/Documentation/mainboard/sy… File Documentation/mainboard/system76/oryp5.md: https://review.coreboot.org/c/coreboot/+/47892/3/Documentation/mainboard/sy… PS3, Line 72: > Please remove blank lines at the end of the file. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 04 Dec 2020 17:35:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 04 Dec '20

04 Dec '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Jeremy Soller, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47892 to look at the new patch set (#4). Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... mb/system76/oryp5: Add System76 Oryx Pro 5 Tested with TianoCore payload. Not working: - Discrete/Hybrid graphics - Internal speakers Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp5.md A configs/config.system76_oryp5 A src/mainboard/system76/oryp5/Kconfig A src/mainboard/system76/oryp5/Kconfig.name A src/mainboard/system76/oryp5/Makefile.inc A src/mainboard/system76/oryp5/acpi/gpe.asl A src/mainboard/system76/oryp5/acpi/mainboard.asl A src/mainboard/system76/oryp5/acpi/sleep.asl A src/mainboard/system76/oryp5/board_info.txt A src/mainboard/system76/oryp5/bootblock.c A src/mainboard/system76/oryp5/data.vbt A src/mainboard/system76/oryp5/devicetree.cb A src/mainboard/system76/oryp5/dsdt.asl A src/mainboard/system76/oryp5/gpio.c A src/mainboard/system76/oryp5/gpio_early.c A src/mainboard/system76/oryp5/hda_verb.c A src/mainboard/system76/oryp5/include/mainboard/gpio.h A src/mainboard/system76/oryp5/ramstage.c A src/mainboard/system76/oryp5/romstage.c 20 files changed, 834 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/47892/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm_module_loaderv2: Fix compiling for x86_64
by Arthur Heymans (Code Review) 04 Dec '20

04 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48263 ) Change subject: cpu/x86/smm_module_loaderv2: Fix compiling for x86_64 ...................................................................... cpu/x86/smm_module_loaderv2: Fix compiling for x86_64 Change-Id: I9288ede88f822ff78dd9cb91020451dc935203a0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loaderv2.c M src/include/cpu/x86/smm.h 2 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48263/1 diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index 14ed9b8..873e800 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -221,7 +221,7 @@ */ static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus, - unsigned int stack_top, const struct smm_loader_params *params) + uintptr_t stack_top, const struct smm_loader_params *params) { unsigned int i; unsigned int size; @@ -235,7 +235,7 @@ if (cpus[num_cpus - 1].smbase + params->smm_main_entry_offset < stack_top) { printk(BIOS_ERR, "%s: stack encroachment\n", __func__); - printk(BIOS_ERR, "%s: smbase %zx, stack_top %x\n", + printk(BIOS_ERR, "%s: smbase %zx, stack_top %lx\n", __func__, cpus[num_cpus].smbase, stack_top); return 0; } @@ -245,7 +245,7 @@ return 0; } - printk(BIOS_INFO, "%s: smbase %zx, stack_top %x\n", + printk(BIOS_INFO, "%s: smbase %zx, stack_top %lx\n", __func__, cpus[num_cpus-1].smbase, stack_top); /* start at 1, the first CPU stub code is already there */ @@ -311,9 +311,9 @@ * sets up the stack, and then jumps to common SMI handler */ if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { - rc = smm_place_entry_code((unsigned int)base, - params->num_concurrent_save_states, - (unsigned int)params->stack_top, params); + rc = smm_place_entry_code((uintptr_t)base, + params->num_concurrent_save_states, + (uintptr_t)params->stack_top, params); } return rc; } @@ -384,7 +384,7 @@ /* The save state size encroached over the first SMM entry point. */ if (size <= params->smm_main_entry_offset) { printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__); - printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %x\n", + printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", __func__, size, params->smm_main_entry_offset); return -1; } diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 6cf6f82..6dfe08d 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -150,10 +150,10 @@ /* The following are only used by X86_SMM_LOADER_VERSION2 */ #if CONFIG(X86_SMM_LOADER_VERSION2) - unsigned int smm_entry; - unsigned int smm_main_entry_offset; - unsigned int smram_start; - unsigned int smram_end; + uintptr_t smm_entry; + uintptr_t smm_main_entry_offset; + uintptr_t smram_start; + uintptr_t smram_end; #endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9288ede88f822ff78dd9cb91020451dc935203a0 Gerrit-Change-Number: 48263 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Furquan Shaikh (Code Review) 04 Dec '20

04 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48304 ) Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Dec 2020 17:20:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020