coreboot-gerrit December 2020

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Change in coreboot[master]: soc/mediatek/mt8192: Init SSPM
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Erin Lo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47347 to review the following change. Change subject: soc/mediatek/mt8192: Init SSPM ...................................................................... soc/mediatek/mt8192: Init SSPM Load SSPM firmware and boot up SSPM. Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> Change-Id: I051478e8bac9f48b9639ee55157ec539fe89f67c --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/soc.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47347/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 22674ca..1ba67a6 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -75,6 +75,11 @@ spm_firmware.bin-type := raw spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += sspm.bin +sspm.bin-file := $(MT8192_BLOB_DIR)/sspm.bin +sspm.bin-type := raw +sspm.bin-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += mcupm.bin mcupm.bin-file := $(MT8192_BLOB_DIR)/mcupm.bin mcupm.bin-type := raw diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 5a2fa37..883f4dc 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -5,6 +5,7 @@ #include <soc/emi.h> #include <soc/mcupm.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> @@ -18,6 +19,7 @@ mtk_mmu_disable_l2c_sram(); dapc_init(); mcupm_init(); + sspm_init(); ufs_disable_refclk(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I051478e8bac9f48b9639ee55157ec539fe89f67c Gerrit-Change-Number: 47347 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: add rtc MT6359P driver
by Roger Lu (Code Review) 04 Dec '20

04 Dec '20

Hello Roger Lu, Yuchen Huang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46877 to review the following change. Change subject: soc/mediatek/mt8192: add rtc MT6359P driver ...................................................................... soc/mediatek/mt8192: add rtc MT6359P driver fix rtc for boot reason check TEST=boot asurada Signed-off-by: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Change-Id: I86b5c1b8d8ccedbb51bbc6e4c9d490c893fb4506 --- M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8192/include/soc/rtc.h M src/soc/mediatek/mt8192/rtc.c 3 files changed, 71 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46877/1 diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index d0b90f7..5ac19eb 100755 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -141,9 +141,6 @@ rtc_info("con=%x, pwrkey1=%x, pwrkey2=%x\n", con, pwrky1, pwrky2); - if (con & RTC_CON_LPSTA_RAW) - return RTC_STATE_INIT; - if (!rtc_busy_wait()) return RTC_STATE_RECOVER; @@ -168,9 +165,11 @@ rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_write_trigger(); rtc_osc_init(); + rtc_info("RTC_STATE_REBOOT\n"); break; case RTC_STATE_RECOVER: rtc_init(1); + rtc_info("RTC_STATE_RECOVER\n"); break; case RTC_STATE_INIT: default: diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h index b1be85c..bad7c68 100755 --- a/src/soc/mediatek/mt8192/include/soc/rtc.h +++ b/src/soc/mediatek/mt8192/include/soc/rtc.h @@ -108,10 +108,18 @@ RTC_EMBCK_SRC_SEL = 1U << 8, RTC_EMBCK_SEL_OPTION = 1U << 9, RTC_GPS_CKOUT_EN = 1U << 10, + RTC_EOSC32_VCT_EN = 1U << 11, + RTC_EOSC32_CHOP_EN = 1U << 12, + RTC_GP_OSC32_CON = 2U << 13, /* Keep RG_EOSC_RSV[0] to low for lower leakage current hw design change */ RTC_REG_XOSC32_ENB = 1U << 15 }; enum { + OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | RTC_EOSC32_VCT_EN |\ + RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION | RTC_EMB_K_EOSC32_MODE +}; + +enum { RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, RTC_LPD_OPT_EOSC_LPD = 1U << 13, RTC_LPD_OPT_XOSC_LPD = 2U << 13, @@ -142,6 +150,15 @@ PMIC_RG_FQMTR_CK_PDN_SHIFT = 11 }; +enum { + PMIC_RG_BANK_FQMTR_RST = 0x522 +}; + +enum { + PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4, + PMIC_RG_BANK_FQMTR_RST_SHIFT = 6 +}; + /* PMIC DCXO Register Definition */ enum { PMIC_RG_DCXO_CW00 = 0x0788, @@ -208,6 +225,12 @@ RTC_TC_MTH_MASK = 0xf }; +enum { + RTC_K_EOSC_RSV_0 = 1 << 8, + RTC_K_EOSC_RSV_1 = 1 << 9, + RTC_K_EOSC_RSV_2 = 1 << 10 +}; + int rtc_read(u16 addr, u16 *rdata); int rtc_write(u16 addr, u16 wdata); void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift); diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c index a8e28b5..f02c633 100755 --- a/src/soc/mediatek/mt8192/rtc.c +++ b/src/soc/mediatek/mt8192/rtc.c @@ -57,15 +57,12 @@ } u16 bbpu, con, osc32con, sec; - rtc_read(RTC_BBPU, &bbpu); rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_write_trigger(); rtc_read(RTC_OSC32CON, &osc32con); - osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK - | RTC_GPS_CKOUT_EN); - osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB - | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; + osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK); + osc32con |= (OSC32CON_ANALOG_SETTING | RTC_REG_XOSC32_ENB); if (!rtc_xosc_write(osc32con)) { rtc_info("rtc_xosc_write() failed\n"); @@ -99,7 +96,7 @@ static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) { u16 bbpu, osc32con; - u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; + u16 fqmtr_busy, fqmtr_data, fqmtr_tcksel; struct stopwatch sw; if (val) { @@ -111,32 +108,34 @@ (val & RTC_XOSCCALI_MASK)); } + /* RG_BANK_FQMTR_RST=1, reset FQMTR*/ + rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 1, 1, + PMIC_RG_BANK_FQMTR_RST_SHIFT); + udelay(20); + /* RG_BANK_FQMTR_RST=0, release FQMTR*/ + rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 0, 1, + PMIC_RG_BANK_FQMTR_RST_SHIFT); + /* enable FQMTR clock */ rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, - PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); - rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, PMIC_RG_FQMTR_CK_PDN_SHIFT); - /* FQMTR reset */ - rtc_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); - do { - rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); - rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); - } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY)); - rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); - /* FQMTR normal */ - rtc_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT); + rtc_write_field(PMIC_RG_FQMTR_CON0, 1, 1, + PMIC_RG_FQMTR_DCXO26M_EN_SHIFT); + /* set frequency meter window value (0=1X32K(fixed clock)) */ rtc_write(PMIC_RG_FQMTR_WINSET, window_size); /* enable 26M and set test clock source */ rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); /* enable 26M -> delay 100us -> enable FQMTR */ - udelay(100); + mdelay(1); rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); /* enable FQMTR */ rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); - udelay(100); + mdelay(1); stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); /* FQMTR read until ready */ do { @@ -149,30 +148,35 @@ /* read data should be closed to 26M/32k = 794 */ rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); - rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* disable FQMTR */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); /* disable FQMTR -> delay 100us -> disable 26M */ - udelay(100); + mdelay(1); /* disable 26M */ rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); - rtc_info("input=0x%x, output=%d\n", val, fqmtr_data); + rtc_info("input=%d, output=%d\n", val, fqmtr_data); + /* disable FQMTR clock */ rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, - PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); - rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, PMIC_RG_FQMTR_CK_PDN_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + return fqmtr_data; } /* 32k clock calibration */ static u16 rtc_eosc_cali(void) { - u16 middle, diff1, diff2, cksel; + u16 diff1, diff2, cksel; u16 val = 0; - u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END; + static u16 middle = 0; + static u16 left = RTC_XOSCCALI_START; + static u16 right = RTC_XOSCCALI_END; rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); cksel &= ~PMIC_FQMTR_CKSEL_MASK; @@ -183,16 +187,20 @@ while (left <= right) { middle = (right + left) / 2; - if (middle == left) + if (middle == left) { break; + } /* select 26M as target clock */ val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) { break; - if (val > RTC_FQMTR_HIGH_BASE) + } + if (val > RTC_FQMTR_HIGH_BASE) { right = middle; - else + } + else { left = middle; + } } if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) @@ -212,6 +220,7 @@ else diff2 = RTC_FQMTR_LOW_BASE - val; + rtc_info("left:%d, middle:%d, right: %d\n", left, middle, right); if (diff1 < diff2) return left; else @@ -332,6 +341,7 @@ int rtc_init(u8 recover) { int ret; + u16 year; rtc_info("recovery: %d\n", recover); @@ -347,7 +357,7 @@ goto err; } - //rtc_osc_init(); + rtc_osc_init(); if (recover) mdelay(20); @@ -367,6 +377,11 @@ goto err; } + /* solution1 for EOSC cali*/ + rtc_read(RTC_AL_YEA, &year); + rtc_write(RTC_AL_YEA, (year | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1) & (~RTC_K_EOSC_RSV_2)); + rtc_write_trigger(); + if (!rtc_lpd_init()) { ret = -RTC_STATUS_LPD_INIT_FAIL; goto err; -- To view, visit https://review.coreboot.org/c/coreboot/+/46877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86b5c1b8d8ccedbb51bbc6e4c9d490c893fb4506 Gerrit-Change-Number: 46877 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Lu <roger.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Roger Lu <roger.lu(a)mediatek.com> Gerrit-Reviewer: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Support SSPM
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Erin Lo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47346 to review the following change. Change subject: soc/mediatek/mt8192: Support SSPM ...................................................................... soc/mediatek/mt8192: Support SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> Change-Id: Ie174e8c4f4fc2055b731a3a5ee8d5b49df8af9ac --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/sspm.h A src/soc/mediatek/mt8192/sspm.c 4 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47346/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index f348a20..22674ca 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c +ramstage-y += sspm.c ramstage-y += devapc.c ramstage-y += ufs.c ramstage-y += mcupm.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 43a1bdc..b031b16 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -34,6 +34,8 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + SSPM_SRAM_BASE = IO_PHYS + 0x00400000, + SSPM_CFG_BASE = IO_PHYS + 0x00440000, AUXADC_BASE = IO_PHYS + 0x01001000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, diff --git a/src/soc/mediatek/mt8192/include/soc/sspm.h b/src/soc/mediatek/mt8192/include/soc/sspm.h new file mode 100644 index 0000000..5749fa4 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/sspm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_SSPM_H +#define SOC_MEDIATEK_MT8192_SSPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_sspm_regs { + u32 sw_rstn; +}; +static struct mt8192_sspm_regs *const mt8192_sspm = (void *)SSPM_CFG_BASE; +void sspm_init(void); +#endif /* SOC_MEDIATEK_MT8192_SSPM_H */ diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c new file mode 100644 index 0000000..7f66535 --- /dev/null +++ b/src/soc/mediatek/mt8192/sspm.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/sspm.h> +#include <string.h> + +#define BUF_SIZE (64 * KiB) +static uint8_t sspm_bin[BUF_SIZE] __aligned(8); + +void sspm_init(void) +{ + const char *file_name = "sspm.bin"; + size_t fw_size = cbfs_boot_load_file(file_name, + sspm_bin, + sizeof(sspm_bin), + CBFS_TYPE_RAW); + + if (fw_size == 0) + die("SSPM file :sspm.bin not found."); + + memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8192_sspm->sw_rstn, 0x1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie174e8c4f4fc2055b731a3a5ee8d5b49df8af9ac Gerrit-Change-Number: 47346 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: add maintainers for soc/amd/cezanne and soc/amd/common
by Felix Held (Code Review) 04 Dec '20

04 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48239 ) Change subject: MAINTAINERS: add maintainers for soc/amd/cezanne and soc/amd/common ...................................................................... MAINTAINERS: add maintainers for soc/amd/cezanne and soc/amd/common Change-Id: Ib661fdf27d5cdb6c2b989c7f2acfc8a6e061657c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M MAINTAINERS 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/48239/1 diff --git a/MAINTAINERS b/MAINTAINERS index 880c4aa..14444aa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -551,6 +551,20 @@ # Systems on a Chip ################################################################################ +AMD Cezanne +M: Marshall Dawson <marshalldawson3rd(a)gmail.com> +M: Felix Held <felix-coreboot(a)felixheld.de> +M: Jason Glenesk <jason.glenesk(a)gmail.com> +S: Maintained +F: src/soc/amd/cezanne/ + +AMD common SoC code +M: Marshall Dawson <marshalldawson3rd(a)gmail.com> +M: Felix Held <felix-coreboot(a)felixheld.de> +M: Jason Glenesk <jason.glenesk(a)gmail.com> +S: Maintained +F: src/soc/amd/common/ + AMD Picasso M: Marshall Dawson <marshalldawson3rd(a)gmail.com> M: Felix Held <felix-coreboot(a)felixheld.de> -- To view, visit https://review.coreboot.org/c/coreboot/+/48239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib661fdf27d5cdb6c2b989c7f2acfc8a6e061657c Gerrit-Change-Number: 48239 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputs
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48093 ) Change subject: mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputs ...................................................................... mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputs All four SMI/NMI interrupt inputs have an external pull-up resistor and get triggered by pulling the line low. Thus, correct the trigger to active-low. Also document the signals by adding appropriate comments. The pads' connections have been determined by dissecting a dead board. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48093 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c index dc41573..335171e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c @@ -80,13 +80,13 @@ PAD_NC(GPP_C19, NONE), PAD_NC(GPP_C20, NONE), PAD_NC(GPP_C21, NONE), - PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_SMI_LOW(GPP_C22, UP_20K, DEEP, EDGE_SINGLE), /* BMC SMI# */ PAD_NC(GPP_C23, NONE), /* GPIO Group GPP_D */ PAD_NC(GPP_D0, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), - PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* BMC NMI# */ PAD_NC(GPP_D3, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), PAD_NC(GPP_D5, NONE), @@ -116,7 +116,7 @@ PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E4, NONE), PAD_NC(GPP_E5, NONE), - PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, INVERT), /* NMI# (BMC WDT + JF1) */ PAD_NC(GPP_E7, NONE), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), @@ -169,8 +169,8 @@ PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), PAD_NC(GPP_G17, NONE), - PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* BMC NMI# */ + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* BMC SMI# */ PAD_NC(GPP_G20, NONE), PAD_NC(GPP_G21, NONE), PAD_NC(GPP_G22, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/48093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085 Gerrit-Change-Number: 48093 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11ssm-f: drop NMI overrides
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48092 ) Change subject: mb/supermicro/x11ssm-f: drop NMI overrides ...................................................................... mb/supermicro/x11ssm-f: drop NMI overrides Drop the NMI overrides, since NMI now gets configured in gpio common code. Also remove the variant init mechanism, which is unused now. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I02e0c679f9aafe33108320a8dfc62dcb278202ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48092 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/Makefile.inc D src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h M src/mainboard/supermicro/x11-lga1151-series/mainboard.c D src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc D src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c 5 files changed, 0 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index a4ebe46..40afacb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -8,5 +8,3 @@ ramstage-y += mainboard.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - -subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h deleted file mode 100644 index cad75f4..0000000 --- a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BASEBOARD_X11_LGA1151_SERIES_H -#define _BASEBOARD_X11_LGA1151_SERIES_H - -#include <device/device.h> - -void variant_mainboard_init(void *chip_info); - -#endif /* _BASEBOARD_X11_LGA1151_SERIES_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 0f8dbed..b7ea1f2 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -1,20 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <mainboard.h> #include <device/device.h> #include <mainboard/gpio.h> -__weak void variant_mainboard_init(void *chip_info) -{ -} - static void mainboard_chip_init(void *chip_info) { - /* do common init */ mainboard_configure_gpios(); - - /* do variant init */ - variant_mainboard_init(chip_info); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc deleted file mode 100644 index f3c87b2..0000000 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += mainboard.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c deleted file mode 100644 index 75351eb..0000000 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <mainboard.h> -#include <device/device.h> -#include <intelblocks/pcr.h> -#include <soc/pcr_ids.h> - -void variant_mainboard_init(void *chip_info) -{ - // TODO: NMI; is this needed? vendor sets it - pcr_write32(0xae, 0x01e4, 0x00000004); - pcr_write32(0xae, 0x01e8, 0x00000040); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02e0c679f9aafe33108320a8dfc62dcb278202ef Gerrit-Change-Number: 48092 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{skl,cnl}: add NMI_{EN,STS} registers
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48091 ) Change subject: soc/intel/{skl,cnl}: add NMI_{EN,STS} registers ...................................................................... soc/intel/{skl,cnl}: add NMI_{EN,STS} registers Add NMI_EN and NMI_STS registers, so they can be configured for using NMI gpios. References: - CMP-LP: Intel doc# 615146-1.2 - CMP-H: Intel doc# 620855-002 - SPT-H: Intel doc# 332691-003 - SPT-LP: Intel doc# 334659-005 - CNP-H: Intel doc# 337868-002 Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before but now makes the Linux kernel complain about a NMI. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h 6 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 3c70ad9..90efacc 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -76,6 +76,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_ABG", .acpi_path = "\\_SB.PCI0.GPIO", @@ -96,6 +98,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_DFH", .acpi_path = "\\_SB.PCI0.GPIO", @@ -116,6 +120,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", .acpi_path = "\\_SB.PCI0.GPIO", @@ -136,6 +142,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GP_AC", .acpi_path = "\\_SB.PCI0.GPIO", @@ -156,6 +164,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CEJ", .acpi_path = "\\_SB.PCI0.GPIO", diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index 06e344d..a9035ed 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -78,6 +78,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_AB", .acpi_path = "\\_SB.PCI0.GPIO", @@ -98,6 +100,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CDG", .acpi_path = "\\_SB.PCI0.GPIO", @@ -118,6 +122,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", .acpi_path = "\\_SB.PCI0.GPIO", @@ -138,6 +144,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_KHEF", .acpi_path = "\\_SB.PCI0.GPIO", @@ -158,6 +166,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_IJ", .acpi_path = "\\_SB.PCI0.GPIO", diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index e7769b5..c96a67d 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -236,6 +236,8 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x600 #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index bd68b04..4f87459 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -310,6 +310,8 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x600 #endif diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 5519762..1ac9912 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -62,6 +62,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM0", .acpi_path = "\\_SB.PCI0.GPIO", @@ -84,6 +86,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM1", .acpi_path = "\\_SB.PCI0.GPIO", @@ -107,6 +111,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM3", .acpi_path = "\\_SB.PCI0.GPIO", @@ -125,6 +131,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM2", .acpi_path = "\\_SB.PCI0.GPIO", diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 2a5e788..de14bb6 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -216,5 +216,7 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #endif /* _SOC_GPIO_DEFS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598 Gerrit-Change-Number: 48091 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/gpio: add code for NMI enabling
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48090 ) Change subject: soc/intel/common/block/gpio: add code for NMI enabling ...................................................................... soc/intel/common/block/gpio: add code for NMI enabling Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/skylake/acpi.c 4 files changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f0ff898..4efeb88 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -79,6 +79,9 @@ current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + /* NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + return current; } diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 0d21c8a..fb9287c 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -48,6 +48,10 @@ ((group) * sizeof(uint32_t))) #define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \ ((group) * sizeof(uint32_t))) +#define GPI_NMI_STS_OFFSET(comm, group) ((comm)->gpi_nmi_sts_reg_0 + \ + ((group) * sizeof(uint32_t))) +#define GPI_NMI_EN_OFFSET(comm, group) ((comm)->gpi_nmi_en_reg_0 + \ + ((group) * sizeof(uint32_t))) #define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \ ((group) * sizeof(uint32_t))) #define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \ @@ -176,6 +180,35 @@ pcr_or32(comm->port, en_reg, en_value); } +static void gpi_enable_nmi(const struct pad_config *cfg, + const struct pad_community *comm) +{ + uint16_t sts_reg; + uint16_t en_reg; + uint32_t en_value; + int group; + int pin; + + if (((cfg->pad_config[0]) & PAD_CFG0_ROUTE_NMI) != PAD_CFG0_ROUTE_NMI) + return; + + /* Do not configure NMI if the platform doesn't support it */ + if (!comm->gpi_nmi_sts_reg_0 || !comm->gpi_nmi_en_reg_0) + return; + + pin = relative_pad_in_comm(comm, cfg->pad); + group = gpio_group_index(comm, pin); + sts_reg = GPI_NMI_STS_OFFSET(comm, group); + en_reg = GPI_NMI_EN_OFFSET(comm, group); + en_value = gpio_bitmask_within_group(comm, pin); + + /* Write back 1 to reset the sts bit */ + pcr_rmw32(comm->port, sts_reg, en_value, 0); + + /* Set enable bits */ + pcr_or32(comm->port, en_reg, en_value); +} + static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, uint16_t pad_cfg_offset) { @@ -283,6 +316,7 @@ gpio_configure_itss(cfg, comm->port, config_offset); gpio_configure_owner(cfg, comm); gpi_enable_smi(cfg, comm); + gpi_enable_nmi(cfg, comm); } void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 6e2bf1c..173a383 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -111,6 +111,8 @@ uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */ uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */ uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */ + uint16_t gpi_nmi_sts_reg_0; /* offset to GPI NMI STS Reg 0 */ + uint16_t gpi_nmi_en_reg_0; /* offset to GPI NMI EN Reg 0 */ uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */ uint8_t gpi_status_offset; /* specifies offset in struct gpi_status */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 98d9313..0083be5 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -522,6 +522,9 @@ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); + /* NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Gerrit-Change-Number: 48090 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block/gpio: only reset configured SMI instead of all
by Michael Niewöhner (Code Review) 04 Dec '20

04 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48089 ) Change subject: intel/common/block/gpio: only reset configured SMI instead of all ...................................................................... intel/common/block/gpio: only reset configured SMI instead of all Currently, when a SMI GPIO gets configured, the whole status register is get written back and thus, all SMIs get reset. Do it right and reset only the correspondig status bit of the GPIO to be configured. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48089 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d6958b1..0d21c8a 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -154,9 +154,9 @@ static void gpi_enable_smi(const struct pad_config *cfg, const struct pad_community *comm) { - uint32_t value; uint16_t sts_reg; uint16_t en_reg; + uint32_t en_value; int group; int pin; @@ -165,15 +165,15 @@ pin = relative_pad_in_comm(comm, cfg->pad); group = gpio_group_index(comm, pin); - sts_reg = GPI_SMI_STS_OFFSET(comm, group); - value = pcr_read32(comm->port, sts_reg); - /* Write back 1 to reset the sts bits */ - pcr_write32(comm->port, sts_reg, value); + en_reg = GPI_SMI_EN_OFFSET(comm, group); + en_value = gpio_bitmask_within_group(comm, pin); + + /* Write back 1 to reset the sts bit */ + pcr_rmw32(comm->port, sts_reg, en_value, 0); /* Set enable bits */ - en_reg = GPI_SMI_EN_OFFSET(comm, group); - pcr_or32(comm->port, en_reg, gpio_bitmask_within_group(comm, pin)); + pcr_or32(comm->port, en_reg, en_value); } static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, -- To view, visit https://review.coreboot.org/c/coreboot/+/48089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc Gerrit-Change-Number: 48089 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3
by Martin Roth (Code Review) 04 Dec '20

04 Dec '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48255 ) Change subject: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 ...................................................................... mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 This is used as a signal to show the system state. It hadn't been used up to this point as we're not currently using S0i3, but the fingerprint sensor will use it to go into a low power mode, so set it appropriately on Trembyle. Dalboz devices don't use the FPMCU, but set there as well so that the state matches. BUG=b:174695987 TEST=Verify GPIO state in S0 and S3 with the EC BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/48255/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 884862d..a528827 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -30,8 +30,8 @@ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC */ + PAD_GPO(GPIO_10, HIGH), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), /* USI_INT_ODL */ @@ -302,6 +302,8 @@ } static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), /* diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 818c39b..2929c54 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -32,8 +32,8 @@ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC & FPMCU */ + PAD_GPO(GPIO_10, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ @@ -342,6 +342,8 @@ } static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05 Gerrit-Change-Number: 48255 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020