coreboot-gerrit December 2020

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Change in coreboot[master]: [TESTONLY] build with TRACE=y
by Kyösti Mälkki (Code Review) 03 Dec '20

03 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43870 ) Change subject: [TESTONLY] build with TRACE=y ...................................................................... [TESTONLY] build with TRACE=y Change-Id: Iee20e3c1fc31aba704d813f909c39986df3e2c29 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/43870/1 diff --git a/src/Kconfig b/src/Kconfig index a4c2fa6..fb7cd2d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1055,7 +1055,7 @@ config TRACE bool "Trace function calls" - default n + default y help If enabled, every function will print information to console once the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) -- To view, visit https://review.coreboot.org/c/coreboot/+/43870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee20e3c1fc31aba704d813f909c39986df3e2c29 Gerrit-Change-Number: 43870 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/tigerlake: Define and use a Kconfig for no of USB ports.
by Meera Ravindranath (Code Review) 03 Dec '20

03 Dec '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38682 ) Change subject: src/soc/tigerlake: Define and use a Kconfig for no of USB ports. ...................................................................... src/soc/tigerlake: Define and use a Kconfig for no of USB ports. BUG=None BRANCH=None TEST=Compilation for jasper lake board is working Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params_jsl.c M src/soc/intel/tigerlake/fsp_params_tgl.c 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..f50e40e 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -156,6 +156,16 @@ default 3 if SOC_INTEL_JASPERLAKE default 4 if SOC_INTEL_TIGERLAKE +config SOC_INTEL_USB2_DEV_MAX + int + default 8 if SOC_INTEL_JASPERLAKE + default 10 if SOC_INTEL_TIGERLAKE + +config SOC_INTEL_USB3_DEV_MAX + int + default 6 if SOC_INTEL_JASPERLAKE + default 4 if SOC_INTEL_TIGERLAKE + config SOC_INTEL_I2C_DEV_MAX int default 6 diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 8046b2e..d5d623b 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -106,7 +106,7 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* USB configuration */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; @@ -116,7 +116,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..f027ee0 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -89,7 +89,7 @@ params->IomTypeCPortPadCfg[i] = 0x09000000; /* USB */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; @@ -98,7 +98,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Create copano variant
by Zhuohao Lee (Code Review) 03 Dec '20

03 Dec '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48136 ) Change subject: mb/google/volteer: Create copano variant ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef Gerrit-Change-Number: 48136 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Dec 2020 10:30:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S Audio for ADLRVP
by Sathya Prakash M R (Code Review) 03 Dec '20

03 Dec '20

Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48000 ) Change subject: mb/intel/adlrvp: Enable I2S Audio for ADLRVP ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Gerrit-Change-Number: 48000 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Dec 2020 09:27:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Update GPIO configurations according to schematics
by Johnny Lin (Code Review) 03 Dec '20

03 Dec '20

Johnny Lin has uploaded a new patch set (#10) to the change originally created by Jingle Hsu. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Update GPIO configurations according to schematics ...................................................................... mb/ocp/deltalake: Update GPIO configurations according to schematics On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH (C621A) by util/inteltool and generate the header file by util/intelp2m. The DVT and EVT GPIO configurations are the same. The initial value of GPP_B20 (POST complete) should be high, otherwise BIC would get incorrect sensor readings and see events like PCH prochot. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h 1 file changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47229/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 10 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S Audio for ADLRVP
by Meera Ravindranath (Code Review) 03 Dec '20

03 Dec '20

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48000 ) Change subject: mb/intel/adlrvp: Enable I2S Audio for ADLRVP ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/48000/1/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/48000/1/src/mainboard/intel/adlrvp… PS1, Line 17: select DRIVERS_SOUNDWIRE_ALC711 > remove this too Done https://review.coreboot.org/c/coreboot/+/48000/1/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/gpio.c: https://review.coreboot.org/c/coreboot/+/48000/1/src/mainboard/intel/adlrvp… PS1, Line 209: > GPPC_D19 -> NF1 : sorry i noticed this late. please add that too. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/48000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Gerrit-Change-Number: 48000 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Dec 2020 08:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S Audio for ADLRVP
by Meera Ravindranath (Code Review) 03 Dec '20

03 Dec '20

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48000 ) Change subject: mb/intel/adlrvp: Enable I2S Audio for ADLRVP ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/48000/1/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/48000/1/src/mainboard/intel/adlrvp… PS1, Line 145: register "PchHdaAudioLinkSndwEnable[0]" = "1" : register "PchHdaAudioLinkSndwEnable[1]" = "1" > please remove this too for I2S Done https://review.coreboot.org/c/coreboot/+/48000/5/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/48000/5/src/mainboard/intel/adlrvp… PS5, Line 233: end # I2C0 > submit a separate CL, i will review Done https://review.coreboot.org/c/coreboot/+/48000/5/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb: https://review.coreboot.org/c/coreboot/+/48000/5/src/mainboard/intel/adlrvp… PS5, Line 90: device pci 1f.3 on end #Intel Audio > why we need this here ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/48000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Gerrit-Change-Number: 48000 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Dec 2020 08:01:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S Audio for ADLRVP
by Meera Ravindranath (Code Review) 03 Dec '20

03 Dec '20

Hello build bot (Jenkins), Sugnan Prabhu S, Subrata Banik, Sathya Prakash M R, Vamshi Krishna Gopal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48000 to look at the new patch set (#6). Change subject: mb/intel/adlrvp: Enable I2S Audio for ADLRVP ...................................................................... mb/intel/adlrvp: Enable I2S Audio for ADLRVP Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb 3 files changed, 62 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/48000/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/48000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Gerrit-Change-Number: 48000 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S Audio for ADLRVP
by Sathya Prakash M R (Code Review) 03 Dec '20

03 Dec '20

Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48000 ) Change subject: mb/intel/adlrvp: Enable I2S Audio for ADLRVP ...................................................................... Patch Set 5: Code-Review+1 > Patch Set 5: > > on ERB we had HS INT working which is not on RVP. Will wait for verification on that before giving a +1. Now we have HS INT working. I'm good with changes, Note that playback on HS doesnt work - same as ERB. -- To view, visit https://review.coreboot.org/c/coreboot/+/48000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Gerrit-Change-Number: 48000 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Dec 2020 07:33:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0)
by Xi Chen (Code Review) 03 Dec '20

03 Dec '20

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47987 ) Change subject: TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0) ...................................................................... TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0) Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I232e325af5e8ce77a1289e2001900850fadcec21 --- M src/mainboard/google/asurada/sdram_configs.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47987/1 diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c index acefada..6fbc376 100644 --- a/src/mainboard/google/asurada/sdram_configs.c +++ b/src/mainboard/google/asurada/sdram_configs.c @@ -18,10 +18,10 @@ { uint32_t ramcode = ram_code(); - if (ramcode >= ARRAY_SIZE(sdram_configs) || - cbfs_boot_load_file(sdram_configs[ramcode], &params, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params)) + if (ramcode >= ARRAY_SIZE(sdram_configs)) die("Cannot load SDRAM parameter file for RAM code: %#x", ramcode); + // patch for samsung: dram type: 0 + params.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2; return &params; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232e325af5e8ce77a1289e2001900850fadcec21 Gerrit-Change-Number: 47987 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020