coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/brya: Add entry stubs of each stage
by EricR Lai (Code Review) 03 Dec '20

03 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48063 ) Change subject: mb/google/brya: Add entry stubs of each stage ...................................................................... mb/google/brya: Add entry stubs of each stage Add entry point stubs of each stage for Brya. More functionalities will be added later. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57 --- A src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/bootblock.c A src/mainboard/google/brya/mainboard.c A src/mainboard/google/brya/romstage.c A src/mainboard/google/brya/variants/baseboard/include/gpio.h A src/mainboard/google/brya/variants/baseboard/include/variants.h 6 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48063/1 diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc new file mode 100644 index 0000000..1680fd0 --- /dev/null +++ b/src/mainboard/google/brya/Makefile.inc @@ -0,0 +1,8 @@ +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c new file mode 100644 index 0000000..8a7b93a --- /dev/null +++ b/src/mainboard/google/brya/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ + /* TODO: Perform mainboard initialization */ +} diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c new file mode 100644 index 0000000..53425a8 --- /dev/null +++ b/src/mainboard/google/brya/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +static void mainboard_init(void *chip_info) +{ + /* TODO: Perform mainboard initialization */ +} +static void mainboard_enable(struct device *dev) +{ + /* TODO: Enable mainboard */ +} +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c new file mode 100644 index 0000000..412edde --- /dev/null +++ b/src/mainboard/google/brya/romstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/romstage.h> +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* ToDo : Fill FSP-M memory params */ +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/gpio.h new file mode 100644 index 0000000..e2874b6 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/include/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#endif /* __BASEBOARD_GPIO_H__ */ + diff --git a/src/mainboard/google/brya/variants/baseboard/include/variants.h b/src/mainboard/google/brya/variants/baseboard/include/variants.h new file mode 100644 index 0000000..d16d3da --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/include/variants.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> + +#endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57 Gerrit-Change-Number: 48063 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/google/brya: Add flashmap descriptor
by EricR Lai (Code Review) 03 Dec '20

03 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48062 ) Change subject: mb/google/brya: Add flashmap descriptor ...................................................................... mb/google/brya: Add flashmap descriptor BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117 --- M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/chromeos.fmd 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/48062/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index db2252a..2c0e513 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -2,3 +2,4 @@ bool "Brya 0" select BOARD_GOOGLE_BASEBOARD_BRYA select BASEBOARD_BRYA_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd new file mode 100644 index 0000000..64776fe --- /dev/null +++ b/src/mainboard/google/brya/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xb00000 + RW_SECTION_A@0xb00000 0x5e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x32ffc0 + RW_FWID_A@0x33ffc0 0x40 + ME_RW_A(CBFS)@0x340000 0x2a0000 + } + RW_SECTION_B@0x10e0000 0x5e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x32ffc0 + RW_FWID_B@0x33ffc0 0x40 + ME_RW_B(CBFS)@0x340000 0x2a0000 + } + RW_MISC@0x16c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117 Gerrit-Change-Number: 48062 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/asrock/h110m: add libgfxinit support
by Nico Huber (Code Review) 02 Dec '20

02 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39104 ) Change subject: mb/asrock/h110m: add libgfxinit support ...................................................................... Patch Set 15: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG@7 PS10, Line 7: mb/asrock/h110m: add libgfxinit support > I understand, but maybe we should configure ptn3356 bridge somehow? […] It's hard to tell. It might need out-of-band configuration (e.g. via I2C like that ptn3460 driver does) or maybe via DP Aux. Didn't look into the datasheet yet... Marking this as resolved as the original issue was fixed. I think it's ok to merge it as long as it's documented what does(n't) work. https://review.coreboot.org/c/coreboot/+/39104/15/src/mainboard/asrock/h110… File src/mainboard/asrock/h110m/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/39104/15/src/mainboard/asrock/h110… PS15, Line 13: HDMI3, -- HDMI (DDI3) I'm confused. There is no HDMI in the picture linked? I assume the -HDV version of the board would have that. But is the coreboot port compatible? -- To view, visit https://review.coreboot.org/c/coreboot/+/39104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Gerrit-Change-Number: 39104 Gerrit-PatchSet: 15 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 02 Dec 2020 22:40:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/i2c/nct7802y: Move the sensor initialization procedure
by Maxim Polyakov (Code Review) 02 Dec '20

02 Dec '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47861 ) Change subject: drivers/i2c/nct7802y: Move the sensor initialization procedure ...................................................................... drivers/i2c/nct7802y: Move the sensor initialization procedure Current place for the sensor initialization procedure was chosen unsuccessfully. Move it to the main driver file - nct7802y.c . Change-Id: I093ae75db5f0051bff65375b0720c86642b9148a Signed-off-by: Maxim Polyakov <m.polyakov(a)yadro.com> --- M src/drivers/i2c/nct7802y/nct7802y.c M src/drivers/i2c/nct7802y/nct7802y_fan.c 2 files changed, 16 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/47861/1 diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c index 5057890..8b4bdab 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.c +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -2,10 +2,25 @@ #include <console/console.h> #include <device/device.h> +#include <types.h> #include "nct7802y.h" #include "chip.h" +void nct7802y_init_sensors(struct device *const dev) +{ + const struct drivers_i2c_nct7802y_config *const config = dev->chip_info; + unsigned int i; + u8 value; + + value = 0; + for (i = 0; i < NCT7802Y_RTD_CNT; ++i) + value |= MODE_SELECTION_RTDx(i, config->sensors.rtd[i]); + if (config->sensors.local_enable) + value |= MODE_SELECTION_LTD_EN; + nct7802y_write(dev, MODE_SELECTION, value); +} + static void nct7802y_init(struct device *const dev) { if (!dev->chip_info) { @@ -15,6 +30,7 @@ } nct7802y_init_peci(dev); + nct7802y_init_sensors(dev); nct7802y_init_fan(dev); } diff --git a/src/drivers/i2c/nct7802y/nct7802y_fan.c b/src/drivers/i2c/nct7802y/nct7802y_fan.c index a608802..bfe3a91 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_fan.c +++ b/src/drivers/i2c/nct7802y/nct7802y_fan.c @@ -78,13 +78,6 @@ init_fan(dev, &config->fan[i], i); } - value = 0; - for (i = 0; i < NCT7802Y_RTD_CNT; ++i) - value |= MODE_SELECTION_RTDx(i, config->sensors.rtd[i]); - if (config->sensors.local_enable) - value |= MODE_SELECTION_LTD_EN; - nct7802y_write(dev, MODE_SELECTION, value); - switch (config->on_pecierror) { case PECI_ERROR_KEEP: value = CLOSE_LOOP_FAN_PECI_ERR_CURR; -- To view, visit https://review.coreboot.org/c/coreboot/+/47861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I093ae75db5f0051bff65375b0720c86642b9148a Gerrit-Change-Number: 47861 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfs: Port cbfs_load() and cbfs_map() to new API
by Julius Werner (Code Review) 02 Dec '20

02 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39305 to review the following change. Change subject: cbfs: Port cbfs_load() and cbfs_map() to new API ...................................................................... cbfs: Port cbfs_load() and cbfs_map() to new API This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API directly, rather than through cbfs_boot_locate(). For cbfs_load() this means that attribute metadata does not need to be read twice. Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/lib/cbfs.c 3 files changed, 43 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39305/1 diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 85a75ab..7e309ec 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -155,3 +155,21 @@ }; return cbfs_walk(dev, lookup_walker, &args, master_hash, 0); } + +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag) +{ + uint32_t offset = be32toh(mdata->h.attributes_offset); + uint32_t end = be32toh(mdata->h.offset); + + if (!offset) + return NULL; + + while (offset < end) { + struct cbfs_file_attribute *attr = (void *)mdata + offset; + if (be32toh(attr->tag) == attr_tag) + return attr; + offset += be32toh(attr->len); + } + + return NULL; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index df97009..4962cef 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -112,4 +112,7 @@ /* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size); +/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian). */ +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index bece4d0..c3660aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -81,18 +81,19 @@ void *cbfs_map(const char *name, size_t *size) { - struct cbfsf fh; - size_t fsize; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL)) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return NULL; - fsize = region_device_sz(&fh.data); + size_t data_size = be32toh(mdata.h.len); if (size != NULL) - *size = fsize; + *size = data_size; - return rdev_mmap(&fh.data, 0, fsize); + return rdev_mmap(&cbd->rdev, data_offset, data_size); } int cbfs_unmap(void *mapping) @@ -216,21 +217,25 @@ size_t cbfs_load(const char *name, void *buf, size_t buf_size) { - struct cbfsf fh; - uint32_t compression_algo; - size_t decompressed_size; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL) < 0) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return 0; - if (cbfsf_decompression_info(&fh, &compression_algo, - &decompressed_size) - < 0 - || decompressed_size > buf_size) - return 0; + uint32_t compression = CBFS_COMPRESS_NONE; + struct cbfs_file_attr_compression *attr = + cbfs_find_attr(&mdata, CBFS_FILE_ATTR_TAG_COMPRESSION); + if (attr) { + compression = be32toh(attr->compression); + if (buf_size < be32toh(attr->decompressed_size)) + return 0; + } - return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data), - buf, buf_size, compression_algo); + return cbfs_load_and_decompress(&cbd->rdev, data_offset, + be32toh(mdata.h.len), buf, buf_size, + compression); } size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) -- To view, visit https://review.coreboot.org/c/coreboot/+/39305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Gerrit-Change-Number: 39305 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfs: Move more stuff into cbfs_boot_lookup()
by Julius Werner (Code Review) 02 Dec '20

02 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39327 to review the following change. Change subject: cbfs: Move more stuff into cbfs_boot_lookup() ...................................................................... cbfs: Move more stuff into cbfs_boot_lookup() cbfs_boot_locate() is supposed to be deprecated eventually, after slowly migrating all APIs to bypass it. That means common features (like RO-fallback or measurement) need to be moved to the new cbfs_boot_lookup(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a --- M src/lib/cbfs.c M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 3 files changed, 34 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39327/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 39db97a..ef29299 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -31,40 +31,47 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> -static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd, - const char *name, union cbfs_mdata *mdata, size_t *data_offset) +static cb_err_t cbfs_boot_lookup(struct region_device *rdev, const char *name, + union cbfs_mdata *mdata, size_t *data_offset, bool force_ro) { + cb_err_t err; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); + if (!cbd || rdev_chain_full(rdev, &cbd->rdev)) + return CB_ERR; + if (CONFIG(NO_CBFS_MCACHE)) - return cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL); + err = cbfs_lookup(rdev, name, mdata, data_offset, NULL); else - return cbfs_mcache_lookup(&cbd->rdev, - cbd->mcache, cbd->mcache_size, - name, mdata, data_offset, NULL); + err = cbfs_mcache_lookup(rdev, cbd->mcache, cbd->mcache_size, + name, mdata, data_offset, NULL); + + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro && + err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); + return cbfs_boot_lookup(rdev, name, mdata, data_offset, true); + } + if (err) + return err; + + if (vboot_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) + return CB_ERR; + + return CB_SUCCESS; } int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); - if (!cbd) - return -1; - + struct region_device rdev; union cbfs_mdata mdata; size_t data_offset; - cb_err_t err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { - printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", - name); - if (!(cbd = cbfs_get_boot_device(true))) - return -1; - err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - } - if (err) + if (cbfs_boot_lookup(&rdev, name, &mdata, &data_offset, false)) return -1; size_t msize = be32toh(mdata.h.offset); - if (rdev_chain(&fh->metadata, &cbd->rdev, data_offset - msize, msize) || - rdev_chain(&fh->data, &cbd->rdev, data_offset, be32toh(mdata.h.len))) + if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) return -1; if (type) { if (!*type) @@ -73,9 +80,6 @@ return -1; } - if (vboot_measure_cbfs_hook(fh, name)) - return -1; - return 0; } diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index f68ab0a4..75c5662 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -157,19 +157,16 @@ return false; } -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name) +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type) { uint32_t pcr_index; - uint32_t cbfs_type; struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; if (!vboot_logic_executed()) return 0; - cbfsf_file_type(fh, &cbfs_type); - cbfs_file_data(&rdev, fh); - switch (cbfs_type) { case CBFS_TYPE_MRC: case CBFS_TYPE_MRC_CACHE: diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..8e6c076 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -49,13 +49,14 @@ #if CONFIG(VBOOT_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) - * fh is the cbfs file handle to measure + * rdev covers the file data (not metadata) * return 0 if successful, else an error */ -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type); #else -#define vboot_measure_cbfs_hook(fh, name) 0 +#define vboot_measure_cbfs_hook(rdev, name, cbfs_type) 0 #endif #endif /* __VBOOT_VBOOT_CRTM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a Gerrit-Change-Number: 39327 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
by Furquan Shaikh (Code Review) 02 Dec '20

02 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48130 ) Change subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry ...................................................................... soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry This change drops the special check added for TGL/JSL platforms and performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later in the boot process to ensure that the memory training parameters are written back to SPI flash before performing a reset for CSE RW jump. With the recent changes in CB:44196 ("mrc_cache: Update mrc_cache data in romstage"), MRC cache is updated right away in romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/48130/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9c498b5..9011593 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -809,12 +809,4 @@ } } -#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) -/* - * This needs to happen after the MRC cache write to avoid a 2nd - * memory training sequence. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); -#else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 Gerrit-Change-Number: 48130 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/amd: factor out common SMI/SCI enums and function prototypes
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48217 ) Change subject: soc/amd: factor out common SMI/SCI enums and function prototypes ...................................................................... soc/amd: factor out common SMI/SCI enums and function prototypes At least a part or the remaining definitions in the soc-specific smi.h files are also common, but those have to be verified more closely. Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/gpio_banks/gpio.c A src/soc/amd/common/block/include/amdblocks/smi.h M src/soc/amd/picasso/gpio.c M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/psp.c M src/soc/amd/picasso/smi_util.c M src/soc/amd/picasso/smihandler.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/picasso/xhci.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/amd/stoneyridge/southbridge.c 14 files changed, 62 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/48217/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 91773d9..a5f0eaf 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -7,6 +7,7 @@ #include <gpio.h> #include <amdblocks/acpimmio.h> #include <amdblocks/gpio_banks.h> +#include <amdblocks/smi.h> #include <soc/gpio.h> #include <soc/smi.h> #include <assert.h> diff --git a/src/soc/amd/common/block/include/amdblocks/smi.h b/src/soc/amd/common/block/include/amdblocks/smi.h new file mode 100644 index 0000000..ab00933 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/smi.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_SMI_H +#define AMD_BLOCK_SMI_H + +#include <stdint.h> + +enum smi_mode { + SMI_MODE_DISABLE = 0, + SMI_MODE_SMI = 1, + SMI_MODE_NMI = 2, + SMI_MODE_IRQ13 = 3, +}; + +enum smi_sci_type { + INTERRUPT_NONE, + INTERRUPT_SCI, + INTERRUPT_SMI, + INTERRUPT_BOTH, +}; + +enum smi_sci_lvl { + SMI_SCI_LVL_LOW, + SMI_SCI_LVL_HIGH, +}; + +enum smi_sci_dir { + SMI_SCI_EDG, + SMI_SCI_LVL, +}; + +struct smi_sources_t { + int type; + void (*handler)(void); +}; + +struct sci_source { + uint8_t scimap; /* SCIMAP 0-57 */ + uint8_t gpe; /* 32 GPEs */ + uint8_t direction; /* Active High or Low, smi_sci_lvl */ + uint8_t level; /* Edge or Level, smi_sci_dir */ +}; + +void configure_smi(uint8_t smi_num, uint8_t mode); +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void configure_scimap(const struct sci_source *sci); +void disable_gevent_smi(uint8_t gevent); +void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); +void soc_route_sci(uint8_t event); + +#endif /* AMD_BLOCK_SMI_H */ diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index c402fb5..3ad4c5c 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> #include <soc/gpio.h> #include <soc/smi.h> diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 1f08efe..ad7edbc 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -178,47 +178,4 @@ #define SMI_MODE_MASK 0x03 -enum smi_mode { - SMI_MODE_DISABLE = 0, - SMI_MODE_SMI = 1, - SMI_MODE_NMI = 2, - SMI_MODE_IRQ13 = 3, -}; - -enum smi_sci_type { - INTERRUPT_NONE, - INTERRUPT_SCI, - INTERRUPT_SMI, - INTERRUPT_BOTH, -}; - -enum smi_sci_lvl { - SMI_SCI_LVL_LOW, - SMI_SCI_LVL_HIGH, -}; - -enum smi_sci_dir { - SMI_SCI_EDG, - SMI_SCI_LVL, -}; - -struct smi_sources_t { - int type; - void (*handler)(void); -}; - -struct sci_source { - uint8_t scimap; /* SCIMAP 0-57 */ - uint8_t gpe; /* 32 GPEs */ - uint8_t direction; /* Active High or Low, smi_sci_lvl */ - uint8_t level; /* Edge or Level, smi_sci_dir */ -}; - -void configure_smi(uint8_t smi_num, uint8_t mode); -void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); -void configure_scimap(const struct sci_source *sci); -void disable_gevent_smi(uint8_t gevent); -void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); -void soc_route_sci(uint8_t event); - #endif /* AMD_PICASSO_SMI_H */ diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c index 702b0d9..6a4a1ea 100644 --- a/src/soc/amd/picasso/psp.c +++ b/src/soc/amd/picasso/psp.c @@ -5,6 +5,7 @@ #include <soc/smi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/psp.h> +#include <amdblocks/smi.h> #define PSP_MAILBOX_OFFSET 0x10570 #define MSR_CU_CBBCFG 0xc00110a2 diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2fbc8e2..39b2b95 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -9,6 +9,7 @@ #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> void configure_smi(uint8_t smi_num, uint8_t mode) { diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 7e762a9..4931de8 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -14,6 +14,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> #include <amdblocks/psp.h> +#include <amdblocks/smi.h> #include <elog.h> #include <soc/smu.h> diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index edbcb60..8e0ceb2 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -19,6 +19,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/smbus.h> #include <amdblocks/spi.h> +#include <amdblocks/smi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/i2c.h> diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c index 97a012e..a7e4807 100644 --- a/src/soc/amd/picasso/xhci.c +++ b/src/soc/amd/picasso/xhci.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/gpio_banks.h> +#include <amdblocks/smi.h> #include <bootstate.h> #include <device/device.h> #include <drivers/usb/pci_xhci/pci_xhci.h> diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index a595014..f1ed202 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> #include <soc/gpio.h> #include <soc/smi.h> diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 60a91d0..6162475 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -175,47 +175,4 @@ #define SMI_REG_CONTROL8 0xc0 #define SMI_REG_CONTROL9 0xc4 -enum smi_mode { - SMI_MODE_DISABLE = 0, - SMI_MODE_SMI = 1, - SMI_MODE_NMI = 2, - SMI_MODE_IRQ13 = 3, -}; - -enum smi_sci_type { - INTERRUPT_NONE, - INTERRUPT_SCI, - INTERRUPT_SMI, - INTERRUPT_BOTH, -}; - -enum smi_sci_lvl { - SMI_SCI_LVL_LOW, - SMI_SCI_LVL_HIGH, -}; - -enum smi_sci_dir { - SMI_SCI_EDG, - SMI_SCI_LVL, -}; - -struct smi_sources_t { - int type; - void (*handler)(void); -}; - -struct sci_source { - uint8_t scimap; /* SCIMAP 0-57 */ - uint8_t gpe; /* 32 GPEs */ - uint8_t direction; /* Active High or Low, smi_sci_lvl */ - uint8_t level; /* Edge or Level, smi_sci_dir */ -}; - -void configure_smi(uint8_t smi_num, uint8_t mode); -void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); -void configure_scimap(const struct sci_source *sci); -void disable_gevent_smi(uint8_t gevent); -void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); -void soc_route_sci(uint8_t event); - #endif /* AMD_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2fbc8e2..39b2b95 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -9,6 +9,7 @@ #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> void configure_smi(uint8_t smi_num, uint8_t mode) { diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index be55458..c8a113c 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -13,6 +13,7 @@ #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> +#include <amdblocks/smi.h> #include <elog.h> /* bits in smm_io_trap */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 84872ab..f5e652e 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -18,6 +18,7 @@ #include <amdblocks/lpc.h> #include <amdblocks/acpi.h> #include <amdblocks/smbus.h> +#include <amdblocks/smi.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a Gerrit-Change-Number: 48217 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/amd/common/smbus: remove misleading definition
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48219 ) Change subject: soc/amd/common/smbus: remove misleading definition ...................................................................... soc/amd/common/smbus: remove misleading definition SMBHST_STAT_NOERROR was a redefinition of SMBHST_STAT_INTERRUPT that was used in smbus_wait_until_done. Remove the misleading bit definition that also didn't correspond with the register definitions and replace it with the definition of the actual bit that gets checked. Also add a comment that the code actually checks the IRQ status flag to see if the last command is already completed. Change-Id: I1a58fe0d58d3887dd2e83320e977a57e271685b3 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/smbus.h M src/soc/amd/common/block/smbus/smbus.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48219/1 diff --git a/src/soc/amd/common/block/include/amdblocks/smbus.h b/src/soc/amd/common/block/include/amdblocks/smbus.h index 773daf7..73f63b0 100644 --- a/src/soc/amd/common/block/include/amdblocks/smbus.h +++ b/src/soc/amd/common/block/include/amdblocks/smbus.h @@ -11,7 +11,6 @@ #define SMBHST_STAT_INTERRUPT (1 << 1) #define SMBHST_STAT_BUSY (1 << 0) #define SMBHST_STAT_CLEAR 0xff -#define SMBHST_STAT_NOERROR (1 << 1) /* TODO: this one looks odd */ #define SMBHST_STAT_VAL_BITS 0x1f #define SMBHST_STAT_ERROR_BITS 0x1c diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index e94adf5..4fb68d4 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -69,7 +69,8 @@ val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ if (val & SMBHST_STAT_ERROR_BITS) return -5; /* error */ - if (val == SMBHST_STAT_NOERROR) { + /* check IRQ status bit to see if the last host command is completed */ + if (val == SMBHST_STAT_INTERRUPT) { controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a58fe0d58d3887dd2e83320e977a57e271685b3 Gerrit-Change-Number: 48219 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd: factor out fch_smbus_init
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48218 ) Change subject: soc/amd: factor out fch_smbus_init ...................................................................... soc/amd: factor out fch_smbus_init Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/smbus.h M src/soc/amd/common/block/smbus/Makefile.inc A src/soc/amd/common/block/smbus/smbus_early_fch.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 23 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/48218/1 diff --git a/src/soc/amd/common/block/include/amdblocks/smbus.h b/src/soc/amd/common/block/include/amdblocks/smbus.h index b618b78..773daf7 100644 --- a/src/soc/amd/common/block/include/amdblocks/smbus.h +++ b/src/soc/amd/common/block/include/amdblocks/smbus.h @@ -47,4 +47,6 @@ #define SMBSLVDAT 0xc #define SMBTIMING 0xe +void fch_smbus_init(void); + #endif /* AMD_BLOCK_SMBUS_H */ diff --git a/src/soc/amd/common/block/smbus/Makefile.inc b/src/soc/amd/common/block/smbus/Makefile.inc index b9c7f2a..867465e 100644 --- a/src/soc/amd/common/block/smbus/Makefile.inc +++ b/src/soc/amd/common/block/smbus/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y) +bootblock-y += smbus_early_fch.c romstage-y += smbus.c ramstage-y += smbus.c ramstage-y += sm.c diff --git a/src/soc/amd/common/block/smbus/smbus_early_fch.c b/src/soc/amd/common/block/smbus/smbus_early_fch.c new file mode 100644 index 0000000..3d04778 --- /dev/null +++ b/src/soc/amd/common/block/smbus/smbus_early_fch.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/smbus.h> +#include <soc/southbridge.h> + +void fch_smbus_init(void) +{ + /* 400 kHz smbus speed. */ + const uint8_t smbus_speed = (66000000 / (400000 * 4)); + + pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); + smbus_write8(SMBTIMING, smbus_speed); + /* Clear all SMBUS status bits */ + smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); + asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); +} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index edbcb60..f342449 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -113,20 +113,6 @@ misc_write32(MISC_CLK_CNTL1, ctrl); } -static void fch_smbus_init(void) -{ - /* 400 kHz smbus speed. */ - const uint8_t smbus_speed = (66000000 / (400000 * 4)); - - pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(SMBTIMING, smbus_speed); - /* Clear all SMBUS status bits */ - smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); - asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); - asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); -} - static void lpc_configure_decodes(void) { if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 84872ab..c59936d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -332,20 +332,6 @@ } } -static void fch_smbus_init(void) -{ - /* 400 kHz smbus speed. */ - const uint8_t smbus_speed = (66000000 / (400000 * 4)); - - pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(SMBTIMING, smbus_speed); - /* Clear all SMBUS status bits */ - smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); - asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); - asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); -} - /* Before console init */ void bootblock_fch_early_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/48218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54 Gerrit-Change-Number: 48218 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020