Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48160 )
Change subject: mb/google/volteer: Add fw_config entries for boot device
......................................................................
mb/google/volteer: Add fw_config entries for boot device
Add the fw_config entries for the newly added boot device fields.
These are added as separate fields since a board may have more
than one selected.
BUG=b:173129299
TEST=abuild google/volteer
Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/48160/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 455b9ab..1b3b1cc 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -46,6 +46,18 @@
option KB_LAYOUT_DEFAULT 0
option KB_LAYOUT_1 1
end
+ field BOOT_DEVICE_EMMC 22
+ option BOOT_EMMC_DISABLED 0
+ option BOOT_EMMC_ENABLED 1
+ end
+ field BOOT_DEVICE_NVME 23
+ option BOOT_NVME_DISABLED 0
+ option BOOT_NVME_ENABLED 1
+ end
+ field BOOT_DEVICE_SATA 24
+ option BOOT_SATA_DISABLED 0
+ option BOOT_SATA_ENABLED 1
+ end
end
chip soc/intel/tigerlake
--
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42472 )
Change subject: [WIP] soc/amd/picasso: add FSP binary location
......................................................................
[WIP] soc/amd/picasso: add FSP binary location
Since the blobs haven't landed yet, it is expected that this breaks the
Jenkins build.
Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/picasso/Kconfig
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42472/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index dd5731d..bf809f8 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -60,6 +60,20 @@
string
default "src/soc/amd/picasso/memlayout.ld"
+config FSP_M_FILE
+ string "FSP-M (memory init) binary path and filename"
+ depends on ADD_FSP_BINARIES
+ default "3rdparty/amd_blobs/picasso/PICASSO_M.fd"
+ help
+ The path and filename of the FSP-M binary for this platform.
+
+config FSP_S_FILE
+ string "FSP-S (silicon init) binary path and filename"
+ depends on ADD_FSP_BINARIES
+ default "3rdparty/amd_blobs/picasso/PICASSO_S.fd"
+ help
+ The path and filename of the FSP-S binary for this platform.
+
config EARLY_RESERVED_DRAM_BASE
hex
default 0x2000000
--
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Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48213 )
Change subject: mb/intel/adlrvp: Replace tab by white space in devicetree
......................................................................
mb/intel/adlrvp: Replace tab by white space in devicetree
Change-Id: I928b4528fa5b4c378a2e8ff7bb88547da1413df2
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/48213/1
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index f2f768a..daf6ed1 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -230,7 +230,7 @@
device generic 0 on end
end
end # CNVi: WiFi
- device pci 15.0 on end # I2C0
+ device pci 15.0 on end # I2C0
device pci 15.1 on end # I2C1
device pci 15.2 on end # I2C2
device pci 15.3 on end # I2C3
--
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48090 )
Change subject: soc/intel/common/block/gpio: add code for NMI enabling
......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acp…
File src/soc/intel/skylake/acpi.c:
https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acp…
PS10, Line 526: 1)
> always LINT1?
yes, see IOAPIC spec
https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acp…
PS10, Line 526: 5,
> will this always be active-high, edge-triggered?
mh, LINT1 is a ISA interrupt (see IOAPIC spec) - and ISA interrupts are always edge/active-high according to the ACPI spec
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48089 )
Change subject: intel/common/block/gpio: only reset configured SMI instead of all
......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48089/10/src/soc/intel/common/bloc…
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/48089/10/src/soc/intel/common/bloc…
PS10, Line 169: en_reg = GPI_SMI_EN_OFFSET(comm, group);
> nit: This didn't really have to move up from line 175.
yes, it didn't have to, I just did it for consistency
https://review.coreboot.org/c/coreboot/+/48089/10/src/soc/intel/common/bloc…
PS10, Line 170: en_value
> or maybe gpio_bitmask?
I used en_value, because it actually is the bitmask of the enabled smi. Since we need to reset the enabled one, using it with that name for reset, shouldn't hurt
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Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47803 )
Change subject: vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341
......................................................................
vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341
The FSP-M/S/T related headers added are generated as per FSP v2341.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com>
Change-Id: I98f738402490b47efa1a346f81db47857e384e13
---
A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h
A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h
6 files changed, 8,433 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47803/1
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Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43853 )
Change subject: soc/intel/skylake: Map VBIOS IDs
......................................................................
soc/intel/skylake: Map VBIOS IDs
The extracted VBIOS Option ROM ships the same ID for several
generations, not matching the ID on the hardware resulting in a
mismatch, and coreboot does not run the Option ROM.
PCI ROM image, vendor ID 8086, device ID 0406,
ID mismatch: vendor ID 8086, device ID 5916
Add the appropriate mappings.
TEST=coreboot runs the ROM on the TUXEDO Book BU1406.
Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/soc/intel/skylake/graphics.c
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/43853/1
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index 4ecf67a..f95ca6c 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -3,11 +3,13 @@
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/mmio.h>
+#include <device/pci_rom.h>
#include <device/resource.h>
#include <drivers/intel/gma/i915.h>
#include <drivers/intel/gma/i915_reg.h>
#include <intelblocks/graphics.h>
#include <soc/ramstage.h>
+#include <soc/systemagent.h>
#include <types.h>
void graphics_soc_init(struct device *dev)
@@ -76,3 +78,21 @@
struct soc_intel_skylake_config *chip = device->chip_info;
return &chip->gfx;
}
+
+/*
+ * Some VGA option roms are used for several chipsets but they only have one PCI ID in their
+ * header. If we encounter such an option rom, we need to do the mapping ourselves.
+ */
+u32 map_oprom_vendev(u32 vendev)
+{
+ u32 new_vendev = vendev;
+
+ switch (vendev) {
+ case 0x80865916: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM */
+ case 0x80865917: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR */
+ new_vendev = SA_IGD_OPROM_VENDEV;
+ break;
+ }
+
+ return new_vendev;
+}
--
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