coreboot-gerrit December 2020

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Change in coreboot[master]: mt8192/dpm.c: use load_blob_file to load the blob files
by Yidi Lin (Code Review) 02 Dec '20

02 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46932 ) Change subject: mt8192/dpm.c: use load_blob_file to load the blob files ...................................................................... mt8192/dpm.c: use load_blob_file to load the blob files Use load_blob_file to load the blob files. TEST=1. emerge-asurada coreboot chromeos-bootimage; 2. See following log during booting. load_blob_file: Load dpm.dm in 15 msecs, size 36 bytes load_blob_file: Load dpm.pm in 18 msecs, size 13848 bytes 3. Test suspend/resume by: a. suspend (on DUT): echo mem > /sys/power/stat b. resume (on host): dut-control power_state:on Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: If5e51d1390a3daf5fac68e1180506ec0431160d2 --- M src/soc/mediatek/mt8192/dpm.c 1 file changed, 10 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46932/1 diff --git a/src/soc/mediatek/mt8192/dpm.c b/src/soc/mediatek/mt8192/dpm.c index ef46c30..912f153 100644 --- a/src/soc/mediatek/mt8192/dpm.c +++ b/src/soc/mediatek/mt8192/dpm.c @@ -1,50 +1,30 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <assert.h> -#include <cbfs.h> #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <soc/dpm.h> +#include <soc/mtlib_common.h> #include <timer.h> -#define DM_BUF_SIZE (2 * KiB) -#define PM_BUF_SIZE (20 * KiB) - -static u8 dpm_dm_bin[DM_BUF_SIZE] __aligned(8); -static u8 dpm_pm_bin[PM_BUF_SIZE] __aligned(8); -static void *dpm_pm_reg = (void *)DPM_PM_SRAM_BASE; -static void *dpm_dm_reg = (void *)DPM_DM_SRAM_BASE; /* Return Value: 0 successful, < 0 means failed */ static int dpm_load_firmware(void) { const char *dm_file_name = "dpm.dm"; const char *pm_file_name = "dpm.pm"; - size_t dm_file_bytes, pm_file_bytes; - - dm_file_bytes = cbfs_boot_load_file(dm_file_name, dpm_dm_bin, - sizeof(dpm_dm_bin), CBFS_TYPE_RAW); - if (dm_file_bytes == 0) { - printk(BIOS_ERR, "binary %s not found\n", dm_file_name); - return -1; - } - - pm_file_bytes = cbfs_boot_load_file(pm_file_name, dpm_pm_bin, - sizeof(dpm_pm_bin), CBFS_TYPE_RAW); - if (pm_file_bytes == 0) { - printk(BIOS_ERR, "binary %s not found\n", pm_file_name); - return -2; - } - printk(BIOS_INFO, "dm_file_bytes: %d, pm_file_bytes: %d\n", - (int)dm_file_bytes, (int)pm_file_bytes); /* config DPM SRAM layout */ write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x10000000); - /* copy PM DM to DPM_SRAM */ - memcpy(dpm_pm_reg, dpm_pm_bin, pm_file_bytes); - memcpy(dpm_dm_reg, dpm_dm_bin, dm_file_bytes); + if (load_blob_file(dm_file_name, DPM_DM_SRAM_BASE)) { + printk(BIOS_ERR, "binary %s not found\n", dm_file_name); + return -1; + } + + if (load_blob_file(pm_file_name, DPM_PM_SRAM_BASE)) { + printk(BIOS_ERR, "binary %s not found\n", pm_file_name); + return -2; + } /* write bootargs */ write32(&mtk_dpm->twam_window_len, 0x0); @@ -58,16 +38,10 @@ int dpm_init(void) { - struct stopwatch sw; - stopwatch_init(&sw); - if (dpm_load_firmware()) { printk(BIOS_ERR, "DPM: firmware is not ready\n"); return -1; } - printk(BIOS_INFO, "DPM: load finish in %ld msecs\n", - stopwatch_duration_msecs(&sw)); - return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5e51d1390a3daf5fac68e1180506ec0431160d2 Gerrit-Change-Number: 46932 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/acpi/acpigen: Add NULL pointer check
by Subrata Banik (Code Review) 02 Dec '20

02 Dec '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48148 ) Change subject: src/acpi/acpigen: Add NULL pointer check ...................................................................... src/acpi/acpigen: Add NULL pointer check Add NULL pointer check in acpigen_emit_namestring to avoid segmentation fault. Change-Id: I3d01d28e74f202278b5a5a96d2edd45c66f10883 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48148 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpigen.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 244ac54..9a5543d 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -291,6 +291,10 @@ int dotcount = 0, i; int dotpos = 0; + /* Check for NULL pointer */ + if (!namepath) + return; + /* We can start with a '\'. */ if (namepath[0] == '\\') { acpigen_emit_byte('\\'); -- To view, visit https://review.coreboot.org/c/coreboot/+/48148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d01d28e74f202278b5a5a96d2edd45c66f10883 Gerrit-Change-Number: 48148 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S Audio for ADLRVP
by Sathya Prakash M R (Code Review) 02 Dec '20

02 Dec '20

Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48000 ) Change subject: mb/intel/adlrvp: Enable I2S Audio for ADLRVP ...................................................................... Patch Set 5: on ERB we had HS INT working which is not on RVP. Will wait for verification on that before giving a +1. -- To view, visit https://review.coreboot.org/c/coreboot/+/48000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948b4528ea5c4c378a2e8ff7bb88546da1413df2 Gerrit-Change-Number: 48000 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 Dec 2020 04:48:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: volteer/variants/volteer2: Goodix touch panel power-on sequence tuning
by Jesper Lin (Code Review) 02 Dec '20

02 Dec '20

Jesper Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48226 ) Change subject: volteer/variants/volteer2: Goodix touch panel power-on sequence tuning ...................................................................... volteer/variants/volteer2: Goodix touch panel power-on sequence tuning 1. generic.reset_delay_ms change to 30 Change-Id: Ic23ffab78d3f52c41917dc2794506ccd7dffe8b4 --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/48226/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index a1012a6..3b3603c 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -161,7 +161,7 @@ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" # Parameter T3 >= 10ms - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "30" # Parameter T2 >= 1ms register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" -- To view, visit https://review.coreboot.org/c/coreboot/+/48226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic23ffab78d3f52c41917dc2794506ccd7dffe8b4 Gerrit-Change-Number: 48226 Gerrit-PatchSet: 1 Gerrit-Owner: Jesper Lin <jesper_lin(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: align AOAC code with Picasso
by Felix Held (Code Review) 01 Dec '20

01 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48181 ) Change subject: soc/amd/stoneyridge: align AOAC code with Picasso ...................................................................... soc/amd/stoneyridge: align AOAC code with Picasso In commit 09d50671e6b43c23853a91ff4d6fb26c1e7e17a1 the AOAC code was reworked for Picasso and this patch ports this back to Stoneyridge to facilitate factoring out the functionality into common code. Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 36 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/48181/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cbd9caa..9450a92 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -190,16 +190,20 @@ #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) /* FCH AOAC Registers 0xfed81e00 */ -#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c -#define FCH_AOAC_D3_CONTROL_I2C2 0x4e -#define FCH_AOAC_D3_CONTROL_I2C3 0x50 -#define FCH_AOAC_D3_CONTROL_UART0 0x56 -#define FCH_AOAC_D3_CONTROL_UART1 0x58 -#define FCH_AOAC_D3_CONTROL_AMBA 0x62 -#define FCH_AOAC_D3_CONTROL_USB2 0x64 -#define FCH_AOAC_D3_CONTROL_USB3 0x6e +#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) +#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) + +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_USB2 18 +#define FCH_AOAC_DEV_USB3 23 + /* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) @@ -209,16 +213,6 @@ #define FCH_AOAC_SW_RST_B BIT(6) #define FCH_AOAC_IS_SW_CONTROL BIT(7) -#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d -#define FCH_AOAC_D3_STATE_I2C2 0x4f -#define FCH_AOAC_D3_STATE_I2C3 0x51 -#define FCH_AOAC_D3_STATE_UART0 0x57 -#define FCH_AOAC_D3_STATE_UART1 0x59 -#define FCH_AOAC_D3_STATE_AMBA 0x63 -#define FCH_AOAC_D3_STATE_USB2 0x65 -#define FCH_AOAC_D3_STATE_USB3 0x6f /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) @@ -292,11 +286,6 @@ #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct stoneyridge_aoac { - int enable; - int status; -}; - typedef struct aoac_devs { unsigned int :5; unsigned int ic0e:1; /* 5: I2C0 */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 267f747..05f3072 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -31,14 +31,13 @@ * waiting for each device to become available, a single delay will be * executed. */ -static const struct stoneyridge_aoac aoac_devs[] = { - { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), - (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, - { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, - { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } +static const unsigned int aoac_devs[] = { + FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, }; static int is_sata_config(void) @@ -146,21 +145,21 @@ return irq_association; } -static void power_on_aoac_device(int aoac_device_control_register) +static void power_on_aoac_device(unsigned int dev) { uint8_t byte; /* Power on the UART and AMBA devices */ - byte = aoac_read8(aoac_device_control_register); + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; - aoac_write8(aoac_device_control_register, byte); + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -static bool is_aoac_device_enabled(int aoac_device_status_register) +static bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte; - byte = aoac_read8(aoac_device_status_register); + byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -174,14 +173,14 @@ int i; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i].enable); + power_on_aoac_device(aoac_devs[i]); /* Wait for AOAC devices to indicate power and clock OK */ do { udelay(100); status = true; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i].status); + status &= is_aoac_device_enabled(aoac_devs[i]); } while (!status); } @@ -545,14 +544,14 @@ if (gnvs == NULL) return; - gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); + gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); + gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); + gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); + gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/48181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211 Gerrit-Change-Number: 48181 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/aoac: make aoac_devs array unsigned
by Felix Held (Code Review) 01 Dec '20

01 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48180 ) Change subject: soc/amd/picasso/aoac: make aoac_devs array unsigned ...................................................................... soc/amd/picasso/aoac: make aoac_devs array unsigned The numbers in the array are unsigned, so use an unsigned type there. Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/aoac.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48180/1 diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index f9fe0e2..00f26fe 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -21,7 +21,7 @@ * waiting for each device to become available, a single delay will be * executed. The console UART is handled separately from this table. */ -const static int aoac_devs[] = { +const static unsigned int aoac_devs[] = { FCH_AOAC_DEV_AMBA, FCH_AOAC_DEV_I2C2, FCH_AOAC_DEV_I2C3, -- To view, visit https://review.coreboot.org/c/coreboot/+/48180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348 Gerrit-Change-Number: 48180 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: add vbt_drawman file to CBFS
by Maulik V Vaghela (Code Review) 01 Dec '20

01 Dec '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48205 ) Change subject: mb/google/dedede/var/drawcia: add vbt_drawman file to CBFS ...................................................................... mb/google/dedede/var/drawcia: add vbt_drawman file to CBFS Drawman board has different port configuration where it has HDMI port on DDI2. We need separate VBT file for drawman to handle this since all other variants has type-C port. Stitching vbt_drawman.bin will allow coreboot to check fw_config and get correct VBT files as per port supported. BUG=b:161190931 BRANCH=dedede TEST=vbt_drawman is stitched into CBFS and drawcia and drawman boots fine. Cq-Depend: chrome-internal:3436383 Change-Id: Ic68e211126eadbd2c866027619e1ed4e6128d905 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/Makefile.inc 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/48205/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc index 24c75d1..cef8047 100644 --- a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc @@ -1,3 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-$(CONFIG_FW_CONFIG) += variant.c + +cbfs-files-y += vbt_drawman.bin +vbt_drawman.bin-file := 3rdparty/blobs/baseboard-dedede/vbt_drawman.bin +vbt_drawman.bin-type := raw +vbt_drawman.bin-compression := lzma + + -- To view, visit https://review.coreboot.org/c/coreboot/+/48205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic68e211126eadbd2c866027619e1ed4e6128d905 Gerrit-Change-Number: 48205 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/gpio: add code for NMI enabling
by Tim Wawrzynczak (Code Review) 01 Dec '20

01 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48090 ) Change subject: soc/intel/common/block/gpio: add code for NMI enabling ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acp… File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acp… PS10, Line 526: 1) always LINT1? https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acp… PS10, Line 526: 5, will this always be active-high, edge-triggered? -- To view, visit https://review.coreboot.org/c/coreboot/+/48090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Gerrit-Change-Number: 48090 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Dec 2020 18:22:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block/gpio: only reset configured SMI instead of all
by Tim Wawrzynczak (Code Review) 01 Dec '20

01 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48089 ) Change subject: intel/common/block/gpio: only reset configured SMI instead of all ...................................................................... Patch Set 10: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/48089/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/48089/10/src/soc/intel/common/bloc… PS10, Line 170: en_value > nit: Should this be just value since it is used for both sts_reg and en_reg? or maybe gpio_bitmask? -- To view, visit https://review.coreboot.org/c/coreboot/+/48089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc Gerrit-Change-Number: 48089 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Dec 2020 18:19:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Tim Wawrzynczak (Code Review) 01 Dec '20

01 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46314 ) Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Dec 2020 18:14:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020