coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Frank Chu (Code Review) 01 Dec '20

01 Dec '20

Frank Chu has removed Zhuohao Lee from this change. ( https://review.coreboot.org/c/coreboot/+/48194 ) Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... Removed reviewer Zhuohao Lee. -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Frank Chu (Code Review) 01 Dec '20

01 Dec '20

Hello build bot (Jenkins), Zhuohao Lee, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48194 to look at the new patch set (#3). Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48194/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: Update GPIO configurations according to schematics
by Jingle Hsu (Code Review) 01 Dec '20

01 Dec '20

Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Update GPIO configurations according to schematics ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 9 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Dec 2020 08:55:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 8 information
by Tim Chu (Code Review) 01 Dec '20

01 Dec '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47893 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 8 information ...................................................................... mb/ocp/deltalake: Update SMBIOS type 8 information Update port connector information for Delta Lake. Tested=Execute "dmidecode -t 8" to check all the information of SMBIOS type 8 is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47893/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 52c55b8..3f9e1c9 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -155,6 +155,38 @@ } } +static const struct port_information SMBIOS_type8_info[] = { + /* + * Port Information fields: + * Internal Reference Designator, + * Internal Connector Type, + * External Reference Designator, + * External Connector_Type, + * Port Type + */ + { + "JCN18 - CPU MIPI60", + CONN_OTHER, + "", + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "JCN32 - TPM_CONN", + CONN_OTHER, + "", + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "JCN7 - USB type C", + CONN_USB_TYPE_C, + "", + CONN_NONE, + TYPE_USB + }, +}; + static int create_smbios_type9(int *handle, unsigned long *current) { int index; @@ -256,6 +288,13 @@ { int len = 0; + // add port information + len += smbios_write_type8( + current, handle, + SMBIOS_type8_info, + ARRAY_SIZE(SMBIOS_type8_info) + ); + len += create_smbios_type9(handle, current); return len; -- To view, visit https://review.coreboot.org/c/coreboot/+/47893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f Gerrit-Change-Number: 47893 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec/acpi: Make OperationRegion brace align
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48149 ) Change subject: ec/google/chromeec/acpi: Make OperationRegion brace align ...................................................................... ec/google/chromeec/acpi: Make OperationRegion brace align Inject TAB to make OperationRegion closing brace align with opening brace. Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48149/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index d12274f..ce2455f 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -82,7 +82,7 @@ Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power -} + } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) OperationRegion (EMEM, EmbeddedControl, -- To view, visit https://review.coreboot.org/c/coreboot/+/48149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b Gerrit-Change-Number: 48149 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48131 ) Change subject: mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP ...................................................................... mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ hence remove the unused GPIO. Wrong GPIO configuration is causing platform reboot issue on ADLRVP with Chrome SKU. Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/include/baseboard/ec.h M src/mainboard/intel/adlrvp/include/baseboard/gpio.h 2 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48131/1 diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h index 4303faf..c018299 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/ec.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h @@ -56,9 +56,6 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h index b61276c..de0adf6 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -12,7 +12,4 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK -/* EC sync IRQ */ -#define EC_SYNC_IRQ GPP_A15_IRQ - #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Gerrit-Change-Number: 48131 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add ASL support for WFC annd UFC
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47497 ) Change subject: mb/intel/adlrvp: Add ASL support for WFC annd UFC ...................................................................... mb/intel/adlrvp: Add ASL support for WFC annd UFC 1. Add 2 Ports and 2 Endpoints 2. Add support for OVTI5675 WFC Cam is on I2C5 and UFC is on I2C1 Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 --- A src/mainboard/intel/adlrvp/acpi/mipi_camera.asl M src/mainboard/intel/adlrvp/dsdt.asl 2 files changed, 523 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47497/1 diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000..b09f7ae --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl @@ -0,0 +1,520 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + One, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C1.CAM0, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C1) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(0,1) /* Clock 0, 19.2MHz */ + + /* Pull PWREN high */ + STXS(GPP_B23) + Sleep(2) /* reset pulse width */ + + /* Pull RST low */ + CTXS(GPP_R5) + Sleep(1) /* t2 */ + + /* Pull RST high */ + STXS(GPP_R5) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(0) /* Clock 0 */ + + /* Pull RST low */ + CTXS(GPP_R5) + + /* Pull PWREN low */ + CTXS(GPP_B23) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "DW AF DAC") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(1,1) /* Clock 1, 19.2MHz */ + + /* Pull PWREN high */ + STXS(GPP_E16) + Sleep(2) /* reset pulse width */ + + /* Pull RST low */ + CTXS(GPP_E15) + Sleep(1) /* t2 */ + + /* Pull RST high */ + STXS(GPP_E15) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(1) /* Clock 1 */ + + /* Pull RST low */ + CTXS(GPP_E15) + + /* Pull PWREN low */ + CTXS(GPP_E16) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index d4fb7a4..6e7ccd1 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -27,6 +27,9 @@ #include <soc/intel/common/block/acpi/acpi/ipu.asl> } + /* Camera */ + #include <acpi/mipi_camera.asl> + #if CONFIG(CHROMEOS) /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/47497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 Gerrit-Change-Number: 47497 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Configure Camera related GPIO as per schematics
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47496 ) Change subject: mb/intel/adlrvp: Configure Camera related GPIO as per schematics ...................................................................... mb/intel/adlrvp: Configure Camera related GPIO as per schematics Configure RST and PWR_EN signals for both WFC and UFC Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 9 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/47496/1 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 9f96620..bf1dad2 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -26,8 +26,6 @@ PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* M.2 SSD_2 Reset */ PAD_CFG_GPO(GPP_H0, 1, PLTRST), - /* CAM1-IRQ */ - PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* CAM_STROBE */ PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Audio Codec INT N */ @@ -182,15 +180,6 @@ /* I2S0_RXD */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* I2S1_SCLK */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* I2S1_SFRM */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* I2S1_TXD */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* I2S1_RXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - /* I2S2_SCLK */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SFRM */ @@ -273,6 +262,15 @@ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/47496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec Gerrit-Change-Number: 47496 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Update GPIO configuration as per schematics
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47495 ) Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ...................................................................... mb/intel/adlrvp: Update GPIO configuration as per schematics Configure I2C related GPIO as per ADL-P Schematics Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 12 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47495/1 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index f91b94f..9f96620 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -134,22 +134,16 @@ /* SPI_MOSI(2) */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), - /* SPI_MIS0(0) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI_MIS0(1) */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* SPI_MIS0(2) */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), - /* SPI_CLK(0) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI_CLK(1) */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* SPI_CLK(2) */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), - /* SPI_CS(0, 0) */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI_CS(0, 1) */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPI_CS(1, 0) */ @@ -158,34 +152,26 @@ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), /* I2C_SCL(0) */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* I2C_SCL(2) */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(3) */ + /* I2C_SCL(1) */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* I2C_SCL(6) */ - PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), - /* I2C_SCL(7) */ - PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), /* I2C_SDA(0) */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* I2C_SDA(2) */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(3) */ + /* I2C_SDA(1) */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* I2C_SDA(6) */ - PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), - /* I2C_SDA(7) */ - PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), -- To view, visit https://review.coreboot.org/c/coreboot/+/47495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e Gerrit-Change-Number: 47495 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/intel/adlrvp: Enable PCH PCIE device over x1 slot
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48080 ) Change subject: mainboard/intel/adlrvp: Enable PCH PCIE device over x1 slot ...................................................................... mainboard/intel/adlrvp: Enable PCH PCIE device over x1 slot List of changes: 1. Enable Root Port 8 aka 0:0x1c:7 2. Assign free running clock for RP8 3. Driven OEB 7:GPP_A7 and OEB 6:GPP_E5 low TEST=Able to detect PCIE SD card over x1 slot localhost ~ # dmesg | grep mmc [ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA [ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8 [ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB [ 3.849158] mmcblk0: p1 Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/gpio.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48080/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 80edb92..f2f768a 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -51,6 +51,12 @@ register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1" + # Enable PCH PCIE RP 8 using free running CLK (0x80) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieRpClkReqDetect[7]" = "1" + # Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" register "PcieClkSrcClkReq[1]" = "1" @@ -245,7 +251,7 @@ device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7 - device pci 1c.7 off end # RP8 + device pci 1c.7 on end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 device pci 1d.2 on end # RP11 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 89e6f58..4cb8c3a 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -72,6 +72,10 @@ PAD_CFG_GPO(GPP_B4, 1, PLTRST), /* M.2_PCH_SSD_PWREN */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + /* SRCCLK_OEB6 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* M.2_SSD_PDET_R */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/48080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Gerrit-Change-Number: 48080 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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