coreboot-gerrit December 2020

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Change in coreboot[master]: drivers/intel/fsp2_0/notify: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48168 ) Change subject: drivers/intel/fsp2_0/notify: Fix compilation under x86_64 ...................................................................... drivers/intel/fsp2_0/notify: Fix compilation under x86_64 Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48168/1 diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf12..ee04630 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -57,7 +57,7 @@ static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase phase = (uint32_t)arg; + enum fsp_notify_phase phase = (uint32_t)(uintptr_t)arg; display_mtrrs(); -- To view, visit https://review.coreboot.org/c/coreboot/+/48168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Gerrit-Change-Number: 48168 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/systemagent: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48167 ) Change subject: soc/intel/common/block/systemagent: Fix compilation on x86_64 ...................................................................... soc/intel/common/block/systemagent: Fix compilation on x86_64 Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/systemagent/systemagent_early.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48167/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 53d6077..ca11ee6 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -95,8 +95,8 @@ base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; if (base >> 32) - write32((void *)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Gerrit-Change-Number: 48167 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/reg_script: Add cast to fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48166 ) Change subject: lib/reg_script: Add cast to fix compilation on x86_64 ...................................................................... lib/reg_script: Add cast to fix compilation on x86_64 Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/reg_script.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48166/1 diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e0ae68c..bad9d9c 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -150,11 +150,11 @@ switch (step->size) { case REG_SCRIPT_SIZE_8: - return read8((u8 *)step->reg); + return read8((u8 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_16: - return read16((u16 *)step->reg); + return read16((u16 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_32: - return read32((u32 *)step->reg); + return read32((u32 *)(uintptr_t)step->reg); } return 0; } @@ -165,13 +165,13 @@ switch (step->size) { case REG_SCRIPT_SIZE_8: - write8((u8 *)step->reg, step->value); + write8((u8 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_16: - write16((u16 *)step->reg, step->value); + write16((u16 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_32: - write32((u32 *)step->reg, step->value); + write32((u32 *)(uintptr_t)step->reg, step->value); break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb Gerrit-Change-Number: 48166 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by Paul Fagerburg (Code Review) 01 Dec '20

01 Dec '20

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48154 ) Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... mb/intel/jslrvp: Modify the flash layout for fsp debug build Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 25 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, but someone else must approve Ronak Kanabar: Looks good to me, approved diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 57be7f1..e4e0b24 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,37 +1,38 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x600000 { + SI_ALL@0x0 0x381000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x57F000 + SI_ME@0x81000 0x300000 } - SI_BIOS@0x600000 0xA00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x12ffc0 - RW_FWID_A@0x13ffc0 0x40 - ME_RW_A(CBFS)@0x140000 0x190000 + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x12ffc0 - RW_FWID_B@0x13ffc0 0x40 - ME_RW_B(CBFS)@0x140000 0x190000 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x849000 0x36000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } - RW_LEGACY(CBFS)@0x5d0000 0x30000 - WP_RO@0x600000 0x400000 { + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: Mark RW_MRC_CACHE as "Preserve"
by Martin Roth (Code Review) 01 Dec '20

01 Dec '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47776 ) Change subject: mb/google/zork: Mark RW_MRC_CACHE as "Preserve" ...................................................................... mb/google/zork: Mark RW_MRC_CACHE as "Preserve" AGESA checks to make sure that the firmware version reading the MRC cache is the same version that wrote it, so it doesn't need to be erased during a firmware update. BUG=b:173724014 TEST=Flash firmware to DUT, update firmware, check RW_MRC_CACHE was not erased BRANCH=Zork Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca --- M src/mainboard/google/zork/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47776/1 diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 7c2b95b..be43e8a 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,6 +1,6 @@ FLASH@0xFF000000 16M { SI_BIOS { - RW_MRC_CACHE 64K + RW_MRC_CACHE(PRESERVE) 64K RW_SECTION_A 3M { VBLOCK_A 8K FW_MAIN_A(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca Gerrit-Change-Number: 47776 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/sipi: Add x86_64 support
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45187 ) Change subject: cpu/x86/sipi: Add x86_64 support ...................................................................... cpu/x86/sipi: Add x86_64 support Enter long mode on secondary APs. Tested on Lenovo T410 with additional x86_64 patches. Tested on HP Z220 with additional x86_64 patches. Still boots on x86_32. Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/sipi_vector.S 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45187/1 diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc..7025517 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -16,7 +16,12 @@ #endif #include <cpu/x86/msr.h> +#if defined(__RAMSTAGE__) +#include <arch/ram_segs.h> +#else #include <arch/rom_segs.h> +#endif + setup_longmode: /* Get page table address */ @@ -42,7 +47,12 @@ movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ +#if defined(__RAMSTAGE__) + ljmp $RAM_CODE_SEG64, $__longmode_start +#else ljmp $ROM_CODE_SEG64, $__longmode_start + +#endif .code64 __longmode_start: diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..cde5532 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -5,6 +5,8 @@ #include <cpu/x86/msr.h> #include <arch/ram_segs.h> +#define __RAMSTAGE__ + /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ @@ -192,11 +194,24 @@ mov %eax, %cr4 #endif +#ifdef __x86_64__ + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + + mov %rsi, %rdi /* cpu_num */ + + movl c_handler, %eax + call *%rax +#else /* c_handler(cpu_num), preserve proper stack alignment */ sub $12, %esp push %esi /* cpu_num */ + mov c_handler, %eax call *%eax +#endif + + halt_jump: hlt jmp halt_jump -- To view, visit https://review.coreboot.org/c/coreboot/+/45187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0 Gerrit-Change-Number: 45187 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/mal10: Use the system library for headers
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48141 ) Change subject: mb/kontron/mal10: Use the system library for headers ...................................................................... mb/kontron/mal10: Use the system library for headers Use the system library for header files instead of relative filesystem paths. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123 --- M src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c M src/mainboard/kontron/mal10/variants/mal10/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/48141/1 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c index f1f93bf..674b209 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/carrier/gpio.h" +#include <carrier/gpio.h> static const struct pad_config gpio_table[] = { PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c index 1e88e38..3986776 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/gpio.c +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/variant/gpio.h" +#include <variant/gpio.h> static const struct pad_config gpio_table[] = { /* SPI */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123 Gerrit-Change-Number: 48141 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/mal10/Kconfig: Reorder selects alphabetically
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48140 ) Change subject: mb/kontron/mal10/Kconfig: Reorder selects alphabetically ...................................................................... mb/kontron/mal10/Kconfig: Reorder selects alphabetically Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8 --- M src/mainboard/kontron/mal10/Kconfig 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48140/1 diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig index 1705b91..f53746d 100644 --- a/src/mainboard/kontron/mal10/Kconfig +++ b/src/mainboard/kontron/mal10/Kconfig @@ -2,18 +2,18 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_NCT7802Y + select EC_KONTRON_KEMPLD select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT - select SOC_INTEL_APOLLOLAKE - select BOARD_ROMSIZE_KB_16384 - select ONBOARD_VGA_IS_PRIMARY - select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_CRB_TPM - select EC_KONTRON_KEMPLD - select DRIVERS_I2C_NCT7802Y + select MAINBOARD_HAS_LIBGFXINIT + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_APOLLOLAKE config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/48140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8 Gerrit-Change-Number: 48140 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Add missing trailing slashes
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48137 ) Change subject: MAINTAINERS: Add missing trailing slashes ...................................................................... MAINTAINERS: Add missing trailing slashes Add missing trailing slashes so that gerrit recognizes maintainers correctly. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797 --- M MAINTAINERS 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/48137/1 diff --git a/MAINTAINERS b/MAINTAINERS index 4f643b2..880c4aa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -233,19 +233,19 @@ GETAC P470 MAINBOARD M: Patrick Georgi <patrick(a)georgi.software> S: Maintained -F: src/mainboard/getac/p470 +F: src/mainboard/getac/p470/ GIGABYTE GA-G41M-ES2L MAINBOARD M: Damien Zammit <damien(a)zamaudio.com> S: Odd Fixes -F: src/mainboard/gigabyte/ga-g41m-es2l +F: src/mainboard/gigabyte/ga-g41m-es2l/ GIGABYTE GA-H61M SERIES MAINBOARDS M: Angel Pons <th3fanbus(a)gmail.com> S: Maintained -F: src/mainboard/gigabyte/ga-h61m-series +F: src/mainboard/gigabyte/ga-h61m-series/ @@ -273,7 +273,7 @@ INTEL D510MO MAINBOARD M: Damien Zammit <damien(a)zamaudio.com> S: Odd Fixes -F: src/mainboard/intel/d510mo +F: src/mainboard/intel/d510mo/ INTEL STRAGO MAINBOARD M: Hannah Williams <hannah.williams(a)intel.com> @@ -314,7 +314,7 @@ M: Piotr Król <piotr.krol(a)3mdeb.com> M: Michał Żygowski <michal.zygowski(a)3mdeb.com> S: Maintained -F: src/mainboard/libretrend/lt1000 +F: src/mainboard/libretrend/lt1000/ OCP DELTALAKE MAINBOARD @@ -325,7 +325,7 @@ M: Ryback Hung <<Ryback.Hung(a)quantatw.com> M: Bryant Ou <Bryant.Ou(a)quantatw.com> S: Supported -F: src/mainboard/ocp/deltalake +F: src/mainboard/ocp/deltalake/ OCP TIOGAPASS MAINBOARD M: Jonathan Zhang <jonzhang(a)fb.com> @@ -335,7 +335,7 @@ M: Ryback Hung <<Ryback.Hung(a)quantatw.com> M: Bryant Ou <Bryant.Ou(a)quantatw.com> S: Maintained -F: src/mainboard/ocp/tiogapass +F: src/mainboard/ocp/tiogapass/ @@ -375,14 +375,14 @@ M: Christian Walter <christian.walter(a)9elements.com> M: Patrick Rudolph <patrick.rudolph(a)9elements.com> S: Maintained -F: src/mainboard/prodrive/hermes +F: src/mainboard/prodrive/hermes/ PURISM MAINBOARDS M: Matt DeVillier <matt.devillier(a)puri.sm> S: Supported -F: src/mainboard/purism +F: src/mainboard/purism/ @@ -556,8 +556,8 @@ M: Felix Held <felix-coreboot(a)felixheld.de> M: Jason Glenesk <jason.glenesk(a)gmail.com> S: Maintained -F: src/soc/amd/picasso -F: src/vendorcode/amd/fsp/picasso +F: src/soc/amd/picasso/ +F: src/vendorcode/amd/fsp/picasso/ INTEL APOLLOLAKE_SOC M: Andrey Petrov <andrey.petrov(a)gmail.com> @@ -569,8 +569,8 @@ M: Michał Żygowski <michal.zygowski(a)3mdeb.com> M: Frans Hendriks <fhendriks(a)eltan.com> S: Maintained -F: /src/soc/intel/braswell -F: /src/vendorcode/intel/fsp/fsp1_1/braswell +F: /src/soc/intel/braswell/ +F: /src/vendorcode/intel/fsp/fsp1_1/braswell/ INTEL Xeon Sacalable Processor Family M: Jonathan Zhang <jonzhang(a)fb.com> @@ -581,13 +581,13 @@ M: Bryant Ou <Bryant.Ou(a)quantatw.com> S: Supported F: src/soc/intel/xeon_sp -F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp -F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp +F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ MEDIATEK SOCS M: Hung-Te Lin <hungte(a)chromium.org> S: Supported -F: src/soc/mediatek +F: src/soc/mediatek/ ORPHANED ARM SOCS S: Orphaned @@ -615,13 +615,13 @@ EXTERNAL PAYLOADS INTEGRATION M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> M: Martin Roth <gaumless(a)gmail.com> -F: payloads/external +F: payloads/external/ LINUXBOOT PAYLOAD INTEGRATION M: Christian Walter <christian.walter(a)9elements.com> M: Marcello Sylvester Bauer <info(a)marcellobauer.com> S: Supported -F: payloads/external/LinuxBoot +F: payloads/external/LinuxBoot/ ################################################################################ # Utilities @@ -751,7 +751,7 @@ M: Christian Walter <christian.walter(a)9elements.com> S: Supported F: src/drivers/*/tpm/ -F: src/security/tpm +F: src/security/tpm/ SUPERIOS & SUPERIOTOOL M: Felix Held <felix-coreboot(a)felixheld.de> @@ -769,7 +769,7 @@ M: Frans Hendriks <fhendriks(a)eltan.com> M: Wim Vervoorn <wvervoorn(a)eltan.com> S: Maintained -F: src/vendorcode/eltan +F: src/vendorcode/eltan/ MISSING: TIMERS / DELAYS -- To view, visit https://review.coreboot.org/c/coreboot/+/48137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797 Gerrit-Change-Number: 48137 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update GPIO configurations according to schematics
by Johnny Lin (Code Review) 01 Dec '20

01 Dec '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Update GPIO configurations according to schematics ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 9 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Dec 2020 13:33:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020