coreboot-gerrit December 2020

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Change in coreboot[master]: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48079 ) Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ...................................................................... mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU List of changes in SPD: 1. tCKAVGmax 2. CAS Latencies supported (First Byte) 3. CAS Latencies supported (Second Byte) 4. CAS Latencies supported (Third Byte) 5. Minimum CAS Latency (tAAmin) 6. Read and Write Latency Set options 7. FTB for tAAmin 8. FTB for tCKAVGmax 9. FTB for tCKAVGmin TEST=Able to build and boot with updated SPD. Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48079/1 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex index 17f270d..e1d338e 100644 --- a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -1,11 +1,11 @@ -23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 -48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/48079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Gerrit-Change-Number: 48079 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add support for LPDDR5
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlrvp: Add support for LPDDR5 ...................................................................... mb/intel/adlrvp: Add support for LPDDR5 This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex 5 files changed, 71 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 537e624..9cb8640 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -14,6 +14,8 @@ ADL_P_LP4_2 = 0x11, /* ADL-P DDR5 RVPs */ ADL_P_DDR5 = 0x12, + /* ADL-P LPDDR5 RVP */ + ADL_P_LP5 = 0x13, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index b203f69..80ec14a 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -44,6 +44,34 @@ .UserBd = BOARD_TYPE_MOBILE, }; +static const struct mb_cfg lp5_mem_config = { + + /* DQ byte map */ + .dq_map = { + { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, + { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, + { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, + { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, + { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, + { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, + { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, + { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + + .dq_pins_interleaved = false, + + .ect = false, /* Early Command Training */ + + .lp5_ccc_config = 0xff, + + .UserBd = BOARD_TYPE_MOBILE, +}; + static const struct mb_cfg ddr5_mem_config = { /* Baseboard uses only 100ohm Rcomp resistors */ .rcomp_resistor = {100, 100, 100}, @@ -71,6 +99,8 @@ return &ddr4_mem_config; case ADL_P_DDR5: return &ddr5_mem_config; + case ADL_P_LP5: + return &lp5_mem_config; default: die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 672c597..2f03cb4 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -31,7 +31,7 @@ int board_id = get_board_id(); const bool half_populated = false; - const struct spd_info lpddr4_spd_info = { + const struct spd_info lp4_lp5_spd_info = { .read_type = READ_SPD_CBFS, .spd_spec.spd_index = get_spd_index(), }; @@ -56,7 +56,8 @@ break; case ADL_P_LP4_1: case ADL_P_LP4_2: - memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); + case ADL_P_LP5: + memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 1218a76..10ce42e 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -1,4 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = adlrvp_lp4 #0b000 -SPD_SOURCES += empty # 0b001 +SPD_SOURCES = adlrvp_lp4 # 0b000 +SPD_SOURCES += empty # 0b001 +SPD_SOURCES += empty # 0b002 +SPD_SOURCES += adlrvp_lp5 # 0b003 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex new file mode 100644 index 0000000..2f2a31a --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by Maulik V Vaghela (Code Review) 01 Dec '20

01 Dec '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48154 ) Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Dec 2020 07:41:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Alloc .bss.* sections for "struct" file type
by Yu-Ping Wu (Code Review) 01 Dec '20

01 Dec '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47903 ) Change subject: Makefile.inc: Alloc .bss.* sections for "struct" file type ...................................................................... Makefile.inc: Alloc .bss.* sections for "struct" file type When the global variable of a "struct" CBFS file is zero (for example, CB:47696), the binary will appear in the .bss.* section in the ELF file (instead of .data). This results in an empty binary file added to CBFS, so that file size check will fail when reading it at runtime. BUG=b:173751635 TEST=emerge-asurada coreboot TEST=Check sdram-lpddr4x-KMDP6001DA-B425-4GB is non-empty in CBFS BRANCH=none Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47903/1 diff --git a/Makefile.inc b/Makefile.inc index 9273961..f3493d8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -338,7 +338,7 @@ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ printf " CC+STRIP $(@)\n"; \ $(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \ - $(OBJCOPY_ramstage) -O binary $(2).tmp $(2); \ + $(OBJCOPY_ramstage) -O binary -set-section-flags .bss.*=alloc,contents,load $(2).tmp $(2); \ rm -f $(2).tmp) \ $(eval DEPENDENCIES += $(2).d) -- To view, visit https://review.coreboot.org/c/coreboot/+/47903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04 Gerrit-Change-Number: 47903 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/solidrun/solidpc: Do initial commit
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Patch Set 12: Any updates on this? -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Tue, 01 Dec 2020 06:37:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by V Sowmya (Code Review) 01 Dec '20

01 Dec '20

Hello build bot (Jenkins), Maulik V Vaghela, Krishna P Bhat D, Ronak Kanabar, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48154 to look at the new patch set (#4). Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... mb/intel/jslrvp: Modify the flash layout for fsp debug build Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48154/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by Ronak Kanabar (Code Review) 01 Dec '20

01 Dec '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48154 ) Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Dec 2020 05:40:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by V Sowmya (Code Review) 01 Dec '20

01 Dec '20

Hello build bot (Jenkins), Maulik V Vaghela, Krishna P Bhat D, Ronak Kanabar, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48154 to look at the new patch set (#3). Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... mb/intel/jslrvp: Modify the flash layout for fsp debug build Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled Coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48154/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by Ronak Kanabar (Code Review) 01 Dec '20

01 Dec '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48154 ) Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Dec 2020 05:23:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add ACPI support for camera in waddledee
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42205 ) Change subject: mb/google/dedede: Add ACPI support for camera in waddledee ...................................................................... mb/google/dedede: Add ACPI support for camera in waddledee 1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI9734 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledee board and able to capture image using world facing camera and user facing camera. Change-Id: I3f6b490832d2c34c86512384eb7470f13a212a66 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl 6 files changed, 559 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/42205/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 25ad61f..b6e1d64 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -18,6 +18,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_WHEELIE bool "Wheelie" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl new file mode 100644 index 0000000..90c7d58 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA0, Zero) + + /* Method to turn off Power Rails */ + Method (POFF, 0) + { + /* Disable PP1200 lane */ + CTXS(GPP_D14) + /* Disable PP2800 lane */ + CTXS(GPP_D13) + } + + Method (PON, 0) + { + /* Enable PP2800 lane */ + STXS(GPP_D13) + /* Enable PP1200 lane */ + STXS(GPP_D14) + } + + PowerResource (FCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(1, 1) /* Clock 1, 19.2MHz */ + IF(!STA1) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D12) + Sleep(5) /* 5 us */ + /* Deassert Reset */ + STXS(GPP_D12) + Sleep(5) /* 5 us */ + STA0 = 1 + } + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(1) /* Clock 1 */ + /* Assert Reset */ + CTXS(GPP_D12) + IF(!STA1) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA0 = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA0) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hadware ID */ + + Name (_UID, 0x03) /* _UID: Unique ID */ + + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ + { + FCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package(0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl new file mode 100644 index 0000000..3e76197 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA1, Zero) + + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(0, 1) /* Clock 0, 19.2MHz */ + /* Check if another sensor is ON */ + IF(!STA0) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D15) + Sleep(5) /* 5 us */ + /* DeAssert Reset */ + STXS(GPP_D15) + Sleep(5) /* 5 us */ + STA1 = 1 + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(0) /* Clock 0 */ + /* Assert Reset */ + CTXS(GPP_D15) + IF(!STA0) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA1 = 0 + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA1) + } + } + + Device(CAM1) + { + Name (_HID, "OVTI9734") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 9734 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x0ABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl new file mode 100644 index 0000000..51b4ebc --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..89ccb48 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x01) + { + One, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..8d37674 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) /* _ADR: Address */ + + Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f6b490832d2c34c86512384eb7470f13a212a66 Gerrit-Change-Number: 42205 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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