coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Support VBT for Drawman
by Karthik Ramasubramanian (Code Review) 02 Dec '20

02 Dec '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48192 ) Change subject: mb/google/dedede/var/drawcia: Support VBT for Drawman ...................................................................... mb/google/dedede/var/drawcia: Support VBT for Drawman Default VBT supports only integrated Display port. Drawman supports a HDMI port and hence support a separate VBT for Drawman. BUG=b:161190931 BRANCH=dedede TEST=Build and boot to OS in Drawlat and Drawman. Change-Id: I8895cc67d87428eddb31328f1e3a90c346b54533 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/variant.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/48192/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index 88e9de7..b5effbb 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> +#include <drivers/intel/gma/opregion.h> #include <fw_config.h> #include <sar.h> @@ -13,3 +14,11 @@ return filename; } + +const char *mainboard_vbt_filename(void) +{ + if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI))) + return "vbt_drawman.bin"; + + return "vbt.bin"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8895cc67d87428eddb31328f1e3a90c346b54533 Gerrit-Change-Number: 48192 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add Daughter-board FW_CONFIG in devicetree
by Karthik Ramasubramanian (Code Review) 02 Dec '20

02 Dec '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48191 ) Change subject: mb/google/dedede: Add Daughter-board FW_CONFIG in devicetree ...................................................................... mb/google/dedede: Add Daughter-board FW_CONFIG in devicetree Add daughter-board ports bit field and mask in devicetree. BUG=b:161190931 BRANCH=dedede TEST=Build and boot to OS in drawlat & drawman. Change-Id: Ibbd86fc8c3e44a7d1703b8ce75c48881226545c9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/48191/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index ce28123..2785ad0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,4 +1,11 @@ fw_config + field DB_PORTS 0 3 + option DB_PORTS_NONE 0 + option DB_PORTS_2C_2A 1 + option DB_PORTS_1C_LTE 2 + option DB_PORTS_1A_HDMI 3 + option DB_PORTS_1C_1A 4 + end field TABLETMODE 10 option TABLETMODE_DISABLED 0 option TABLETMODE_ENABLED 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbd86fc8c3e44a7d1703b8ce75c48881226545c9 Gerrit-Change-Number: 48191 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04
by Ronak Kanabar (Code Review) 02 Dec '20

02 Dec '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47862 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04 ...................................................................... vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04 The headers added are generated as per FSP v2385_04. Previous FSP version was 2385_02. Changes Include: - add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and RampDown UPDs in Fsps.h TEST=Build and boot JSLRVP Change-Id: I477af05c34f767a43990670a711992641eaf6000 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 1 file changed, 39 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/47862/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index 34c29dc..dd7db9d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -981,9 +981,23 @@ **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x048D - Reserved +/** Offset 0x048D - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. 0: False; 1: True + $EN_DIS **/ - UINT8 Reserved21[21]; + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x0492 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5]; + +/** Offset 0x0497 - Reserved +**/ + UINT8 Reserved21[11]; /** Offset 0x04A2 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1079,9 +1093,30 @@ **/ UINT32 CpuMpHob; -/** Offset 0x04F4 - Reserved +/** Offset 0x04F4 - Pre Wake Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled. Range 0-255 0. **/ - UINT8 Reserved24[16]; + UINT8 PreWake; + +/** Offset 0x04F5 - Ramp Up Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampUp; + +/** Offset 0x04F6 - Ramp Down Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampDown; + +/** Offset 0x04F7 - Reserved +**/ + UINT8 Reserved24[13]; /** Offset 0x0504 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this -- To view, visit https://review.coreboot.org/c/coreboot/+/47862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I477af05c34f767a43990670a711992641eaf6000 Gerrit-Change-Number: 47862 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Update SPD table for Shuboz
by Kane Chen (Code Review) 02 Dec '20

02 Dec '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47902 ) Change subject: mb/google/zork: Update SPD table for Shuboz ...................................................................... mb/google/zork: Update SPD table for Shuboz Add SPD support in Shuboz memory table as follow: 1. MICRON MT40A512M16TB-062E:J 2. HYNIX H5AN8G6NCJR-XNC 3. MICRON MT40A1G16KD-062E:E 4. SAMSUNG K4AAG165WA-BCWE BUG=b:none BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 --- M src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc M src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt 3 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47902/1 diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc index 3edeb96..87b5aa97 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = ddr4-spd-empty.hex +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 2(0b0010) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt index fa24790..8019b2e 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt @@ -1 +1,5 @@ DRAM Part Name ID to assign +MT40A512M16TB-062E:J 0 (0000) +H5AN8G6NCJR-XNC 1 (0001) +MT40A1G16KD-062E:E 2 (0010) +K4AAG165WA-BCWE 3 (0011) diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt index 106a705..f2240fd 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt @@ -7,3 +7,7 @@ # See util/spd_tools/ddr4/README.md for more details and instructions. # Part Name, Fixed ID (optional) +MT40A512M16TB-062E:E, 0 +H5AN8G6NCJR-XNC, 1 +MT40A1G16KD-062E:E, 2 +K4AAG165WA-BCWE, 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 Gerrit-Change-Number: 47902 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/lantis: Configure IRQs as level triggered for HI...
by Tony Huang (Code Review) 02 Dec '20

02 Dec '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48193 ) Change subject: mb/google/dedede/var/lantis: Configure IRQs as level triggered for HID over I2C ...................................................................... mb/google/dedede/var/lantis: Configure IRQs as level triggered for HID over I2C Config HID-I2C device to level trigger. As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:171546871 TEST=emerge-dedede coreboot Change-Id: If8be25f591715765a99920b79482c862b1cc7079 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/lantis/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/48193/1 diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index 2933b1a..1b87bcb 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -93,7 +93,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "50" @@ -107,7 +107,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "120" -- To view, visit https://review.coreboot.org/c/coreboot/+/48193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8be25f591715765a99920b79482c862b1cc7079 Gerrit-Change-Number: 48193 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/car.ld: Check for out of bound on no-XIP stages
by Arthur Heymans (Code Review) 02 Dec '20

02 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36623 ) Change subject: arch/x86/car.ld: Check for out of bound on no-XIP stages ...................................................................... arch/x86/car.ld: Check for out of bound on no-XIP stages Check that stages running in CAR have their start and end in CAR. Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36623/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6ccbd8c..e68beb3 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -119,4 +119,9 @@ #endif #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); +#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE) +_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !"); +_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!"); +#endif + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Gerrit-Change-Number: 36623 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: edist-test: Fix _Static_assert missing message string
by Patrick Georgi (Code Review) 02 Dec '20

02 Dec '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48151 ) Change subject: edist-test: Fix _Static_assert missing message string ...................................................................... edist-test: Fix _Static_assert missing message string Older GCCs don't support _Static_assert without a message string as the second argument. AFAICT _Static_assert with two arguments is in C11 but omitting the message argument is an extension. The tests appear to be built with the system gcc rather than our crossgcc so that's probably why this was not cought by CI. Change-Id: I41fd0ffc42ded8b6d145c3ec30cc7407a78b9a43 Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48151 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M tests/include/lib/edid-test.h 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/tests/include/lib/edid-test.h b/tests/include/lib/edid-test.h index 073905d..8327748 100644 --- a/tests/include/lib/edid-test.h +++ b/tests/include/lib/edid-test.h @@ -43,7 +43,8 @@ uint8_t checksum; } __packed; -_Static_assert(sizeof(struct edid_raw) == 128); +_Static_assert(sizeof(struct edid_raw) == 128, + "assert failed: edid_raw size mismatch"); #define EDID_HEADER_RAW { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 } #define EDID_HEADER_INVALID_RAW { 0, 0, 0, 0, 0, 0, 0, 0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/48151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41fd0ffc42ded8b6d145c3ec30cc7407a78b9a43 Gerrit-Change-Number: 48151 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Gröber (dxld) <coreboot(a)dxld.at> Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1003143 Gerrit-MessageType: merged

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Change in coreboot[master]: edist-test: Fix _Static_assert missing message string
by Patrick Georgi (Code Review) 02 Dec '20

02 Dec '20

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Change in coreboot[master]: edist-test: Fix _Static_assert missing message string
by Patrick Georgi (Code Review) 02 Dec '20

02 Dec '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48151 ) Change subject: edist-test: Fix _Static_assert missing message string ...................................................................... Patch Set 1: > Patch Set 1: > > This is a fix for https://review.coreboot.org/c/coreboot/+/46817. I'm not sure if there's any tags I should be adding to the commit message to express that? No need to mark anything like that: whoever wants to know where this is coming from can look at git history. The only thing may be to add the original author of the line as reviewer so they become aware of such additional constraints, and Gerrit _usually_ does a good job of adding them automatically. -- To view, visit https://review.coreboot.org/c/coreboot/+/48151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41fd0ffc42ded8b6d145c3ec30cc7407a78b9a43 Gerrit-Change-Number: 48151 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Gröber (dxld) <coreboot(a)dxld.at> Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1003143 Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 02 Dec 2020 10:38:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: mediatek/mt8192/spm.c: Use mtlib_load_and_run API
by Yidi Lin (Code Review) 02 Dec '20

02 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47897 ) Change subject: WIP: mediatek/mt8192/spm.c: Use mtlib_load_and_run API ...................................................................... WIP: mediatek/mt8192/spm.c: Use mtlib_load_and_run API Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Ie40e5b62bbaa738cd38312563e81a23443044a64 --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 32 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47897/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index b2d2d47..5e879ab 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -5,11 +5,13 @@ #include <console/console.h> #include <delay.h> #include <device/mmio.h> +#include <soc/mtlib_common.h> #include <soc/spm.h> #include <soc/symbols.h> #include <timer.h> #define SPMFW_HEADER_SIZE 16 +#define SPM_FW_FILE "spm_firmware.bin" static struct pwr_ctrl spm_init_ctrl = { /* Auto-gen Start */ @@ -491,22 +493,14 @@ write32(&mtk_spm->pcm_pwr_io_en, 0); } -static int spm_load_firmware(struct dyna_load_pcm *pcm) +static void spm_parse_firmware(struct mtlib_fw_prop *fw) { - struct stopwatch sw; - const char *file_name = "spm_firmware.bin"; size_t file_size, copy_size; int offset; u16 firmware_size; - stopwatch_init(&sw); - - file_size = cbfs_boot_load_file(file_name, _dram_dma, - REGION_SIZE(dram_dma), CBFS_TYPE_RAW); - if (file_size == 0) { - printk(BIOS_ERR, "SPM binary %s not found\n", file_name); - return -1; - } + struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)fw->priv; + file_size = fw->size; /* * spmfw layout: @@ -519,28 +513,25 @@ /* firmware size */ offset = 0; copy_size = sizeof(firmware_size); - memcpy(&firmware_size, _dram_dma + offset, copy_size); + memcpy(&firmware_size, fw->buf + offset, copy_size); printk(BIOS_DEBUG, "SPM: binary array size = %#x\n", firmware_size); /* binary */ offset = SPMFW_HEADER_SIZE; /* binary start offset */ copy_size = firmware_size * sizeof(u32); assert(offset < file_size); - pcm->buf = (u8 *)(_dram_dma + offset); + pcm->buf = (u8 *)(fw->buf + offset); /* descriptor */ offset += copy_size; assert(offset < file_size); copy_size = sizeof(pcm->desc); - memcpy(&pcm->desc, _dram_dma + offset, copy_size); + memcpy(&pcm->desc, fw->buf + offset, copy_size); /* version */ offset += copy_size; assert(offset < file_size); - printk(BIOS_INFO, "spmfw (version %s) loaded in %ld msecs\n", - _dram_dma + offset, stopwatch_duration_msecs(&sw)); - - return 0; + printk(BIOS_INFO, "SPM: spmfw (version %s)\n", (u8 *)fw->buf + offset); } static void spm_set_wakeup_event(struct pwr_ctrl *pwrctrl) @@ -637,6 +628,23 @@ udelay(SPM_INIT_DONE_US); } +static void reset_spm(struct mtlib_fw_prop *fw) +{ + struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)fw->priv; + + spm_parse_firmware(fw); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcm); + spm_init_pcm_register(); + spm_set_wakeup_event(&spm_init_ctrl); + spm_kick_pcm_to_run(&spm_init_ctrl); +} + +static struct mtlib_fw_prop spm = { + .name = SPM_FW_FILE, + .reset = reset_spm, +}; + int spm_init(void) { struct dyna_load_pcm pcm; @@ -648,17 +656,15 @@ spm_set_power_control(&spm_init_ctrl); spm_set_sysclk_settle(); - if (spm_load_firmware(&pcm)) { - printk(BIOS_ERR, "SPM: firmware is not ready\n"); + spm.buf = _dram_dma; + spm.buf_size = REGION_SIZE(dram_dma); + spm.priv = (void *)&pcm; + + if (mtlib_load_and_run(&spm)) { + printk(BIOS_ERR, "%s() failed\n", __func__); return -1; } - spm_reset_and_init_pcm(); - spm_kick_im_to_fetch(&pcm); - spm_init_pcm_register(); - spm_set_wakeup_event(&spm_init_ctrl); - spm_kick_pcm_to_run(&spm_init_ctrl); - printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n", __func__, stopwatch_duration_msecs(&sw), read32(&mtk_spm->md32pcm_pc)); -- To view, visit https://review.coreboot.org/c/coreboot/+/47897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie40e5b62bbaa738cd38312563e81a23443044a64 Gerrit-Change-Number: 47897 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020