Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47862 )
Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04
......................................................................
vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04
The headers added are generated as per FSP v2385_04.
Previous FSP version was 2385_02.
Changes Include:
- add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and
RampDown UPDs in Fsps.h
TEST=Build and boot JSLRVP
Change-Id: I477af05c34f767a43990670a711992641eaf6000
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
1 file changed, 39 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/47862/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
index 34c29dc..dd7db9d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
@@ -981,9 +981,23 @@
**/
UINT8 AcousticNoiseMitigation;
-/** Offset 0x048D - Reserved
+/** Offset 0x048D - Disable Fast Slew Rate for Deep Package C States for VR domains
+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+ feature enabled. <b>0: False</b>; 1: True
+ $EN_DIS
**/
- UINT8 Reserved21[21];
+ UINT8 FastPkgCRampDisable[5];
+
+/** Offset 0x0492 - Slew Rate configuration for Deep Package C States for VR domains
+ Slew Rate configuration for Deep Package C States for VR domains based on Acoustic
+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+ UINT8 SlowSlewRate[5];
+
+/** Offset 0x0497 - Reserved
+**/
+ UINT8 Reserved21[11];
/** Offset 0x04A2 - AcLoadline
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
@@ -1079,9 +1093,30 @@
**/
UINT32 CpuMpHob;
-/** Offset 0x04F4 - Reserved
+/** Offset 0x04F4 - Pre Wake Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled. Range 0-255 <b>0</b>.
**/
- UINT8 Reserved24[16];
+ UINT8 PreWake;
+
+/** Offset 0x04F5 - Ramp Up Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled.Range 0-255 <b>0</b>.
+**/
+ UINT8 RampUp;
+
+/** Offset 0x04F6 - Ramp Down Randomization time
+ PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down
+ randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
+ is enabled.Range 0-255 <b>0</b>.
+**/
+ UINT8 RampDown;
+
+/** Offset 0x04F7 - Reserved
+**/
+ UINT8 Reserved24[13];
/** Offset 0x0504 - PpinSupport to view Protected Processor Inventory Number
Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I477af05c34f767a43990670a711992641eaf6000
Gerrit-Change-Number: 47862
Gerrit-PatchSet: 1
Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com>
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Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47902 )
Change subject: mb/google/zork: Update SPD table for Shuboz
......................................................................
mb/google/zork: Update SPD table for Shuboz
Add SPD support in Shuboz memory table as follow:
1. MICRON MT40A512M16TB-062E:J
2. HYNIX H5AN8G6NCJR-XNC
3. MICRON MT40A1G16KD-062E:E
4. SAMSUNG K4AAG165WA-BCWE
BUG=b:none
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com>
Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050
---
M src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
M src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
M src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
3 files changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47902/1
diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
index 3edeb96..87b5aa97 100644
--- a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
+++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
@@ -1,5 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-or-later
## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-SPD_SOURCES = ddr4-spd-empty.hex
+SPD_SOURCES =
+SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J
+SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC
+SPD_SOURCES += ddr4-spd-7.hex # ID = 2(0b0010) Parts = MT40A1G16KD-062E:E
+SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE
diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
index fa24790..8019b2e 100644
--- a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
+++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
@@ -1 +1,5 @@
DRAM Part Name ID to assign
+MT40A512M16TB-062E:J 0 (0000)
+H5AN8G6NCJR-XNC 1 (0001)
+MT40A1G16KD-062E:E 2 (0010)
+K4AAG165WA-BCWE 3 (0011)
diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
index 106a705..f2240fd 100644
--- a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
+++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
@@ -7,3 +7,7 @@
# See util/spd_tools/ddr4/README.md for more details and instructions.
# Part Name, Fixed ID (optional)
+MT40A512M16TB-062E:E, 0
+H5AN8G6NCJR-XNC, 1
+MT40A1G16KD-062E:E, 2
+K4AAG165WA-BCWE, 3
--
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Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com>
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36623 )
Change subject: arch/x86/car.ld: Check for out of bound on no-XIP stages
......................................................................
arch/x86/car.ld: Check for out of bound on no-XIP stages
Check that stages running in CAR have their start and end in CAR.
Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/car.ld
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36623/1
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 6ccbd8c..e68beb3 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -119,4 +119,9 @@
#endif
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
+#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE)
+_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !");
+_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!");
+#endif
+
#endif
--
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Gerrit-Change-Number: 36623
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-MessageType: newchange
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48151 )
Change subject: edist-test: Fix _Static_assert missing message string
......................................................................
edist-test: Fix _Static_assert missing message string
Older GCCs don't support _Static_assert without a message string as the
second argument. AFAICT _Static_assert with two arguments is in C11 but
omitting the message argument is an extension.
The tests appear to be built with the system gcc rather than our
crossgcc so that's probably why this was not cought by CI.
Change-Id: I41fd0ffc42ded8b6d145c3ec30cc7407a78b9a43
Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48151
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
---
M tests/include/lib/edid-test.h
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/tests/include/lib/edid-test.h b/tests/include/lib/edid-test.h
index 073905d..8327748 100644
--- a/tests/include/lib/edid-test.h
+++ b/tests/include/lib/edid-test.h
@@ -43,7 +43,8 @@
uint8_t checksum;
} __packed;
-_Static_assert(sizeof(struct edid_raw) == 128);
+_Static_assert(sizeof(struct edid_raw) == 128,
+ "assert failed: edid_raw size mismatch");
#define EDID_HEADER_RAW { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 }
#define EDID_HEADER_INVALID_RAW { 0, 0, 0, 0, 0, 0, 0, 0 }
--
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48151 )
Change subject: edist-test: Fix _Static_assert missing message string
......................................................................
Patch Set 1: Code-Review+2
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48151 )
Change subject: edist-test: Fix _Static_assert missing message string
......................................................................
Patch Set 1:
> Patch Set 1:
>
> This is a fix for https://review.coreboot.org/c/coreboot/+/46817. I'm not sure if there's any tags I should be adding to the commit message to express that?
No need to mark anything like that: whoever wants to know where this is coming from can look at git history. The only thing may be to add the original author of the line as reviewer so they become aware of such additional constraints, and Gerrit _usually_ does a good job of adding them automatically.
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