coreboot-gerrit December 2020

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Change in coreboot[master]: mb/clevo/l140cu: Use proper indents
by Frans Hendriks (Code Review) 07 Dec '20

07 Dec '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48372 ) Change subject: mb/clevo/l140cu: Use proper indents ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150 Gerrit-Change-Number: 48372 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 07 Dec 2020 09:09:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Remove GPP_E0
by Meera Ravindranath (Code Review) 07 Dec '20

07 Dec '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48240 ) Change subject: mb/intel/adlrvp: Remove GPP_E0 ...................................................................... mb/intel/adlrvp: Remove GPP_E0 Remove the unused UART_BT_WAKE GPIO as BT is over USB. Change-Id: I638b4528fa5c4c378a1e8ff7bb88546da1513df2 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48240/1 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 8ff6fcd..1943a66 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -58,8 +58,6 @@ PAD_CFG_GPO(GPP_C5, 1, PLTRST), /* PEG_SLOT_WAKE_N */ PAD_CFG_GPI(GPP_A20, NONE, PLTRST), - /* UART_BT_WAKE_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), /* CAM CONN1 CLKEN */ PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* CPU SSD2 PWREN */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I638b4528fa5c4c378a1e8ff7bb88546da1513df2 Gerrit-Change-Number: 48240 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device: Remove unused TBT IDs for TGL and ADL
by Subrata Banik (Code Review) 07 Dec '20

07 Dec '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48394 ) Change subject: include/device: Remove unused TBT IDs for TGL and ADL ...................................................................... Patch Set 1: Hi Duncan, Do we really need this TBT PCIE RP IDs, as i couldn't see its usage into src/soc/intel/common/block/usb4/pcie.c file ? -- To view, visit https://review.coreboot.org/c/coreboot/+/48394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9ca39070ccb4d6abc18aa8c39b2660f313663f1 Gerrit-Change-Number: 48394 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Dec 2020 06:23:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Zhuohao Lee (Code Review) 07 Dec '20

07 Dec '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48194 ) Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Dec 2020 03:30:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] compress rcven coarse plots
by Angel Pons (Code Review) 06 Dec '20

06 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48387 ) Change subject: [WIP] compress rcven coarse plots ...................................................................... [WIP] compress rcven coarse plots Change-Id: I190207d85ff1b94c1a29ed4903cb07926090507a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 23 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/48387/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5c679d9..8149465 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1117,17 +1117,17 @@ return ret; } -static void print_raw_statistics(ramctr_timing *ctrl, u32 statistics[NUM_LANES][4], int sz) +static void print_raw_statistics(ramctr_timing *ctrl, u32 stats[NUM_LANES][4], int sz, int step) { printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); for (int j = 0; j < sz; j++) { - for (int i = 0; i < 32; i++) { + for (int i = 0; i < 32; i += step) { printk(BIOS_ERR, "% 5d\t", i + j * 32); int lane; FOR_ALL_LANES { - const bool pass = !!(statistics[lane][j] & 1 << i); + const bool pass = !!(stats[lane][j] & 1 << i); printk(BIOS_ERR, "%c", pass ? '.' : '#'); } printk(BIOS_ERR, "\n"); @@ -1217,27 +1217,41 @@ static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { + const int step_size = 4; + int rcven; - u32 statistics[NUM_LANES][4]; + u32 statistics[NUM_LANES][4] = { 0 }; int lane; + FOR_ALL_LANES { + MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, 0)) = 0; + MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, 1)) = 0; + } + for (u32 logic_delay = 0; logic_delay < 2; logic_delay++) { - for (rcven = 0; rcven < 64; rcven++) { + for (rcven = 0; rcven < 64; rcven += step_size) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rcven = rcven + logic_delay * 64; } program_timings(ctrl, channel); - test_rcven(ctrl, channel, slotrank); + for (int i = 0; i < step_size; i++) + test_rcven(ctrl, channel, slotrank); } FOR_ALL_LANES { - statistics[lane][logic_delay * 2 + 0] = get_stats(channel, lane, 0); - statistics[lane][logic_delay * 2 + 1] = get_stats(channel, lane, 1); + const u32 stats_a = get_stats(channel, lane, 0); + const u32 stats_b = get_stats(channel, lane, 1); + + /* Account for missing data points */ + for (int i = 0; i < step_size; i++) { + statistics[lane][logic_delay * 2 + 0] |= stats_a << i; + statistics[lane][logic_delay * 2 + 1] |= stats_b << i; + } } } printk(BIOS_ERR, "channel %d rank %d results:\n", channel, slotrank); - print_raw_statistics(ctrl, statistics, 4); + print_raw_statistics(ctrl, statistics, 4, step_size); printk(BIOS_ERR, "\n"); FOR_ALL_LANES { -- To view, visit https://review.coreboot.org/c/coreboot/+/48387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I190207d85ff1b94c1a29ed4903cb07926090507a Gerrit-Change-Number: 48387 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48371 ) Change subject: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Gerrit-Change-Number: 48371 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Dec 2020 23:42:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden
by Felix Singer (Code Review) 06 Dec '20

06 Dec '20

Hello build bot (Jenkins), Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48371 to look at the new patch set (#3). Change subject: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden ...................................................................... mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden The PCI devices P2SB and PMC are hidden by the FSP. So instead turning them off, set their state to hidden being able to allocate ressources for them. Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48371/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Gerrit-Change-Number: 48371 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Dec 2020 22:36:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Wrap UART driver by PCI device
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48293 ) Change subject: mb/prodrive/hermes: Wrap UART driver by PCI device ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/48293/4/src/mainboard/prodrive/her… File src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb: https://review.coreboot.org/c/coreboot/+/48293/4/src/mainboard/prodrive/her… PS4, Line 177: device pci 19.2 on end > > > Maybe the driver needs to be edited to make that work […] see CB:48385 -- To view, visit https://review.coreboot.org/c/coreboot/+/48293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298247276ec95b2f599f1fcd399550a51b63aff1 Gerrit-Change-Number: 48293 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Dec 2020 22:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden
by Michael Niewöhner (Code Review) 06 Dec '20

06 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48371 ) Change subject: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Gerrit-Change-Number: 48371 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Dec 2020 21:39:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020