coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

1 participants
3168 discussions

Change in coreboot[master]: nb/intel/ironlake: Introduce memmap.h
by Patrick Georgi (Code Review) 07 Dec '20

07 Dec '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48235 ) Change subject: nb/intel/ironlake: Introduce memmap.h ...................................................................... nb/intel/ironlake: Introduce memmap.h Inspired by Idca25b2e4bf65abcb and Ib275f9ad8ca9ff move all memory map definitions into a header with a common name. Change-Id: I5d8a3df4d18cad89de17d3842d28ab8695e2b139 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/northbridge/intel/ironlake/ironlake.h A src/northbridge/intel/ironlake/memmap.h 2 files changed, 24 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/48235/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 86c6054..0a0c295 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,12 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ -#define DEFAULT_HECIBAR ((u8 *)0xfed17000) - -#define IOMMU_BASE1 0xfed90000 -#define IOMMU_BASE2 0xfed91000 -#define IOMMU_BASE3 0xfed92000 -#define IOMMU_BASE4 0xfed93000 +#include "memmap.h" /* * D1:F0 PEG @@ -24,16 +19,6 @@ #define IRONLAKE_DESKTOP 1 #define IRONLAKE_SERVER 2 -/* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ - #define QUICKPATH_BUS 0xff #include <southbridge/intel/ibexpeak/pch.h> diff --git a/src/northbridge/intel/ironlake/memmap.h b/src/northbridge/intel/ironlake/memmap.h new file mode 100644 index 0000000..77ed251 --- /dev/null +++ b/src/northbridge/intel/ironlake/memmap.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__ + +#define DEFAULT_HECIBAR ((u8 *)0xfed17000) + +#define IOMMU_BASE1 0xfed90000 +#define IOMMU_BASE2 0xfed91000 +#define IOMMU_BASE3 0xfed92000 +#define IOMMU_BASE4 0xfed93000 + +/* Northbridge BARs */ +#ifndef __ACPI__ +#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ +#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ +#else +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#endif +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d8a3df4d18cad89de17d3842d28ab8695e2b139 Gerrit-Change-Number: 48235 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: nb/intel/i945: Introduce memmap.h
by Patrick Georgi (Code Review) 07 Dec '20

07 Dec '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48234 ) Change subject: nb/intel/i945: Introduce memmap.h ...................................................................... nb/intel/i945: Introduce memmap.h Inspired by Idca25b2e4bf65abcb and Ib275f9ad8ca9ff move all memory map definitions into a header with a common name. Change-Id: I32a99f70f4d2eb52367c9edfc0aa6d5da2fec03f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/northbridge/intel/i945/i945.h A src/northbridge/intel/i945/memmap.h 2 files changed, 18 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/48234/1 diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4b79b2b..e809794 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -3,16 +3,7 @@ #ifndef NORTHBRIDGE_INTEL_I945_H #define NORTHBRIDGE_INTEL_I945_H -/* Northbridge BARs */ -#define DEFAULT_X60BAR 0xfed13000 -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#include "memmap.h" #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/northbridge/intel/i945/memmap.h b/src/northbridge/intel/i945/memmap.h new file mode 100644 index 0000000..a890445 --- /dev/null +++ b/src/northbridge/intel/i945/memmap.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef NORTHBRIDGE_INTEL_I945_MEMMAP_H +#define NORTHBRIDGE_INTEL_I945_MEMMAP_H + +/* Northbridge BARs */ +#define DEFAULT_X60BAR 0xfed13000 +#ifndef __ACPI__ +#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */ +#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ +#else +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#endif +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32a99f70f4d2eb52367c9edfc0aa6d5da2fec03f Gerrit-Change-Number: 48234 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/skl: set PEG port state to auto
by Patrick Georgi (Code Review) 07 Dec '20

07 Dec '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48304 ) Change subject: soc/intel/skl: set PEG port state to auto ...................................................................... soc/intel/skl: set PEG port state to auto Setting PegXEnable to 1, statically enables the PEG ports, which blocks the SoC from going to deeper PC states. Instead, set the state to "auto" (2), so the port gets disabled, when no device was detected. Note: Currently, this only works with the AST PCI bridge disabled or the VGA jumper set to disabled on coreboot, while it works on vendor in any case. The reason for this is still unclear. Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware instead of just PC3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I3933a219b77d7234af273217df031cf627b4071f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/skylake/romstage/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 5e0d687..a7ce2f8 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -173,6 +173,7 @@ dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ m_cfg->Peg0Enable = dev && dev->enabled; if (m_cfg->Peg0Enable) { + m_cfg->Peg0Enable = 2; m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; /* Use maximum possible link speed */ m_cfg->Peg0MaxLinkSpeed = 0; @@ -186,6 +187,7 @@ dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ m_cfg->Peg1Enable = dev && dev->enabled; if (m_cfg->Peg1Enable) { + m_cfg->Peg1Enable = 2; m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; m_cfg->Peg1MaxLinkSpeed = 0; m_cfg->Peg1PowerDownUnusedLanes = 1; @@ -196,6 +198,7 @@ dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ m_cfg->Peg2Enable = dev && dev->enabled; if (m_cfg->Peg2Enable) { + m_cfg->Peg2Enable = 2; m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; m_cfg->Peg2MaxLinkSpeed = 0; m_cfg->Peg2PowerDownUnusedLanes = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/48304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f Gerrit-Change-Number: 48304 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/volteer/var/elemi: use devtree aliases for PMC MUX connectors
by Chen Wisley (Code Review) 07 Dec '20

07 Dec '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48268 ) Change subject: mb/google/volteer/var/elemi: use devtree aliases for PMC MUX connectors ...................................................................... mb/google/volteer/var/elemi: use devtree aliases for PMC MUX connectors refer to cb:45878 Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=none BRANCH=volteer TEST=build and type-c display work Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a --- M src/mainboard/google/volteer/variants/elemi/overridetree.cb 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48268/1 diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index d4c40f9..af58b81 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -183,6 +183,13 @@ device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" @@ -201,14 +208,14 @@ register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a Gerrit-Change-Number: 48268 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: util/cbfstool/.gitignore: Add ifittool
by Arthur Heymans (Code Review) 07 Dec '20

07 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48005 ) Change subject: util/cbfstool/.gitignore: Add ifittool ...................................................................... util/cbfstool/.gitignore: Add ifittool Change-Id: Ie0ee6511e91c0bf1ff2f4ca49b24e3e5a36a06f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/.gitignore 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/48005/1 diff --git a/util/cbfstool/.gitignore b/util/cbfstool/.gitignore index 560d7ea..a63222a 100644 --- a/util/cbfstool/.gitignore +++ b/util/cbfstool/.gitignore @@ -1,5 +1,6 @@ cbfs-compression-tool cbfstool fmaptool +ifittool ifwitool rmodtool -- To view, visit https://review.coreboot.org/c/coreboot/+/48005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0ee6511e91c0bf1ff2f4ca49b24e3e5a36a06f2 Gerrit-Change-Number: 48005 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: soc/amd: move non-CAR linker scripts to common directory
by Felix Held (Code Review) 07 Dec '20

07 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47828 ) Change subject: soc/amd: move non-CAR linker scripts to common directory ...................................................................... soc/amd: move non-CAR linker scripts to common directory AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar. TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries. Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/Kconfig R src/soc/amd/common/block/cpu/noncar/memlayout.ld R src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld R src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc R src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig 6 files changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/47828/1 diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index f6756e1..826f80b 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -11,3 +11,19 @@ This is only used for AMD CPU before family 17h. From family 17h on the RAM is already initialized by the PSP before the x86 cores are released from reset. + +config SOC_AMD_COMMON_BLOCK_NONCAR + bool + default n + help + From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any + more, since the RAM initialization is already done by the PSP when + the x86 cores are released from reset. + +if SOC_AMD_COMMON_BLOCK_NONCAR + +config MEMLAYOUT_LD_FILE + string + default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" + +endif # SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/common/block/cpu/noncar/memlayout.ld similarity index 100% rename from src/soc/amd/picasso/memlayout.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout.ld diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld similarity index 93% rename from src/soc/amd/picasso/memlayout_psp_verstage.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld index ca95cf8..aa27bae 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld @@ -4,6 +4,8 @@ #include <soc/psp_transfer.h> #include <fmap_config.h> +/* TODO: Move defines to SoC-specific header file to allow SoC specific values if needed. */ + /* * Start of available space is 0x15000 and this is where the * header for the user app (verstage) must be mapped. diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc similarity index 100% rename from src/soc/amd/picasso/memlayout_transfer_buffer.inc rename to src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld similarity index 100% rename from src/soc/amd/picasso/memlayout_x86.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d7d2a6..6fa3664 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO @@ -57,10 +58,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS -config MEMLAYOUT_LD_FILE - string - default "src/soc/amd/picasso/memlayout.ld" - config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/47828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Gerrit-Change-Number: 47828 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: mb/supermicro/x11ssm-f: enable AER for PCIe root ports
by Michael Niewöhner (Code Review) 07 Dec '20

07 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48369 ) Change subject: mb/supermicro/x11ssm-f: enable AER for PCIe root ports ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e Gerrit-Change-Number: 48369 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Dec 2020 11:55:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices
by Michael Niewöhner (Code Review) 07 Dec '20

07 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48368 ) Change subject: mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d Gerrit-Change-Number: 48368 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Dec 2020 11:55:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: enable LTR for all root ports
by Michael Niewöhner (Code Review) 07 Dec '20

07 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48367 ) Change subject: mb/supermicro/x11ssm-f: enable LTR for all root ports ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c Gerrit-Change-Number: 48367 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Dec 2020 11:55:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads
by Michael Niewöhner (Code Review) 07 Dec '20

07 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48100 ) Change subject: mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads ...................................................................... Patch Set 14: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06b942e3182469f87e41914c893e5b485ccca420 Gerrit-Change-Number: 48100 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 07 Dec 2020 11:54:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2020