coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/cannonlake: Restore alphabetical order of Kconfig selects
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48396 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Restore alphabetical order of Kconfig selects ...................................................................... soc/intel/cannonlake: Restore alphabetical order of Kconfig selects Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/48396/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753 Gerrit-Change-Number: 48396 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/*: Remove SATA mode config for CNL based mainboards
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Hello build bot (Jenkins), Matt DeVillier, Jeremy Soller, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48391 to look at the new patch set (#4). Change subject: mb/*: Remove SATA mode config for CNL based mainboards ...................................................................... mb/*: Remove SATA mode config for CNL based mainboards SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/48391/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Gerrit-Change-Number: 48391 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Align SATA mode names with soc/skl
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Hello build bot (Jenkins), Matt DeVillier, Jeremy Soller, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48390 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Align SATA mode names with soc/skl ...................................................................... soc/intel/cannonlake: Align SATA mode names with soc/skl Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/chip.h 7 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/48390/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Gerrit-Change-Number: 48390 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/*: Remove SATA mode config for CNL based mainboards
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48391 ) Change subject: mb/*: Remove SATA mode config for CNL based mainboards ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Gerrit-Change-Number: 48391 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 21:00:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Align SATA mode names with soc/skl
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48390 ) Change subject: soc/intel/cannonlake: Align SATA mode names with soc/skl ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Gerrit-Change-Number: 48390 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 21:00:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*: Remove SATA_AHCI config from SKL/KBL based devicetrees
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48378 ) Change subject: mb/*: Remove SATA_AHCI config from SKL/KBL based devicetrees ...................................................................... mb/*: Remove SATA_AHCI config from SKL/KBL based devicetrees SATA_AHCI is already the default mode for SKL/KBL based platforms. Therefore, remove its configuration from all related devicetrees. Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: Ib5222c1b0314365b634f8585e8a97e0054127fe9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48378/1 diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index f65a3d3..a223b7e 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -80,7 +80,6 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" # Ports register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 9b3b8bf..6bdfcaf 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -95,7 +95,6 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 422cd84..76aec3f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -5,7 +5,6 @@ register "SaGv" = "SaGv_Disabled" # SATA configuration - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/48378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5222c1b0314365b634f8585e8a97e0054127fe9 Gerrit-Change-Number: 48378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Shorten SATA mode enum values
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48377 ) Change subject: soc/intel/skylake: Shorten SATA mode enum values ...................................................................... soc/intel/skylake: Shorten SATA mode enum values The Skylake FSP isn't used by coreboot anymore. Therefore, drop the misleading comment and "KBLFSP" extension from the names of these enums. Also, drop the "MODE" extension to make their names shorter in general, since it doesn't add any more value. Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/skylake/chip.h 4 files changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/48377/1 diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 55c5a69..f65a3d3 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -80,7 +80,7 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA - register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" # Ports register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index ef1f0d4..9b3b8bf 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -95,7 +95,7 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA - register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index c021372..422cd84 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -5,7 +5,7 @@ register "SaGv" = "SaGv_Disabled" # SATA configuration - register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0bab45a..58d172f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -142,11 +142,8 @@ /* SATA related */ enum { - /* Documentation and header files of Skylake FSP disagree on - the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses - these: */ - KBLFSP_SATA_MODE_AHCI = 0, - KBLFSP_SATA_MODE_RAID = 1, + SATA_AHCI = 0, + SATA_RAID = 1, } SataMode; u8 SataSalpSupport; u8 SataPortsEnable[8]; -- To view, visit https://review.coreboot.org/c/coreboot/+/48377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0 Gerrit-Change-Number: 48377 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Restore alphabetical order of Kconfig selects
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48376 ) Change subject: soc/intel/skylake: Restore alphabetical order of Kconfig selects ...................................................................... soc/intel/skylake: Restore alphabetical order of Kconfig selects Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/Kconfig 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48376/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 314a08b..3eae5f8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -30,20 +30,20 @@ select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT - select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER + select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select HAVE_INTEL_FSP_REPO select IOAPIC select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 - select REG_SCRIPT - select SA_ENABLE_DPR select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK + select REG_SCRIPT + select SA_ENABLE_DPR select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/48376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13 Gerrit-Change-Number: 48376 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/l140cu: Use lower-case hex values
by Felix Singer (Code Review) 08 Dec '20

08 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48375 ) Change subject: mb/clevo/l140cu: Use lower-case hex values ...................................................................... mb/clevo/l140cu: Use lower-case hex values Change-Id: I56a905980e5ae382c3488b9fddb9fab382efc1d6 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/48375/1 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index acad20c..2e33c34 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -182,9 +182,9 @@ # Address 0x88: Decode 0x68 - 0x6F (PMC) register "gen2_dec" = "0x00040069" # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen3_dec" = "0x00fc0E01" + register "gen3_dec" = "0x00fc0e01" # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen4_dec" = "0x00fc0F01" + register "gen4_dec" = "0x00fc0f01" chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a905980e5ae382c3488b9fddb9fab382efc1d6 Gerrit-Change-Number: 48375 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/chili: Remove unnecessary device declarations
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48374 ) Change subject: mb/siemens/chili: Remove unnecessary device declarations ...................................................................... mb/siemens/chili: Remove unnecessary device declarations Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb 2 files changed, 5 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 196cd81..6bdec65 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -86,8 +86,7 @@ register "PcieRpSlotImplemented[5]" = "0" end device pci 1c.6 on # PCI Express Port 7 - device pci 00.0 on end # x1 M.2 (WLAN / BT) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "1" # x1 M.2 (WLAN / BT) register "PcieRpSlotImplemented[6]" = "1" end device pci 1c.7 off end # PCI Express Port 8 @@ -100,8 +99,7 @@ device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on # PCI Express Port 17 - device pci 00.0 on end # x4 M.2/M - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "1" # x4 M.2/M register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 6c5a306..8595ce8 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -112,8 +112,7 @@ device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC device pci 1c.0 off # PCI Express Port 1 - device pci 00.0 on end # Debug (x1) - register "PcieRpEnable[0]" = "0" + register "PcieRpEnable[0]" = "0" # Debug (x1) register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcClkReq[2]" = "2" end @@ -121,8 +120,7 @@ device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 on # PCI Express Port 5 - device pci 00.0 on end # CORE (x1) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "1" # CORE (x1) register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "1" @@ -157,8 +155,7 @@ device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on # PCI Express Port 17 - device pci 00.0 on end # NVMe (x4) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "1" # NVMe (x4) register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/48374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620 Gerrit-Change-Number: 48374 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit December 2020