coreboot-gerrit December 2020

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Change in coreboot[master]: mb/clevo/l140cu: Remove unnecessary device declarations
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48373 ) Change subject: mb/clevo/l140cu: Remove unnecessary device declarations ...................................................................... mb/clevo/l140cu: Remove unnecessary device declarations Remove unnecessary device declarations and remove comments where SMBIOS slot descriptions are used. Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index b7745a3..5b03f4c 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -141,7 +141,7 @@ device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 chip drivers/wifi/generic - device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) + device pci 00.0 on end end register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" @@ -151,7 +151,6 @@ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end device pci 1d.0 on # PCI Express Port 9 - device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" @@ -163,7 +162,6 @@ device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 - device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" -- To view, visit https://review.coreboot.org/c/coreboot/+/48373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef Gerrit-Change-Number: 48373 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: Use proper indents
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48372 ) Change subject: mb/clevo/l140cu: Use proper indents ...................................................................... mb/clevo/l140cu: Use proper indents Use proper indents in the devicetree and align `end` keywords. Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372 Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 54 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 96d52a4..b7745a3 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -64,16 +64,16 @@ device domain 0 on subsystemid 0x1558 0x1401 inherit - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal device + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device register "Device4Enable" = "1" end - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 @@ -85,15 +85,15 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on # CNVi wifi chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on # I2C #0 + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 chip drivers/i2c/hid register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" @@ -103,16 +103,16 @@ device i2c 15 on end end end - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA register "SataMode" = "Sata_AHCI" register "SataSalpSupport" = "1" # Port 2 (J_SSD2) @@ -122,24 +122,24 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" end - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on # PCI Express Port 6 + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on # PCI Express Port 6 device pci 00.0 on end # x1 Card reader register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" end - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on # PCI Express Port 8 chip drivers/wifi/generic device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) end @@ -150,7 +150,7 @@ register "PcieRpSlotImplemented[7]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end - device pci 1d.0 on # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" @@ -159,10 +159,10 @@ register "PcieRpSlotImplemented[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" @@ -171,14 +171,14 @@ register "PcieRpSlotImplemented[12]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface # LPC configuration from lspci -s 1f.0 -xxx # Address 0x84: Decode 0x80 - 0x8F (Port 80) register "gen1_dec" = "0x000c0081" @@ -192,13 +192,13 @@ device pnp 0c31.0 on end end end - device pci 1f.1 hidden end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on # Intel HDA + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150 Gerrit-Change-Number: 48372 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden
by Michael Niewöhner (Code Review) 08 Dec '20

08 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48371 ) Change subject: mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden ...................................................................... mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden The PCI devices P2SB and PMC are hidden by the FSP. So instead turning them off, set their state to hidden being able to allocate ressources for them. Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48371 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index f861503..96d52a4 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -192,8 +192,8 @@ device pnp 0c31.0 on end end end - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/48371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Gerrit-Change-Number: 48371 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME
by Tim Wawrzynczak (Code Review) 08 Dec '20

08 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48366 ) Change subject: mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 Gerrit-Change-Number: 48366 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 20:47:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Align SATA mode names with soc/skl
by Matt DeVillier (Code Review) 08 Dec '20

08 Dec '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48390 ) Change subject: soc/intel/cannonlake: Align SATA mode names with soc/skl ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Gerrit-Change-Number: 48390 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Dec 2020 20:47:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voxel: Update DPTF parameters
by Sheng-Liang Pan (Code Review) 08 Dec '20

08 Dec '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48264 ) Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ...................................................................... mb/google/volteer/var/voxel: Update DPTF parameters change TCC offset to 10C. BUG=b:174547185 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48264/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 9c4aa47..c60528c 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "tcc_offset" = "5" # TCC of 95 + register "tcc_offset" = "10" # TCC of 90 register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 18, -- To view, visit https://review.coreboot.org/c/coreboot/+/48264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 Gerrit-Change-Number: 48264 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings.
by Stanley Wu (Code Review) 08 Dec '20

08 Dec '20

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48150 ) Change subject: mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings. ...................................................................... mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings. Update lindar gpio settings for Synaptics trackpad no function issue. Update I2C5 bus freq to 400kHz. BUG=b:160013582 TEST=emerge-volteer coreboot and check system dmesg and evtest can get device. Verify trackpad function workable. Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf --- M src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/48150/1 diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c index 4f3d5f7..f99ffbd 100644 --- a/src/mainboard/google/volteer/variants/lindar/gpio.c +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -134,6 +134,9 @@ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E15 : ISH_GP6 ==> NC */ + PAD_NC(GPP_E15, NONE), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 2e61071..7bdb625 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -9,6 +9,44 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 register "SaGv" = "SaGv_Disabled" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + .data_hold_time_ns = 0, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" # I2C Port Config register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/48150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf Gerrit-Change-Number: 48150 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool: Add support for mapping extended window for x86 platforms
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47882 ) Change subject: util/cbfstool: Add support for mapping extended window for x86 platforms ...................................................................... util/cbfstool: Add support for mapping extended window for x86 platforms All x86 platforms until now have memory mapped up to a maximum of 16MiB of SPI flash just below 4G boundary in host address space. For newer platforms, cbfstool needs to be able to accommodate additional windows in the host address space for mapping SPI flash size greater than 16MiB. This change adds two input parameters to cbfstool ext-win-base and ext-win-size which a platform can use to provide the details of the extended window in host address space. The extended window does not necessarily have to be contiguous with the standard decode window below 4G. But, it is left upto the platform to ensure that the fmap sections are defined such that they do not cross the window boundary. create_mmap_windows() uses the input parameters from the platform for the extended window and the flash size to determine if extended mmap window is used. If the entire window in host address space is not covered by the SPI flash region below the top 16MiB, then mapping is assumed to be done at the top of the extended window in host space. BUG=b:171534504 Change-Id: Ie8f95993e9c690e34b0e8e792f9881c81459c6b6 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/cbfstool.c 1 file changed, 90 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47882/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c0f13e7..86bc866 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -93,6 +93,18 @@ char *initrd; char *cmdline; int force; + /* + * Base and size of extended window for decoding SPI flash greater than 16MiB in host + * address space on x86 platforms. The assumptions here are: + * 1. Top 16MiB is still decoded in the fixed decode window just below 4G boundary. + * 2. Rest of the SPI flash below the top 16MiB is mapped at the top of extended + * window. Even though the platform might support a larger extended window, the SPI + * flash part used by the mainboard might not be large enough to be mapped in the entire + * window. In such cases, the mapping is assumed to be in the top part of the extended + * window with the bottom part remaining unused. + */ + uint32_t ext_win_base; + uint32_t ext_win_size; } param = { /* All variables not listed are initialized as zero. */ .arch = CBFS_ARCHITECTURE_UNKNOWN, @@ -124,6 +136,8 @@ enum mmap_window_type { X86_DEFAULT_DECODE_WINDOW, /* Decode window just below 4G boundary */ + X86_EXTENDED_DECODE_WINDOW, /* Extended decode window for mapping greater than 16MiB + flash */ MMAP_MAX_WINDOWS, }; @@ -145,25 +159,69 @@ mmap_window_table[idx].host_space.size = window_size; } -static void create_mmap_windows(void) +static bool create_mmap_windows(void) { static bool done; if (done) - return; + return done; const size_t image_size = partitioned_file_total_size(param.image_file); - const size_t window_size = MIN(16 * MiB, image_size); + const size_t std_window_size = MIN(16 * MiB, image_size); + const size_t std_window_flash_offset = image_size - std_window_size; /* * Default decode window lives just below 4G boundary in host space and maps up to a * maximum of 16MiB. If the window is smaller than 16MiB, the SPI flash window is mapped * at the top of the host window just below 4G. */ - add_mmap_window(X86_DEFAULT_DECODE_WINDOW, image_size - window_size, - 4ULL * GiB - window_size, window_size); + add_mmap_window(X86_DEFAULT_DECODE_WINDOW, std_window_flash_offset, + 4ULL * GiB - std_window_size, std_window_size); + + if (param.ext_win_size && (image_size > 16 * MiB)) { + /* + * If the platform supports extended window and the SPI flash size is greater + * than 16MiB, then create a mapping for the extended window as well. + * The assumptions here are: + * 1. Top 16MiB is still decoded in the fixed decode window just below 4G + * boundary. + * 2. Rest of the SPI flash below the top 16MiB is mapped at the top of extended + * window. Even though the platform might support a larger extended window, the + * SPI flash part used by the mainboard might not be large enough to be mapped + * in the entire window. In such cases, the mapping is assumed to be in the top + * part of the extended window with the bottom part remaining unused. + * + * Example: + * ext_win_base = 0xF8000000 + * ext_win_size = 32 * MiB + * ext_win_limit = ext_win_base + ext_win_size - 1 = 0xF9FFFFFF + * + * If SPI flash is 32MiB, then top 16MiB is mapped from 0xFF000000 - 0xFFFFFFFF + * whereas the bottom 16MiB is mapped from 0xF9000000 - 0xF9FFFFFF. The extended + * window 0xF8000000 - 0xF8FFFFFF remains unused. + */ + const size_t ext_window_mapped_size = MIN(param.ext_win_size, + image_size - std_window_size); + const size_t ext_window_top = param.ext_win_base + param.ext_win_size; + add_mmap_window(X86_EXTENDED_DECODE_WINDOW, + std_window_flash_offset - ext_window_mapped_size, + ext_window_top - ext_window_mapped_size, + ext_window_mapped_size); + + if (region_overlap(&mmap_window_table[X86_EXTENDED_DECODE_WINDOW].host_space, + &mmap_window_table[X86_DEFAULT_DECODE_WINDOW].host_space)) { + const struct region *ext_region; + + ext_region = &mmap_window_table[X86_EXTENDED_DECODE_WINDOW].host_space; + ERROR("Extended window(base=0x%zx, limit=0x%zx) overlaps with default window!\n", + region_offset(ext_region), region_end(ext_region)); + + return false; + } + } done = true; + return done; } static unsigned int convert_address(const struct region *to, const struct region *from, @@ -236,7 +294,7 @@ { assert(region); - create_mmap_windows(); + assert(create_mmap_windows()); if (IS_HOST_SPACE_ADDRESS(addr)) return convert_host_to_flash(region, addr); @@ -1410,6 +1468,8 @@ /* begin after ASCII characters */ LONGOPT_START = 256, LONGOPT_IBB = LONGOPT_START, + LONGOPT_EXT_WIN_BASE, + LONGOPT_EXT_WIN_SIZE, LONGOPT_END, }; @@ -1453,6 +1513,8 @@ {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, {"ibb", no_argument, 0, LONGOPT_IBB }, + {"ext-win-base", required_argument, 0, LONGOPT_EXT_WIN_BASE }, + {"ext-win-size", required_argument, 0, LONGOPT_EXT_WIN_SIZE }, {NULL, 0, 0, 0 } }; @@ -1543,11 +1605,16 @@ " -U Unprocessed; don't decompress or make ELF\n" " -v Provide verbose output\n" " -h Display this help message\n\n" + " --ext-win-base Base of extended decode window in host address\n" + " space(x86 only)\n" + " --ext-win-size Size of extended decode window in host address\n" + " space(x86 only)\n" "COMMANDs:\n" " add [-r image,regions] -f FILE -n NAME -t TYPE [-A hash] \\\n" " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" - " [-j topswap-size] (Intel CPUs only) [--ibb] " + " [-j topswap-size] (Intel CPUs only) [--ibb] \\\n" + " [--ext-win-base win-base --ext-win-size win-size] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1558,7 +1625,8 @@ " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" " [-a alignment] [-P page-size] [-Q|--pow2page] \\\n" - " [-y|--xip] [--ibb] " + " [-y|--xip] [--ibb] \\\n" + " [--ext-win-base win-base --ext-win-size win-size] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1890,6 +1958,20 @@ case LONGOPT_IBB: param.ibb = true; break; + case LONGOPT_EXT_WIN_BASE: + param.ext_win_base = strtoul(optarg, &suffix, 0); + if (!*optarg || (suffix && *suffix)) { + ERROR("Invalid ext window base '%s'.\n", optarg); + return 1; + } + break; + case LONGOPT_EXT_WIN_SIZE: + param.ext_win_size = strtoul(optarg, &suffix, 0); + if (!*optarg || (suffix && *suffix)) { + ERROR("Invalid ext window size '%s'.\n", optarg); + return 1; + } + break; case 'h': case '?': usage(argv[0]); -- To view, visit https://review.coreboot.org/c/coreboot/+/47882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8f95993e9c690e34b0e8e792f9881c81459c6b6 Gerrit-Change-Number: 47882 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 22

Change in coreboot[master]: Add xlate_window
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47658 ) Change subject: Add xlate_window ...................................................................... Add xlate_window Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c M src/soc/intel/apollolake/mmap_boot.c 3 files changed, 78 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47658/1 diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index b9a984f..f8e0de4 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -215,9 +215,14 @@ * space. The sub region is the window within the 1st address space and * the request is modified prior to accessing the second address space * provided by access_dev. */ -struct xlate_region_device { +struct xlate_window { const struct region_device *access_dev; struct region sub_region; +}; + +struct xlate_region_device { + size_t window_count; + const struct xlate_window *window_arr; struct region_device rdev; }; @@ -225,36 +230,28 @@ extern const struct region_device_ops xlate_rdev_rw_ops; -#define XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_, ops_) \ +#define XLATE_REGION_DEV_INIT(window_count_, window_arr_, parent_sz_, ops_) \ { \ - .access_dev = access_dev_, \ - .sub_region = { \ - .offset = (sub_offset_), \ - .size = (sub_size_), \ - }, \ + .window_count = window_count_, \ + .window_arr = window_arr_, \ .rdev = REGION_DEV_INIT((ops_), 0, (parent_sz_)), \ } -#define XLATE_REGION_DEV_RO_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_) \ - XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ - sub_size_, parent_sz_, &xlate_rdev_ro_ops), \ +#define XLATE_REGION_DEV_RO_INIT(window_count_, window_arr_, parent_sz_) \ + XLATE_REGION_DEV_INIT(window_count_, window_arr_, \ + parent_sz_, &xlate_rdev_ro_ops), \ -#define XLATE_REGION_DEV_RW_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_) \ - XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ - sub_size_, parent_sz_, &xlate_rdev_rw_ops), \ +#define XLATE_REGION_DEV_RW_INIT(window_count_, window_arr_, parent_sz_) \ + XLATE_REGION_DEV_INIT(window_count_, window_arr_, \ + parent_sz_, &xlate_rdev_rw_ops), \ /* Helper to dynamically initialize xlate region device. */ void xlate_region_device_ro_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size); void xlate_region_device_rw_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size); /* This type can be used for incoherent access where the read and write diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 467e8ff..ece8848 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -188,33 +188,29 @@ static void xlate_region_device_init(struct xlate_region_device *xdev, const struct region_device_ops *ops, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { memset(xdev, 0, sizeof(*xdev)); - xdev->access_dev = access_dev; - xdev->sub_region.offset = sub_offset; - xdev->sub_region.size = sub_size; + xdev->window_count = window_count; + xdev->window_arr = window_arr; region_device_init(&xdev->rdev, ops, 0, parent_size); } void xlate_region_device_ro_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { - xlate_region_device_init(xdev, &xlate_rdev_ro_ops, access_dev, - sub_offset, sub_size, parent_size); + xlate_region_device_init(xdev, &xlate_rdev_ro_ops, window_count, window_arr, + parent_size); } void xlate_region_device_rw_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { - xlate_region_device_init(xdev, &xlate_rdev_rw_ops, access_dev, - sub_offset, sub_size, parent_size); + xlate_region_device_init(xdev, &xlate_rdev_rw_ops, window_count, window_arr, + parent_size); } static void *mdev_mmap(const struct region_device *rd, size_t offset, @@ -321,6 +317,21 @@ return 0; } +static const struct xlate_window *xlate_find_window(const struct xlate_region_device *xldev, + const struct region *req) +{ + size_t i; + const struct xlate_window *xlwindow; + + for (i = 0; i < xldev->window_count; i++) { + xlwindow = &xldev->window_arr[i]; + if (region_is_subregion(&xlwindow->sub_region, req)) + return xlwindow; + } + + return NULL; +} + static void *xlate_mmap(const struct region_device *rd, size_t offset, size_t size) { @@ -329,24 +340,22 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return NULL; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_mmap(xldev->access_dev, offset, size); + return rdev_mmap(xlwindow->access_dev, offset, size); } -static int xlate_munmap(const struct region_device *rd, void *mapping) +static int xlate_munmap(const struct region_device *rd __unused, void *mapping __unused) { - const struct xlate_region_device *xldev; - - xldev = container_of(rd, __typeof__(*xldev), rdev); - - return rdev_munmap(xldev->access_dev, mapping); + return 0; } static ssize_t xlate_readat(const struct region_device *rd, void *b, @@ -356,16 +365,18 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_readat(xldev->access_dev, b, offset, size); + return rdev_readat(xlwindow->access_dev, b, offset, size); } static ssize_t xlate_writeat(const struct region_device *rd, const void *b, @@ -375,16 +386,18 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_writeat(xldev->access_dev, b, offset, size); + return rdev_writeat(xlwindow->access_dev, b, offset, size); } static ssize_t xlate_eraseat(const struct region_device *rd, @@ -394,16 +407,18 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_eraseat(xldev->access_dev, offset, size); + return rdev_eraseat(xlwindow->access_dev, offset, size); } const struct region_device_ops xlate_rdev_ro_ops = { diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 30c629e..775354d 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -43,6 +43,7 @@ static struct mem_region_device shadow_dev; static struct xlate_region_device real_dev; +static struct xlate_window real_dev_window; static void bios_mmap_init(void) { @@ -68,17 +69,26 @@ mem_region_device_ro_init(&shadow_dev, (void *)base, bios_mapped_size); - xlate_region_device_ro_init(&real_dev, &shadow_dev.rdev, - start, bios_mapped_size, - CONFIG_ROM_SIZE); + real_dev_window.access_dev = &shadow_dev.rdev; + real_dev_window.sub_region.offset = start; + real_dev_window.sub_region.size = bios_mapped_size; + + xlate_region_device_ro_init(&real_dev, 1, &real_dev_window, CONFIG_ROM_SIZE); bios_size = size; /* Check that the CBFS lies within the memory mapped area. It's too easy to forget the SRAM mapping when crafting an FMAP file. */ struct region cbfs_region; - if (!fmap_locate_area("COREBOOT", &cbfs_region) && - !region_is_subregion(&real_dev.sub_region, &cbfs_region)) + void *map; + + if (fmap_locate_area("COREBOOT", &cbfs_region)) + return; + + map = rdev_mmap(&real_dev.rdev, region_offset(&cbfs_region), region_sz(&cbfs_region)); + if (map) + rdev_munmap(&real_dev.rdev, map); + else printk(BIOS_CRIT, "ERROR: CBFS @ %zx size %zx exceeds mem-mapped area @ %zx size %zx\n", region_offset(&cbfs_region), region_sz(&cbfs_region), -- To view, visit https://review.coreboot.org/c/coreboot/+/47658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651 Gerrit-Change-Number: 47658 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: util/cbfstool/fmaptool: Generate list of terminal sections
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47883 ) Change subject: util/cbfstool/fmaptool: Generate list of terminal sections ...................................................................... util/cbfstool/fmaptool: Generate list of terminal sections This change adds support in fmaptool to generate a macro in C header file that provides a list of section names that do not have any subsections. This is useful for performing build time tests on these sections. BUG=b:171534504 Change-Id: Ie32bb8af4a722d329f9d4729722b131ca352d47a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/fmaptool.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47883/1 diff --git a/util/cbfstool/fmaptool.c b/util/cbfstool/fmaptool.c index 9f5803d..4ba5967 100644 --- a/util/cbfstool/fmaptool.c +++ b/util/cbfstool/fmaptool.c @@ -14,6 +14,12 @@ #define HEADER_FMAP_OFFSET "FMAP_OFFSET" #define HEADER_FMAP_SIZE "FMAP_SIZE" +/* + * Macro name used in the generated C header file to provide list of section names that do not + * have any sub-sections. + */ +#define HEADER_FMAP_TERMINAL_SECTIONS "FMAP_TERMINAL_SECTIONS" + enum fmaptool_return { FMAPTOOL_EXIT_SUCCESS = 0, FMAPTOOL_EXIT_BAD_ARGS, @@ -71,6 +77,20 @@ fputc('\n', out); } +static void write_header_fmap_terminal_section_names(FILE *header, + const struct flashmap_descriptor *root) +{ + assert(root); + + if (root->list_len == 0) { + fprintf(header, "%s ", root->name); + return; + } + + fmd_foreach_child(child, root) + write_header_fmap_terminal_section_names(header, child); +} + static void write_header_fmap_sections(FILE *header, const struct flashmap_descriptor *root, unsigned int offset) { @@ -116,6 +136,10 @@ fprintf(header, "#define %s %#x\n", HEADER_FMAP_OFFSET, fmap_offset); fprintf(header, "#define %s %#x\n\n", HEADER_FMAP_SIZE, fmap_size); + fprintf(header, "#define %s \"", HEADER_FMAP_TERMINAL_SECTIONS); + write_header_fmap_terminal_section_names(header, root); + fprintf(header, "\"\n\n"); + write_header_fmap_sections(header, root, 0); fputs("\n", header); -- To view, visit https://review.coreboot.org/c/coreboot/+/47883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32bb8af4a722d329f9d4729722b131ca352d47a Gerrit-Change-Number: 47883 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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