coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Sridhar Siricilla (Code Review) 09 Dec '20

09 Dec '20

Hello build bot (Jenkins), Jamie Ryu, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48281 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage This patch sets up cse_fw_sync() call in the romstage. BUG=b:174694480 Test=Verified on Tigerlake platform Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 --- M src/soc/intel/tigerlake/romstage/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/48281/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the...
by Sridhar Siricilla (Code Review) 09 Dec '20

09 Dec '20

Hello build bot (Jenkins), Jamie Ryu, Sugnan Prabhu S, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48280 to look at the new patch set (#2). Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage ...................................................................... soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage This patch sets up cse_fw_sync() call in the romstage. BUG=b:174694480 Test=Verified on Drawlet Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a --- M src/soc/intel/jasperlake/romstage/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48280/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Gerrit-Change-Number: 48280 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Move CSE Lite driver functionality into romstage
by Sridhar Siricilla (Code Review) 09 Dec '20

09 Dec '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Jamie Ryu, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48279 to look at the new patch set (#2). Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage ...................................................................... soc/intel/common: Move CSE Lite driver functionality into romstage The patch sets up the CSE Lite driver in the romstage instead of ramstage. With this change, CSE Lite driver sets CSE's boot partition and triggeres CSE FW update in the romstage. Test=Verified on JSL and TGL platforms BUG=b:174694480 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48279/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Gerrit-Change-Number: 48279 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad
by Tim Chen (Code Review) 08 Dec '20

08 Dec '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47441 to review the following change. Change subject: mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad ...................................................................... mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad Add Elan and Synaptics touchpad settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47441/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 73ef0b8..8eb9570 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -43,7 +43,25 @@ }" device domain 0 on - device pci 15.0 on end + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 device pci 15.2 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/47441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c Gerrit-Change-Number: 47441 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Add audio related settings
by Tim Chen (Code Review) 08 Dec '20

08 Dec '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47438 to review the following change. Change subject: mb/google/dedede/var/metaknight: Add audio related settings ...................................................................... mb/google/dedede/var/metaknight: Add audio related settings Add HDA,speaker codec and speaker amp settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0 Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47438/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 25bc866..73ef0b8 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -80,5 +80,31 @@ end end # I2C 2 device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/47438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0 Gerrit-Change-Number: 47438 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/google/volteer: Use device aliases
by Duncan Laurie (Code Review) 08 Dec '20

08 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44039 ) Change subject: [WIP] mb/google/volteer: Use device aliases ...................................................................... [WIP] mb/google/volteer: Use device aliases Use the device aliases provided by tigerlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for volteer. Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb 2 files changed, 36 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44039/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 53bbe5a..80e2041 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -47,7 +47,6 @@ register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 @@ -286,10 +285,8 @@ }" device domain 0 on - #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref igpu on end + device ref dptf on # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf ## Active Policy @@ -379,81 +376,35 @@ device generic 0 on end end end # DPTF 0x9A03 - device pci 05.0 off end # IPU 0x9A19 - device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 08.0 on end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B - - # From PCH EDS(576591) - device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - - device pci 12.0 off end # SensorHUB 0xA0FC - device pci 12.6 off end # GSPI2 0x34FB - - device pci 13.0 off end # GSPI3 0xA0FD - - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 off end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref gna on end + device ref north_xhci on end + device ref tbt_dma0 on end + device ref cnvi_bt on end + device ref south_xhci on end + device ref shared_ram on end chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + device ref cnvi_wifi on end end - device pci 15.0 on end # I2C #0 0xA0E8 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - - device pci 17.0 on end # SATA 0xA0D3 - - device pci 19.0 on end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 off end # UART2 0xA0C7 - - device pci 1c.0 on end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 off end # RP3 0xA0BA - device pci 1c.3 off end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # WWAN RP6 0xA0BD - device pci 1c.6 on end # RP7 0xA0BE - device pci 1c.7 on end # SD Card RP8 0xA0BF - - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - - device pci 1e.0 on end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -462,18 +413,12 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 off end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c7350cb..8c95956 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -44,7 +44,7 @@ }, }" device domain 0 on - device pci 15.0 on + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -81,7 +81,7 @@ end end end - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -124,8 +124,8 @@ register "key.label" = ""pen_eject"" device generic 0 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -156,8 +156,8 @@ register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -166,8 +166,8 @@ register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" @@ -197,7 +197,7 @@ end end end - device pci 1f.2 hidden + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -230,6 +230,6 @@ end end end - end # PMC + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/44039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Gerrit-Change-Number: 44039 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/southbridge: drop unused sb_enable
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48440 ) Change subject: soc/amd/picasso/southbridge: drop unused sb_enable ...................................................................... soc/amd/picasso/southbridge: drop unused sb_enable Change-Id: I10a16c8f9db994ff33407619a7ab6e453b026b15 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/include/soc/southbridge.h 2 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48440/1 diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 895a379..cda509b 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -95,11 +95,6 @@ misc_write32(MISC_CLK_CNTL1, ctrl); } -void sb_enable(struct device *dev) -{ - printk(BIOS_DEBUG, "%s\n", __func__); -} - static void sb_init_acpi_ports(void) { u32 reg; diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a74e91f..08e2428 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -197,7 +197,6 @@ void enable_aoac_devices(void); void wait_for_aoac_enabled(unsigned int dev); void sb_clk_output_48Mhz(void); -void sb_enable(struct device *dev); void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void fch_pre_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/48440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a16c8f9db994ff33407619a7ab6e453b026b15 Gerrit-Change-Number: 48440 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: split southbridge into bootblock and ramstage code
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48439 ) Change subject: soc/amd/picasso: split southbridge into bootblock and ramstage code ...................................................................... soc/amd/picasso: split southbridge into bootblock and ramstage code The ramstage parts gets renamed to fch.c and the bootblock one to early_fch.c. No functionality from the old southbridge file is used in romstage, so don't link it there. Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/early_fch.c R src/soc/amd/picasso/fch.c 3 files changed, 61 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/48439/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9c3720b..6e1d88b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -13,7 +13,7 @@ bootblock-y += bootblock.c bootblock-y += aoac.c -bootblock-y += southbridge.c +bootblock-y += early_fch.c bootblock-y += i2c.c bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c @@ -28,7 +28,6 @@ romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c romstage-y += aoac.c -romstage-y += southbridge.c romstage-y += psp.c romstage-y += mrc_cache.c @@ -49,7 +48,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += aoac.c -ramstage-y += southbridge.c +ramstage-y += fch.c ramstage-y += reset.c ramstage-y += acp.c ramstage-y += sata.c diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c new file mode 100644 index 0000000..f56a758 --- /dev/null +++ b/src/soc/amd/picasso/early_fch.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/espi.h> +#include <amdblocks/lpc.h> +#include <amdblocks/smbus.h> +#include <amdblocks/spi.h> +#include <console/console.h> +#include <soc/i2c.h> +#include <soc/southbridge.h> +#include <soc/uart.h> +#include <types.h> + +static void lpc_configure_decodes(void) +{ + if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) + lpc_enable_port80(); +} + +/* Before console init */ +void fch_pre_init(void) +{ + lpc_early_init(); + + if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + lpc_configure_decodes(); + + fch_spi_early_init(); + enable_acpimmio_decode_pm04(); + fch_smbus_init(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); + enable_aoac_devices(); + sb_reset_i2c_slaves(); + + /* + * On reset Range_0 defaults to enabled. We want to start with a clean + * slate to not have things unexpectedly enabled. + */ + clear_uart_legacy_config(); + + if (CONFIG(PICASSO_CONSOLE_UART)) + set_uart_config(CONFIG_UART_FOR_CONSOLE); +} + +/* After console init */ +void fch_early_init(void) +{ + fch_print_pmxc0_status(); + i2c_soc_early_init(); + + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) + lpc_disable_spi_rom_sharing(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + espi_setup(); + espi_configure_decodes(); + } +} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/fch.c similarity index 86% rename from src/soc/amd/picasso/southbridge.c rename to src/soc/amd/picasso/fch.c index 03c424e..895a379 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/fch.c @@ -14,18 +14,13 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> -#include <amdblocks/espi.h> -#include <amdblocks/lpc.h> #include <amdblocks/acpi.h> -#include <amdblocks/smbus.h> -#include <amdblocks/spi.h> #include <amdblocks/smi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include <soc/smi.h> -#include <soc/uart.h> #include <soc/amd_pci_int_defs.h> #include <soc/pci_devs.h> #include <soc/nvs.h> @@ -100,53 +95,6 @@ misc_write32(MISC_CLK_CNTL1, ctrl); } -static void lpc_configure_decodes(void) -{ - if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) - lpc_enable_port80(); -} - -/* Before console init */ -void fch_pre_init(void) -{ - lpc_early_init(); - - if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - lpc_configure_decodes(); - - fch_spi_early_init(); - enable_acpimmio_decode_pm04(); - fch_smbus_init(); - fch_enable_cf9_io(); - fch_enable_legacy_io(); - enable_aoac_devices(); - sb_reset_i2c_slaves(); - - /* - * On reset Range_0 defaults to enabled. We want to start with a clean - * slate to not have things unexpectedly enabled. - */ - clear_uart_legacy_config(); - - if (CONFIG(PICASSO_CONSOLE_UART)) - set_uart_config(CONFIG_UART_FOR_CONSOLE); -} - -/* After console init */ -void fch_early_init(void) -{ - fch_print_pmxc0_status(); - i2c_soc_early_init(); - - if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) - lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { - espi_setup(); - espi_configure_decodes(); - } -} - void sb_enable(struct device *dev) { printk(BIOS_DEBUG, "%s\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/48439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8 Gerrit-Change-Number: 48439 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: select common ACPIMMIO block
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48438 ) Change subject: soc/amd/cezanne: select common ACPIMMIO block ...................................................................... soc/amd/cezanne: select common ACPIMMIO block Change-Id: I7f7d11d84733a43500b0135e565d91fe5c493279 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48438/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 914384b..2a26d6d 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -15,6 +15,7 @@ select ARCH_RAMSTAGE_X86_32 select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H -- To view, visit https://review.coreboot.org/c/coreboot/+/48438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f7d11d84733a43500b0135e565d91fe5c493279 Gerrit-Change-Number: 48438 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/amd: factor out functionality to print last reset source
by Felix Held (Code Review) 08 Dec '20

08 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48437 ) Change subject: soc/amd: factor out functionality to print last reset source ...................................................................... soc/amd: factor out functionality to print last reset source Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/acpimmio/Makefile.inc A src/soc/amd/common/block/acpimmio/print_reset_status.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 7 files changed, 63 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/48437/1 diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index c93e67d..8981231 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -10,4 +10,6 @@ ramstage-y += biosram.c smm-y += biosram.c +bootblock-y += print_reset_status.c + endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c new file mode 100644 index 0000000..3825753 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <amdblocks/acpimmio.h> + +static void print_num_status_bits(int num_bits, uint32_t status, + const char *const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +void fch_print_pmxc0_status(void) +{ + /* PMxC0 S5/Reset Status shows the source of previous reset. */ + uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); + + static const char *const pmxc0_status_bits[32] = { + [0] = "ThermalTrip", + [1] = "FourSecondPwrBtn", + [2] = "Shutdown", + [3] = "ThermalTripFromTemp", + [4] = "RemotePowerDownFromASF", + [5] = "ShutDownFan0", + [16] = "UserRst", + [17] = "SoftPciRst", + [18] = "DoInit", + [19] = "DoReset", + [20] = "DoFullReset", + [21] = "SleepReset", + [22] = "KbReset", + [23] = "LtReset", + [24] = "FailBootRst", + [25] = "WatchdogIssueReset", + [26] = "RemoteResetFromASF", + [27] = "SyncFlood", + [28] = "HangReset", + [29] = "EcWatchdogRst", + }; + + printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); + print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, pmxc0_status_bits); + printk(BIOS_DEBUG, "\n"); +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 0e42ee6..4fcaa92 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -20,6 +20,7 @@ #define SMBUS_ASF_IO_EN (1 << 4) #define CF9_IO_EN (1 << 1) #define LEGACY_IO_EN (1 << 0) +#define PM_RST_STATUS 0xc0 /* * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs @@ -85,6 +86,9 @@ void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); +/* Print source of last reset */ +void fch_print_pmxc0_status(void); + static inline uint8_t sm_pci_read8(uint8_t reg) { return read8(acpimmio_sm_pci + reg); diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 13ef53f..a74e91f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -78,7 +78,6 @@ #define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) -#define PM_RST_STATUS 0xc0 #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 3110dea..03c424e 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -132,62 +132,10 @@ set_uart_config(CONFIG_UART_FOR_CONSOLE); } -static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static void sb_print_pmxc0_status(void) -{ - /* PMxC0 S5/Reset Status shows the source of previous reset. */ - uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); - - static const char *const pmxc0_status_bits[32] = { - [0] = "ThermalTrip", - [1] = "FourSecondPwrBtn", - [2] = "Shutdown", - [3] = "ThermalTripFromTemp", - [4] = "RemotePowerDownFromASF", - [5] = "ShutDownFan0", - [16] = "UserRst", - [17] = "SoftPciRst", - [18] = "DoInit", - [19] = "DoReset", - [20] = "DoFullReset", - [21] = "SleepReset", - [22] = "KbReset", - [23] = "LtReset", - [24] = "FailBootRst", - [25] = "WatchdogIssueReset", - [26] = "RemoteResetFromASF", - [27] = "SyncFlood", - [28] = "HangReset", - [29] = "EcWatchdogRst", - }; - - printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); - print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, - pmxc0_status_bits); - printk(BIOS_DEBUG, "\n"); -} - /* After console init */ void fch_early_init(void) { - sb_print_pmxc0_status(); + fch_print_pmxc0_status(); i2c_soc_early_init(); if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 0a5832b..eb5f3e4 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -72,7 +72,6 @@ #define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) -#define PM_RST_STATUS 0xc0 #define PM_PCIB_CFG 0xea #define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 46fdeb2..fc7a09e 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -344,62 +344,10 @@ enable_aoac_devices(); } -static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static void sb_print_pmxc0_status(void) -{ - /* PMxC0 S5/Reset Status shows the source of previous reset. */ - uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); - - static const char *const pmxc0_status_bits[32] = { - [0] = "ThermalTrip", - [1] = "FourSecondPwrBtn", - [2] = "Shutdown", - [3] = "ThermalTripFromTemp", - [4] = "RemotePowerDownFromASF", - [5] = "ShutDownFan0", - [16] = "UserRst", - [17] = "SoftPciRst", - [18] = "DoInit", - [19] = "DoReset", - [20] = "DoFullReset", - [21] = "SleepReset", - [22] = "KbReset", - [23] = "LtReset", - [24] = "FailBootRst", - [25] = "WatchdogIssueReset", - [26] = "RemoteResetFromASF", - [27] = "SyncFlood", - [28] = "HangReset", - [29] = "EcWatchdogRst", - }; - - printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); - print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, - pmxc0_status_bits); - printk(BIOS_DEBUG, "\n"); -} - /* After console init */ void bootblock_fch_init(void) { - sb_print_pmxc0_status(); + fch_print_pmxc0_status(); } void sb_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/48437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937 Gerrit-Change-Number: 48437 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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