Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48470 )
Change subject: soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset defines
......................................................................
soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset defines
The two Socs don't use this functionality and biosram.c in the common
code is the only place where those defines are used, but it doesn't
include soc/iomap.h and has its own definitions instead.
Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/picasso/include/soc/iomap.h
M src/soc/amd/stoneyridge/include/soc/iomap.h
2 files changed, 0 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48470/1
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index a49768f..cec3aaf 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -85,9 +85,4 @@
#define AB_DATA (AB_INDX+4)
#define SYS_RESET 0xcf9
-/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
-#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */
-#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */
-#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
-
#endif /* AMD_PICASSO_IOMAP_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 4328880..f39200f 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -46,9 +46,4 @@
#define AB_DATA (AB_INDX+4)
#define SYS_RESET 0xcf9
-/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
-#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */
-#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */
-#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
-
#endif /* AMD_STONEYRIDGE_IOMAP_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456
Gerrit-Change-Number: 48470
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48405 )
Change subject: [WIP] soc/amd: Remove Kconfig X86_RESET_VECTOR
......................................................................
[WIP] soc/amd: Remove Kconfig X86_RESET_VECTOR
The architectural requirement is for the address to be
located at the end of bootblock -0x10 bytes, so the
definition was redundant with other Kconfig variables.
Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
M src/soc/amd/picasso/Kconfig
2 files changed, 3 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/48405/1
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 2ae72e3..e595065 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -84,7 +84,6 @@
#if CONFIG(VBOOT)
PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
#endif
- _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
_ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
@@ -105,10 +104,11 @@
SECTIONS {
/* Trigger an error if I have an unusable start address */
- _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
+ _TOO_LOW = _X86_RESET_VECTOR - 0xfff0;
_bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
- . = CONFIG_X86_RESET_VECTOR;
+ . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10;
+ _X86_RESET_VECTOR = .;
.reset . : {
*(.reset);
. = 15;
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 79fc3be..fcb7ddb 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -134,15 +134,6 @@
This variable controls the DRAM allocation size in linker script
for bootblock stage.
-config X86_RESET_VECTOR
- hex
- depends on ARCH_X86
- default 0x203fff0
- help
- Sets the reset vector within bootblock where x86 starts execution.
- Reset vector is supposed to live at offset -0x10 from end of
- bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10.
-
config ROMSTAGE_ADDR
hex
default 0x2040000
--
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Gerrit-Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137
Gerrit-Change-Number: 48405
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-MessageType: newchange
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48186 )
Change subject: soc/intel/tigerlake: Enable support for extended BIOS window
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48186/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/48186/4//COMMIT_MSG@13
PS4, Line 13: BUG=b:171534504
> Waiting to land the earlier patches in chromium tree and then I will cherry-pick rest of the changes […]
Added the Cq-Depend.
--
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Gerrit-Change-Id: I039155506380310cf867f5f8c5542278be40838a
Gerrit-Change-Number: 48186
Gerrit-PatchSet: 5
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
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Gerrit-Comment-Date: Wed, 09 Dec 2020 14:22:53 +0000
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