coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 09 Dec '20

09 Dec '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 68: (7 comments) https://review.coreboot.org/c/coreboot/+/27369/67//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/27369/67//COMMIT_MSG@27 PS67, Line 27: register > nit: PCR register Done https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/Kconfig: https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 6: select > maybe depends on is better? That way you are a bit more aware in the soc code which dependency you p […] Done https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 111: if (rdev_writeat(staging_rdev, cbfs_microcode, 0, : get_microcode_size(cbfs_microcode)) < 0) { : printk(BIOS_ERR, "ucode: Failed to write microcode to staging area\n"); : return UCODE_FWU_STAGING_WRITE_ERROR; : } > If the MCU is bigger than the staging area this will fail but it might be a good idea to be more ver […] Done https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 162: tatic int > use the return type enum ucode_fwu_failure_reason (Add success to the enum?)? Done https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 211: stagin > staging Done https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 260: BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ucode_fw_sync, NULL); > Can this be done as part of coreboot_init_cpus() and somehow avoid calling intel_microcode_find() tw […] This will be moved as part of intel_fw_update where coreboot triggers CSE FW Update and UCODE Update. https://review.coreboot.org/c/coreboot/+/46819/6/src/soc/intel/common/basec… This is required to consolidate number of resets required as part of FW Update. https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h: https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 6: /* : * This is a weak implementation to reboot after ucode update is finished. : * This can be overridden by mainboard/SoC specific implementation. : */ : void ucode_reboot_platform(void); : : /* : * This is a weak implementation for the ucode update module to know if receovery mdoe is : * enabled. This returns non-zero if recovery mode enabled and can be overridden by : * mainboard/SoC specific implementation. : */ : int ucode_update_rec_mode_enabled(void); > What kind of override do you plan to implement? Maybe keep it non weak for now and change that when […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 68 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Wed, 09 Dec 2020 17:17:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 09 Dec '20

09 Dec '20

Sugnan Prabhu S has uploaded a new patch set (#68) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC (BUC) PCR register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 8 files changed, 705 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/68 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 68 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Add initial PCH lockdown
by Arthur Heymans (Code Review) 09 Dec '20

09 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48509 ) Change subject: soc/intel/xeon_sp: Add initial PCH lockdown ...................................................................... soc/intel/xeon_sp: Add initial PCH lockdown TESTED: on ocp/deltalake Change-Id: I287819471762e2eba038597868f8d10935ea9fd4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/pch/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/lpc.c 3 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48509/1 diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6..1125f29 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -12,10 +12,17 @@ if SOC_INTEL_COMMON_PCH_BASE +config SOC_INTEL_NO_ALL_PCH_OPTIONS + bool + help + Select this if you want to be more selective about the common code + you wish to include. + source "src/soc/intel/common/pch/*/Kconfig" config PCH_SPECIFIC_OPTIONS - def_bool y + bool + default y if !SOC_INTEL_NO_ALL_PCH_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..c573ebe 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -44,6 +44,7 @@ select SOC_INTEL_COMMON_BLOCK_LPC select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT @@ -54,6 +55,9 @@ select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_TCO + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_PCH_LOCKDOWN + select SOC_INTEL_NO_ALL_PCH_OPTIONS select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..c3d7092 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -4,6 +4,7 @@ #include <arch/ioapic.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelpch/lockdown.h> #include <soc/iomap.h> #include <soc/pcr_ids.h> @@ -50,3 +51,7 @@ void pch_lpc_soc_fill_io_resources(struct device *dev) { } + +void soc_lockdown_config(int chipset_lockdown) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I287819471762e2eba038597868f8d10935ea9fd4 Gerrit-Change-Number: 48509 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset defines
by Felix Held (Code Review) 09 Dec '20

09 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48470 ) Change subject: soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset defines ...................................................................... soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset defines The two Socs don't use this functionality and biosram.c in the common code is the only place where those defines are used, but it doesn't include soc/iomap.h and has its own definitions instead. Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/iomap.h 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48470/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index a49768f..cec3aaf 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -85,9 +85,4 @@ #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 -/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ -#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ -#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ -#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ - #endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 4328880..f39200f 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -46,9 +46,4 @@ #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 -/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ -#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ -#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ -#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ - #endif /* AMD_STONEYRIDGE_IOMAP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456 Gerrit-Change-Number: 48470 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
by Raul Rangel (Code Review) 09 Dec '20

09 Dec '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48309 ) Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104 ...................................................................... soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104 The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x data width, sampled on each clock edge = 104 MiB/s. BUG=b:159823235 BRANCH=zork TEST=build zork Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/soc/amd/picasso/include/soc/platform_descriptors.h 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48309/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index a39549e..2a385ce 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -164,7 +164,7 @@ SD_EMMC_SD_UHS_I_SDR_104, SD_EMMC_EMMC_SDR_26, SD_EMMC_EMMC_SDR_52, - SD_EMMC_EMMC_DDR_52, + SD_EMMC_EMMC_DDR_104, SD_EMMC_EMMC_HS200, SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 95e691d..fe94061 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -38,8 +38,8 @@ case SD_EMMC_EMMC_SDR_52: val = EMMC_SDR_52; break; - case SD_EMMC_EMMC_DDR_52: - val = EMMC_DDR_52; + case SD_EMMC_EMMC_DDR_104: + val = EMMC_DDR_104; break; case SD_EMMC_EMMC_HS200: val = EMMC_HS200; diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 0ea6f2b..0a77061 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -17,7 +17,7 @@ #define SD_UHS_I_SDR_104 5 #define EMMC_SDR_26 6 #define EMMC_SDR_52 7 -#define EMMC_DDR_52 8 +#define EMMC_DDR_104 8 #define EMMC_HS200 9 #define EMMC_HS400 10 #define EMMC_HS300 11 -- To view, visit https://review.coreboot.org/c/coreboot/+/48309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c Gerrit-Change-Number: 48309 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR
by Kyösti Mälkki (Code Review) 09 Dec '20

09 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48406 ) Change subject: [WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR ...................................................................... [WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR. Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 3 files changed, 12 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48406/1 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index e595065..352472e 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -10,6 +10,9 @@ #define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) #define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr) +BOOTBLOCK_END = CONFIG_ROMSTAGE_ADDR; +BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; + /* * * +--------------------------------+ @@ -31,11 +34,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | @@ -84,8 +87,8 @@ #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif - _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); - BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) + _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); + BOOTBLOCK(BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) #if CONFIG(VBOOT_SEPARATE_VERSTAGE) @@ -107,7 +110,7 @@ _TOO_LOW = _X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10; + . = BOOTBLOCK_END - 0x10; _X86_RESET_VECTOR = .; .reset . : { *(.reset); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fcb7ddb..bd9964b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -120,12 +120,6 @@ help Increase this value if preram cbmem console is getting truncated -config BOOTBLOCK_ADDR - hex - default 0x2030000 - help - Sets the address in DRAM where bootblock should be loaded. - config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 259419c..7ca44b0 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -77,11 +77,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * | (86KiB) | * +--------------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/48406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Gerrit-Change-Number: 48406 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: [WIP] soc/amd: Remove Kconfig X86_RESET_VECTOR
by Kyösti Mälkki (Code Review) 09 Dec '20

09 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48405 ) Change subject: [WIP] soc/amd: Remove Kconfig X86_RESET_VECTOR ...................................................................... [WIP] soc/amd: Remove Kconfig X86_RESET_VECTOR The architectural requirement is for the address to be located at the end of bootblock -0x10 bytes, so the definition was redundant with other Kconfig variables. Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig 2 files changed, 3 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/48405/1 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 2ae72e3..e595065 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -84,7 +84,6 @@ #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif - _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) @@ -105,10 +104,11 @@ SECTIONS { /* Trigger an error if I have an unusable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; + _TOO_LOW = _X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - . = CONFIG_X86_RESET_VECTOR; + . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10; + _X86_RESET_VECTOR = .; .reset . : { *(.reset); . = 15; diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 79fc3be..fcb7ddb 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -134,15 +134,6 @@ This variable controls the DRAM allocation size in linker script for bootblock stage. -config X86_RESET_VECTOR - hex - depends on ARCH_X86 - default 0x203fff0 - help - Sets the reset vector within bootblock where x86 starts execution. - Reset vector is supposed to live at offset -0x10 from end of - bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10. - config ROMSTAGE_ADDR hex default 0x2040000 -- To view, visit https://review.coreboot.org/c/coreboot/+/48405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137 Gerrit-Change-Number: 48405 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/common/dmi: Add support for locking down SRL
by Srinidhi N Kaushik (Code Review) 09 Dec '20

09 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48258 ) Change subject: soc/intel/common/dmi: Add support for locking down SRL ...................................................................... soc/intel/common/dmi: Add support for locking down SRL This change adds support to lock down the DMI configuration in dmi_lockdown_cfg() by setting Secure Register Lock (SRL) bit in DMI control register. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f --- M src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/lockdown/lockdown.c 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48258/1 diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h index 55bf20d..8b12602 100644 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -8,6 +8,9 @@ #define PCR_DMI_DMICTL 0x2234 #define PCR_DMI_DMICTL_SRLOCK (1 << 31) +#define PCR_DMI_GCS 0x274C +#define PCR_DMI_GCS_BILD (1 << 0) + /* * Takes base, size and destination ID and configures the GPMR * for accessing the region. diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index b10306e..d9495a4 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -2,6 +2,7 @@ #include <bootstate.h> #include <intelblocks/cfg.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> @@ -9,9 +10,6 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -#define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) - /* * This function will get lockdown config specific to soc. * @@ -40,6 +38,12 @@ * "1b": LPC/eSPI */ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); + + /* + * Set Secure Register Lock (SRL) bit in DMI control register to lock + * DMI configuration. + */ + pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); } static void fast_spi_lockdown_cfg(int chipset_lockdown) -- To view, visit https://review.coreboot.org/c/coreboot/+/48258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f Gerrit-Change-Number: 48258 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/common/dmi: Move DMI defines into DMI driver header
by Srinidhi N Kaushik (Code Review) 09 Dec '20

09 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48257 ) Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ...................................................................... soc/intel/common/dmi: Move DMI defines into DMI driver header Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 --- M src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/tigerlake/bootblock/pch.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48257/1 diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h index b771b22..55bf20d 100644 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -5,6 +5,9 @@ #include <types.h> +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + /* * Takes base, size and destination ID and configures the GPMR * for accessing the region. diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 5c4d1d5..5a63b40 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -11,6 +11,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -36,9 +37,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC -- To view, visit https://review.coreboot.org/c/coreboot/+/48257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 Gerrit-Change-Number: 48257 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/google/volteer: Reorganize FMAP
by Furquan Shaikh (Code Review) 09 Dec '20

09 Dec '20

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48187 ) Change subject: mb/google/volteer: Reorganize FMAP ...................................................................... mb/google/volteer: Reorganize FMAP This change reorganizes FMAP for volteer to make use of the lower 16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to RW_LEGACY. This is now possible because TGL supports memory mapping of BIOS region greater than 16MiB. Following changes are made in chromeos.fmd as part of this: 1. Move RW_SECTION_A and RW_MISC to lower 16MiB. 2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as a placeholder in the lower half of the SPI flash. 3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a larger region for ELOG. 4. Increase WP_RO to 8MiB to allow larger space for firmware screens. GBB size is thus increased to 448KiB. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/volteer/chromeos.fmd 1 file changed, 39 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 64776fe..6f833fe 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -1,48 +1,48 @@ -FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x4ff000 +FLASH 32M { + SI_ALL 5M { + SI_DESC 4K + SI_ME } - SI_BIOS@0x500000 0x1b00000 { - # Place RW_LEGACY at the start of BIOS region such that the rest - # of BIOS regions start at 16MiB boundary. Since this is a 32MiB - # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0xb00000 - RW_SECTION_A@0xb00000 0x5e0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x32ffc0 - RW_FWID_A@0x33ffc0 0x40 - ME_RW_A(CBFS)@0x340000 0x2a0000 + SI_BIOS 27M { + RW_SECTION_A 8M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3M } - RW_SECTION_B@0x10e0000 0x5e0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x32ffc0 - RW_FWID_B@0x33ffc0 0x40 - ME_RW_B(CBFS)@0x340000 0x2a0000 + RW_LEGACY(CBFS) 2M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 192K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 128K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K } - RW_MISC@0x16c0000 0x40000 { - UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - } - RW_ELOG(PRESERVE)@0x30000 0x4000 - RW_SHARED@0x34000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + # Starts at 16M boundary in the SPI flash. + # No region can be placed across the 16M boundary + # because the SPI flash is mapped into separate + # non-contiguous mmap windows + RW_SECTION_B 8M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3M } # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO@0x1700000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Gerrit-Change-Number: 48187 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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